Jitter and timing measurement with CMOS circuits · Compare to oscilloscope measurements more...
Transcript of Jitter and timing measurement with CMOS circuits · Compare to oscilloscope measurements more...
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Jitter and timing measurement withCMOS circuits
K. A. JenkinsIBM T.J. Watson Research Center
with significant help from Anup Jose, Don Beisser, Ken Shepard, and David Heidel
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Timing jitter is increasingly important as computer clock rates increase; jitter limits accuracy of timing measurements
Contemporary circuits demand jitter of a few ps or less
1. Is there some fundamental limit below which jitter in CMOS gates can not be reduced? (eg. Thermal noise)
Experimental determination of jitter limit in 90 nm, 1.2V CMOS inverter delay chain:
If each inverter adds jitter independently to a propagating signal, the variances add, , eg 2=mj2 and jitter will be proportional to the square root of the number of inverters. If added jitter at each stage is correlated, then standard deviations add, eg =mj net is linearly proportional to the number of stages.
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reference
full chain
64 144 256 400 576 784
input
P1
P3
P3
P3
P2
Two experiments: 1) unloaded inverters (FO1)2) heavily loaded inverters (FO11)
Pulsegenerator
oscilloscope
Experimental determination of jitter limit
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reference
selected length
full chain
Sample oscilloscope traces
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01002003004005006007008000
1
2
3
4
5
1.3 V
1.2V
1.1 V
1.0 Vunloaded delay chain
rms jitter (ps)
stage number
Raw jitter data
Measured jitter includes‘scope jitter (addedin quadrature)
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0 100 200 300 400 500 600 700 8000
1
2
3
4
5
1.1V
1.3 V
1.2 V
1.0 V
unloaded delay chain
rms
jitte
r (p
s)
stage number
0 100 200 300 400 500 600 700 8000
5
10
15
20
25
30
35
1.3 V
1.2V
1.0 V1.0 V
1.1 V
loaded delay chain (FO11)
rms
jitte
r (p
s)
stage number
scope jitter subtracted
Unloaded chains (FO1) loaded chains (FO11)
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0 20 40 60 80 100 120 140 160 1800
5
10
15
20
25
30
35
1.3 V
1.2 V
1.1 V
1.0 Vloaded delay chain (FO11)
0.11 ps/ns
rms
jitte
r (ps
)
delay (ns)
0 5 10 15 20 250.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.12ps/ns
1.3V
1.2 V
1.1 V
1.0 Vunloaded delay chain
rms
jitte
r (ps
)
delay (ns)
Jitter per delay (instead of per stage)
jitter/delay~1E4 (0.12 ps/ns)
Traced to residual power supply noise of about 80 to 100 V (rms)
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0.7 0.8 0.9 1.0 1.1 1.2 1.30.00
0.05
0.10
0.15
0.20
0.25
0.30
unloaded delay chainjit
ter/
dela
y (p
s/ns
)
VDD
(V)
Effect of power supply level
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2. Onchip measurement of jitter and skew
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Existing methods:
Time to digital converters:
many latches driven by buffered signal and clock; arrival time is digitized
jitter is obtained by reading latch states repeatedly;
2. Measurement onchip is an attractive way to measure small amounts of jitter (and skew)
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C
D
QC
D
QC
D
QC
D
Q
signal
counter counter counter counter
ref clock
…128 stages
ReferenceRestle et al, ISSCC 2004
Previous work: latched delay line (“Skitter”); resolution ~ stage delay
1 1 0 0Binary code indicates arrival time of signal after clock
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C
D
Q C
D
Q C
D
Q C
D
Q
t1t1t1t1
t2t2t2t2
signal
ref clock
Dudek et al, JSSC 35, 2000
counter counter counter counter
Previous work: vernier delay line:10 ps resolution
1 1 0 0
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A simpler onchip circuit with ps accuracy:
Single latch with delayed clocksmall arealow powercontinuous operation (no startup noise issues)device matching not important
Full disclosure: proof of principle only not ready to drop into product chip not tested in ‘hostile’ environment
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C
D
o
o
signal
ref clock latch
signal delay chain
clock variable delay chain o
r.o counter
statemachine
clock counter
ref counter
latch counter
Vcntlenable ro
bypass
22
144
This circuit: single latch circuit:
5
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C
D
o
signal
ref clock latch
signal delay chain
clock variable delay chain o
statemachine
latch counter
Vcntlenable ro
bypass
22
144
Voltage controlled delay element varies the arrival of clock to latch varying clock with respect to data integrates jitter distribution to obtain
cumulative distribution function
This circuit: single latch circuit:
5
D
C
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tclock
jitter distribution cumulative distribution function
Changing delay of clock with respect to data generates cumulative distribution function (time integral of jitter spectrum)
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tclock
jitter distribution cumulative distribution function
14
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tclock
jitter distribution cumulative distribution function
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tclock
jitter distribution cumulative distribution function
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tclock
jitter distribution cumulative distribution function
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tclock
jitter distribution cumulative distribution function
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tclock
jitter distribution cumulative distribution function
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tclock
jitter distribution cumulative distribution function
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tclock
jitter distribution cumulative distribution function
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cumulative distribution function
tclock
jitter distribution
Recover jitter by differentiating
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C
D
o
o
signal
ref clock latch
signal delay chain
clock variable delay chain o
r.o counter
statemachine
clock counter
ref counter
latch counter
Vcntlenable ro
bypass
22
144 5
Implementation in 0.13 m, 1.2 V CMOS test chip
Delay elements: invertersLatch: differential edgetriggered (Montanaro, 1996)
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192m x 22 m
delay chain and latch
delay chain, latch, and counter
Delay chains and latch: 3200 m2
Counter: 3200 m2
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reference
clock(a) tracking, or longterm, jitter
(b) period jitter
jitter
jitter
definitions
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C
D
o
o
signal
ref clock latch
signal delay chain
clock variable delay chain o
r.o counter
statemachine
clock counter
ref counter
latch counter
Vcntlenable ro
bypass
22
144 5
Normal operation: compare signal to reference clock
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C
D
o
o
signal
ref clock latch
signal delay chain
clock variable delay chain o
r.o counter
statemachine
clock counter
ref counter
latch counter
Vcntlenable r.o.
bypass
22
144 5
Calibration of clock delay: convert chain to ring oscillator
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1.10 1.15 1.20 1.25 1.30
0.66
0.68
0.70
0.72
0.74
0.76
0.78
0.80
0.82
0.84
7/27/2004 08:15:57
1.3 Polynomial Fit of CAL2_B
Y =1.333170.49495 X
calibration data
dela
y (n
s)
vdd_var(V)
Delay calibration:Sample measurement
about 0.5 ps/mV
calibrate
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1.10 1.15 1.20 1.25 1.30
0.66
0.68
0.70
0.72
0.74
0.76
0.78
0.80
0.82
0.84
7/27/2004 08:15:57
1.3 Polynomial Fit of CAL2_B
Y =1.333170.49495 X
calibration data
dela
y (n
s)
vdd_var(V)
1.14 1.16 1.18 1.20 1.22 1.24
0
5000000
10000000
15000000
20000000
25000000 channeltochannel (HP8131)
de
riva
tive
Vdd_ var(V)
Measured CDF
Sample measurement
about 0.5 ps/mV
apply signal and ref to macro
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1.14 1.16 1.18 1.20 1.22 1.24
0
5000000
10000000
15000000
20000000
25000000 channeltochannel (HP8131)
deri
vativ
e
Vdd_ var(V)
Extracted jitter distribution
Sample measurement
about 0.5 ps/mV
Delay calibration:
differentiate and apply calibration
1.10 1.15 1.20 1.25 1.30
0.66
0.68
0.70
0.72
0.74
0.76
0.78
0.80
0.82
0.84
7/27/2004 08:15:57
1.3 Polynomial Fit of CAL2_B
Y =1.333170.49495 X
calibration data
dela
y (n
s)
vdd_var(V)
jitte
r sp
ect
rum
time (10 ps/div)
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Compare to oscilloscope measurements
(Jitter generated externally)
8131 cyclecycle jitter
sigma=12.5 psd
eri
vativ
e
time (10 ps/div)
Sigma=4.2 ps
Sigma=10.6 ps
8131 channeltochannel
sigma=3.2 ps
de
riva
tive
time (10 ps/div)
(jitter generated externally)
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Compare to oscilloscope measurements more complicated spectrum
Sigma=4.2 ps
(phase modulated pulse generator)
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Compare to oscilloscope measurements more complicated spectrum
Sigma=4.2 ps
820 810 800 790 780 770 7600.0
0.2
0.4
0.6
0.8
1.0
raw signal
ratio
of
cou
nts
time (ps)
measured CDF
(phase modulated pulse generator)
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Compare to oscilloscope measurements more complicated spectrum
Sigma=4.2 ps
820 810 800 790 780 770 7600.0
0.2
0.4
0.6
0.8
1.0
raw signal
ratio
of
cou
nts
time (ps)
9.8 ps
(phase modulated pulse generator)
10.3 ps
de
riva
tive
time (5 ps/div)
measured jitter
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C
D
o
o
ref clock latch
signal delay chain
clock variable delay chain o
r.o counter
statemachine
clock counter
ref counter
latch counter
Vcntlenable ro
bypass
22
144 5
Resolution test: compare reference to itself
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Resolution measurement:
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Effect of operating frequency all circuit blocks work at >2.5 GHz
1.230 1.235 1.240 1.245 1.250 1.255 1.2600
200
500 MHz clock frequency
1 ps
de
riva
tive
Vdd_var(V)
1.230 1.235 1.240 1.245 1.250 1.255 1.2600
200
400
600
800
bypass mode
50 MHz clock frequency
de
riva
tive
Vdd_var(V)
Noise increases due to layout oversight (i/o power supply connectedto delay chain supply)
50 MHz
500 MHz
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0.4 ps corresponds to ~ 850 GHz bandwidth
How is this possible in a technology of about 70 GHz cutoff frequency?
1/fT
Resolution bandwidth determined by uncertainty in switching time, not rise time
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Size and power
Combined reference chain, delay chain latch, and i/o test point power:
@1.2 V, f=200 MHz, P ~1.2 mW
Delay chains and latch: 3200 m2
Counter: 3200 m2
Measurement time
t=(counts)(steps)(clock period)+ overhead
eg, 25 time steps, 10000 counts, 1 GHz clock t=800 s.
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reference
clock(a) tracking, or longterm, jitter
(b) period jitter
jitter
jitter
definitions
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C
D
o
o
signal
ref clock latch
signal delay chain
clock variable delay chain o
r.o counter
statemachine
clock counter
ref counter
latch counter
Vcntlenable ro
bypass
Modification for cycle to cycle jitter:delay chain difference equal to clock period
Will test this in Brahma 9SF run
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C
Dclocksignal latch
signal delay chains
variable delay chain
clock / r.o counterstatemachine
latch counter
Vcntlenable ro
bypassOCD
OCD OCD
OCD
length select
one period delayfixed delay
period jitter: insert additional delay equal to one period
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Comparison of oscilloscope measurement with onchip measurement
CMOS 9SF (0.09 m) pad cage demonstration: Apply known signal to macroGood reproduction of applied signal
fclock
=540 MHz
=5.4 ps
20 ps/div
fclock
=540 MHz
=1.2 ps
20 ps/div
=1.8 ps
=5.7 ps
=1.7 ps
=1.7 ps540 MHz falling edge
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CMOS 9SF pad cage demonstration
fclock
=540 MHz
20 ps/div
fclock
=1080 MHz
=1.03 ps
20 ps/div
=1.8 ps
=1.7 ps
Comparison of oscilloscope measurement with onchip measurement
=1.8 ps
540 MHz falling edge
1080 MHz rising edge
Resolution~ 1ps
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Effect of Vdd noise on resolution
Quiet supply
300 mV Gaussian noise with 10 MHz BW applied to delay chain voltage; probe decoupling of 109 nF to ground reduces the actual noise on the circuit
Note that the prototype used simple inverters which are not noise immune!
fclock
=1080 MHz
=2.3 ps
20 ps/div
fclock
=1080 MHz
=1.03 ps
20 ps/div
1080 MHz rising edge
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C
signal
ref clocklatch
signal delay chain
o
multiple measurement points: measure jitter and skew (with single variable chain) bypass calibrates each test point
signal delay chain
signal delay chain
reference variable delay chain
signal
signal
bypass
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6 8 10 12 14 16 18 20 22 24 26 28 300.00E+000
1.00E+008
2.00E+008
3.00E+008
4.00E+008
5.00E+008
6.00E+008
6 8 10 12 14 16 18 20 22 24 26 28 300.00E+000
1.00E+008
2.00E+008
3.00E+008
4.00E+008
5.00E+008
6.00E+008
skew=16 ps
test point 2test point 1
fclock
=2 GHz
CD
F
time (ps)
Skew measurement on 2 GHz experimentalresonant clock circuit; 0.18m technologyCourtesy of Ken Shepard, Columbia Univ.
Used differential buffers to avoid power supply noise effect
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Which technology is best?
Similar resolution has been seen with 3 technologies:
0.18 m, 1.5 V0.13 m, 1.2 V0.09 m, 1.2 V
Tradeoffs:
Scaled technologies have potentially better resolution due to faster transition times,But lower power supply operation makes them more susceptible to noise adding jitter
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VDD
VDD
D D_
CLK
CLK CLK
S_R_
Q Q_
Montanaro. J., et al. ‘ A 160MHz, 32b, 0.5W CMOS RISC microprocessor’, IEEE J. SolidState Circuits, 1996, 31, (11), pp. 17031714.
Differential latch senseamp latch