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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 6, NOVEMBER 2009 749

Junction Field Effect Transistors for NanoelectronicsJustin B. Jackson, Student Member, IEEE, Divesh Kapoor, Student Member, IEEE, and Mark S. Miller, Member, IEEE

AbstractThe gate leakage currents of MOSFETs increase ex-ponentially with downward scaling, while the gate currents ofenhancement-mode JFETs for complementary logic decrease withscaling. In principle, a crossover point could exist below which theJFET may be the preferred device for some large-scale ICs. Thispaper first examines the crossover point with a simple scaling anal-ysis that suggests it lies in the neighborhood of a 25 nm gate length,depending on the supply voltages and the gate insulator used forthe MOSFET. Other JFETelectrical properties comparefavorablywith those of MOSFETs and exhibit similar scaling behaviors. Nu-merical simulations of a simple 25 nm gate length JFET showelectrical properties better than the conservative scaling analysisand comparable to reported 25 nm MOSFETs, with, for example,a gate current density of 12 A/cm2 at 0.7 V and a drain currentON-to-OFF ratio of 3.5 103 . A self-aligned polycrystalline silicon

gate and some straightforward performance enhancements pro-posed for the 25 nm device may allow it essentially to stand in forthe geometrically similar 25 nm MOSFET in some circumstances.Additional device engineering outlined in this paper should furtherallow the silicon JFET to scale down to 10 nm gate lengths, wheresourcedrain tunneling becomes important. Ten-nanometer-scaleJFETs share many of the fabrication challenges of correspondingMOSFETs, and many of the well-developed concepts for MOS-FETs, such as double gatesand strain engineering, should be easilyadapted to JFETs. These devices also lend themselves to a subse-quent transition to IIIV semiconductorsfor heterostructures,performance increases, and scaling below 10 nmwithout the ox-ide interface problems MOSFETs would face. Overall, JFETs ap-pear to be of interest for the next one to two silicon technologynodes, and perhaps beyond.

Index TermsJFETs, MOSFETs, nanotechnology.

I. INTRODUCTION

AS THE dimensions of MOSFETs have scaled downward

to increase density and performance, gate leakage due to

tunneling through thin gate oxides has become a major design

constraint. The gate leakage current density increases approx-

imately exponentially with decreasing oxide thickness. While

thicker gate insulators with higher dielectric constants have mit-

igated this problem, subsequent scaling still encounters this ex-

ponential dependence. For complementary logic, JFETs need to

be enhancement mode devices, turning ON with forward-biasedgate p-n junctions. Such currents, and the consequent restric-

tions on gate voltages, have historically made these transistors

noncompetitive for large-scale ICs. However, scaling a JFET to

smaller dimensions can actually decrease the gate current some-

what, because the scaled-up doping concentrations reduce the

Manuscript received August 7, 2007; revised April 29, 2008. First publishedDecember 22, 2008; current version published November 11, 2009. The reviewof this paper was arranged by Associate Editor T. Hiramoto.

The authors are withthe Department of Electrical and ComputerEngineering,University of Utah, Salt Lake City, UT 84112 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNANO.2008.2011383

Fig. 1. Scaling models for JFET and MOSFET comparison. The dimensionsscale by > 1, and for the doping scales as 2 .

junction saturation currents; and logic levels are decreasing into

the range of p-n junction turn-on voltages. In principle, there

could be a crossover point in scale below which complementary

JFET circuitry has lower gate leakage and may become prefer-

able. Whether the crossover point happens at a technologicallyrelevant size will depend on the details of where it occurs with

respect to MOSFET scaling, and how well JFETs function at

that scale and below.

The largest tolerable transistor gate current density, which im-

poses a minimum gate length L for MOSFETs, depends on theapplication the circuit is designed for [1]. For comparison pur-

poses, the present paper considers gate lengths for single-gate,

bulk devices as depicted in Fig. 1. For moderate-performance

ICs, for example those used in desktop applications, a conser-

vative limit on gate current density is 1 A/cm2 , though some

authors have argued for and demonstrated a higher practical

maximum of perhaps 100 A/cm2 [2][4]. For a MOSFET with

a silicon dioxide gate insulator and a gate potential of 1 V,

the leakage reaches 1 A/cm2 when the oxide thickness scales to

about 1.7 nm [3], [5]. This silicon dioxide thickness corresponds

to a transistor length ofL 70 nm [6]. Current production tech-nologies at the 65 nm technology node use silicon oxynitride

gate insulators, with one example having a 35 nm gate length,

though its 1.2 nm insulator was not scaled from the preceding

90 nm technology node because of gate leakage [7]. An exam-

ple of an emerging 45 nm technology takes advantage of the

yet higher dielectric constant of a hafnia-based gate insulator,

though its physical gate length remained at 35 nm [8].

The scaling properties of enhancement mode JFETs and the

consequences for complementary logic have received much less

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attention in the literature. Electrically, JFETs behave similarly

to corresponding MOSFETs, and they also benefit from lower

input capacitance and lower noise. Because of these proper-

ties, some applications have favored JFETs over MOSFETs, for

example, as the low-noise front ends for charge sensing ampli-

fiers. For ICs, complementary enhancement mode silicon JFETs

have been investigated because of their inherently greater resis-tance to radiation damage [9], [10]. The scaling behaviors of the

closely related MESFET have been studied and reported [11], as

have complementary enhancement mode silicon MESFET tech-

nologies [12]. However, the Schottky-contact gates have much

larger saturation current densities than p-n junction gates, and

an upper limit on channel doping to avoid gate tunneling cur-

rents prevents these devices from scaling to smaller dimensions.

For JFETs, a simple, one-sided diode model can give an initial

gate current density estimate. Considering a 30-nm-thickn-type

neutral layer doped to 5 1018 cm3 at a forward bias of 0.7 V

yields a current density of the order of 1 A/cm2 . This suggests

that, at the sub-one-volt supplies planned for the near future,

JFET gate current densities may compete with MOSFET gatecurrent densities.

Section II presents a scaling analysis of enhancement mode

JFETs for complementary logic. A comparison to the scaling be-

havior of MOSFETs shows that the gate leakage crossover point

lies somewhere between gate lengths of 2035 nm, depending

on the supply voltages and gate insulator. The numerical simula-

tions reported in Section III examine the behavior of a simple 25

nm gate length design and find electrical properties that validate

the scaling analysis and compare favorably with reported MOS-

FETs. Section IV discusses the implications and opportunities

for JFET engineering, including many of the modifications de-

veloped for MOSFETs that should be applicable to JFETs, andthe prospects for scaling JFETs to 10 nm and below. The final

section summarizes the findings and conclusions of this paper.

II. SCALING ANALYSIS

The scaling analysis presented here correlates the JFET gate

current with the gate length. This allows for comparison with

corresponding MOSFET gate currents, as well as with other

properties, under scaling. A good deal of MESFET scaling

analysis applies to JFETs [11]. However, the literature does

not appear to include MESFET analyses suitable for examin-

ing a JFETMOSFET gate leakage crossover point. The simple

JFET scaling discussed later varies the structural dimensions

and dopings under an approximate constant voltage regime. A

constant voltage scheme applies to these enhancement mode

devices because forward diode currents limit supply voltages

on the high end, and at the low end, OFF-state drain currents,

Ioff, limit the minimum practical values of the threshold volt-age Vt . The voltages used in a given setting will depend on thefigures-of-merit needed for that application. This conservative

scaling scheme has the largest, and most problematic, dopant

and field increases. A constant voltage scaling for the MOSFET

is also used for comparison. Other scaling regimes are possible

for both transistors. For example, a two-parameter generalized

scaling is common for MOSFETs [13], and the wider variety

of scalings available for MESFETs, depending on the figure-

of-merit of interest [11], also applies to JFETs. In addition to

gate currents, the properties scaled and compared next include

the drain current, transconductance, and subthreshold current,

estimated under the gradual channel approximation, as well as

the gate capacitance and band-to-band tunneling. Discussions

of the principal 2-D and short-channel effects, which are largelysimilar for JFETs and MOSFETs, are given with the numerical

simulation results of Section III.

A. JFET Scaling

Fig. 1 depicts the n-channel bulk JFET scaling model. All

dimensions scale by > 1, including the gate length L/ andwidth W/. An oxide defines the bottom of the channel, whichhas a metallurgical thickness of a/, and h/ is the depletionthickness into the channel. To reduce 2-D and short-channel

effects, the channel will be conservatively constrained to L =2a [14]. For numerical comparisons, the reference design has

a gate length of L = 50 nm, channel doping of Nd = 1.6

1018 cm3 , and gate doping of Na = 1.6 1019 cm3 , which

has a threshold voltage of approximately Vt = 250 mV. Theseparameters were chosen, in part, to enable scaling to a viable

10 nm gate length device with minor modifications, as discussed

in Section IV.

For scaling, threshold will be defined here to occur

when the depletion edge coincides with the channel bottom,

with the drainsource potential Vds = 0. Taking the gatechannel junction to be one-sided, this happens at h = a =

2s (Vbi Vg )/qNd , where Vg is the gate potential, s thesemiconductor permittivity, and q the elementary charge. Thebuilt-in potential Vbi will be larger than the nonscaled appliedpotentials for the enhancement mode devices under consider-

ation, and Vbi will vary only logarithmically with dopingor even more slowly for degenerately doped material. Conse-

quently, the channel doping will need to scale as 2 to ac-commodate the scaling ofa and h. With these assumptions andscalings, the threshold voltage

Vt = Vbi qa2 Nd

2s(1)

will also change slowly with scaling. Designing a particular Vtentails changing both the channel thickness and doping.

The forward gate current density depends on the doping and

thus the gate length. A 1-D ideal diode model illustrates this,giving a gate current density of

Jg =1

qn2i

Dn

Na Wp+

DpNd Wn

(eVg /Vth 1) (2)

where ni is the intrinsic carrier concentration, Dn and Dpthe minority carrier diffusivities, Wn and Wp the neutral layerwidths, and Vthe thermal potential. Consequently, in this model,and neglecting that diffusivity decreases with doping, the for-

ward gate current scales as Ig 1/3 . Such a 1-D model should

overestimate the gate current density along the channel because

not all of the gatechannel interface sees the full gate volt-

age, analogous with current crowding seen at the baseemitter


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Fig. 2. Gate current density scaling of MOSFETs and JFETs versus gatelength. The silicon JFET curves (solid black lines), plotted for 0.6, 0.7, and0.8 V gate biases, and the GaAs JFET curves (solid blue lines) for 0.9 and1 V gate biases, come from 1-D models with bandgap narrowing. The 1 Vtunneling data [18] for MOSFET gate current densities through pure SiO 2 (red

open diamonds) and pure HfO2 (red open triangles) are correlated with gatelengths using the international technology roadmap for semiconductors (ITRS)road map [6] and fit with exponential dependences (red dash-dotted lines). Thesilicon JFET band-to-band tunneling current density scaling estimate (greendashed line) is for an abrupt junction and a 0.7 V drain-to-gate bias. The pointsplotted from the 25 nm JFET simulation include the gate current density (blacksolid squares) at 0.6 and 0.7 V gate biases and band-to-band tunneling (greensolid circle) at 0.7 V.

junction in bipolar transistors. The largest gate currents should

flow for small drainsource biases. Under the present constant

potential scaling, with the diffusion current densities in the

quasi-neutral p and n regions determining the forward gate cur-

rents, such 2-D effects should have the same scaling behavior

as the 1-D model.

However,at thesmaller dimensions of interest here, the higher

doping levels will make bandgap narrowing important, reducing

the gatechannel barrier and increasing the saturation current

density. Fig. 2 plots a 1-D diode model for the gate current den-

sity versus gate length for the scaled reference design, including

bandgap narrowing [15], at gate potentials ofVg = 0.6, 0.7, and0.8 V. The neutral layer thicknesses for the reference design in

this 1-D model are Wn = Wp = L/2, and the minority carrierdiffusivities are Dp = 4 cm

2/s [16] and Dn = 6.2 cm2/s [17].

The gate current densities trend upward with decreasing gate

length due to bandgap narrowing, instead of following the be-havior of (2). Significantly, throughout the 1050 nm gate length

range plotted, the gate current density for Vg = 0.6 V is on theorder of 1 A/cm2 , and the 0.7 V curve lies close to 100 A/cm2 ,

which spans the range important for medium-performance ap-

plications [1].

The typical JFET drain current expressions obtained in the

gradual channel approximation can be cast into a second-order

MOSFET-like form for enhancement mode devices [19]. In sat-

uration, the drain current scales as

Idsa t =

1

s n

2a

W

L

Vg

Vt2

(3)

where n is the channel electron mobility. For the short-channelJFETs under consideration here, electron velocity saturation at

vsa t will generally be important, for which the saturation draincurrent approximately becomes

Idsa t s vsa t W

a(Vg Vt ). (4)

With velocity saturation, the transconductance in saturation,gm sa t s vsa t W/a, does not decrease with downward scaling.For the reference design in saturation with vsa t = 10

7 cm/s, the

transconductance per gate width is 420 mS/mm.

The intrinsic gate capacitance can have contributions from

the depletion layer capacitance and, when the gate is forward-

biased, from diffusion capacitance. The diffusion capacitance

per area due to both electron and hole injection scales is

Cdiff.g =1

3qn2i2Vth

WnNd

+WpNa

eVg /Vt h . (5)

The junction capacitance per area scales as

Cdep.g = s

h s

a. (6)

Estimating their contributions in an L = 25 nm device givesCdep.g = 8.4 10

7 F/cm2 and a much smaller Cdiff.g = 1.2

108 F/cm2 , using a gate bias of Vg = 0.8 V and includingbandgap narrowing for the diffusion capacitance. These values

and the respective scaling behaviors show that the diffusion

capacitance should be negligible with respect to the depletion

capacitance over the scales and biases of interest.

The subthreshold drain current given by a 1-D channel barrier

model is

Ids =

1

2 n CDW

L V2

th e(Vg sVt )/Vt h

1 eVd s /Vt h

(7)

where CD is the extrinsic Debye capacitance for the n-typechannel doping [20]. Neglecting changes in mobility, in this

model the subthreshold current will vary with CD , which con-tributes the scaling because of the changing doping. Thisexpression gives an inverse subthreshold slope of

S = log10 (e)Vth 60 mV/decade. (8)

For most practical devices, though, the inverse subthreshold

slope will be larger due to 2-D effects and to some potential

drop across an underlying oxide.

At the smallest dimensions, and thus largest doping con-

centrations, band-to-band tunneling in the reverse-biased gate

drain junction can contribute significantly to leakage. The

tunnelingis largest when thedevice is turnedoff with thesource

drain potential equal to the voltage supply. The tunneling cur-

rent density depends sensitively on the local electric field. Fig. 2

includes an estimate of the band-to-band tunneling current den-

sity scaling based on a phenomenological fit [1] of experimental

data from Fair and Wivell [21] and from Stork and Isaac [22],

corresponding to the JFET turned off and a 0.7 V potential on

the drain. The maximum electric field used for plotting comes

from the conservative assumption of an abrupt p-n junction.

With this estimate, the band-to-band tunneling current becomes

larger than the forward gate current density for L

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A more realistic, graded junction significantly reduces the max-

imum electric field and the tunneling current, though making

such an estimate requires more device design assumptions than

those of Fig. 1. Solomon et al. [23] reported on extensive mea-

surements of the tunneling currents in heavily doped p-n junc-

tions and found an empirical fit based on the effective tunneling

distance between bands. While that empirical fit is not wellsuited to the present scaling analysis, because of its effective

tunneling distance dependence on doping profiles, data from

particular measured devices can give some guidance for actual

junctions with graded compositions. For example, a p+ n diode

with n-doping of 6.2 1018 cm3 (wafer PN-BF2 , Q2 [23]),

which here corresponds to the 25 nm JFET, had a tunneling

current of 1.5 103 A/cm2 at a reverse bias of 0.7 V, which

lies a factor of 100 below our estimate in Fig. 2. Some simple

design changes and tunneling estimates discussed in Section IV

indicate that prohibitively large band-to-band tunneling leakage

can be avoided down to 10 nm gate lengths in silicon devices.

B. MOSFET Scaling Comparisons

The sharpest distinction between JFETs and MOSFETs un-

der scaling occurs for their gate currents. The MOSFET gate

current leakage due to tunneling through the oxide varies ap-

proximatelyas et o x / , where is a material-dependent poten-tial barrier parameter. Fig. 2 plots estimates of MOSFET gate

current densities versus gate length for two limiting cases of

gate oxide materials, assuming either SiO2 or pure, high dielec-

tric constant HfO2 . Experimental current densities for tunnel-

ing through SiO2 layers from Yeo et al. [18] at a gate potential

of 1 V are correlated with gate lengths using the 2005 ITRS

roadmap [6] and fit with an exponential dependence in Fig. 2.

Similarly, tunneling data at 1 V for HfO2 layers [18] are plotted

using their equivalent SiO2 thickness and fit with an exponen-

tial dependence. The curves in Fig. 2 indicate that the crossover

point from MOSFET to JFET gate current densities occurs at

roughly a 20 nm gate length for pure hafnia and 35 nm for sili-

con dioxide, assuming a 0.7 V JFET supply voltage. Generally,

the oxide tunneling will lie in between the fitted curves for SiO 2and HfO2 , either because silicon oxynitride is used or because

pure hafnia will not be used. Additionally, oxide tunneling data

for 0.7 V would shift the MOSFET curves leftward, but still

retain the exponential dependences.

A disadvantage of the JFET with respect to a similarly sized

MOSFET is that the drain current can be somewhat lower. Com-paring the JFET drain current in saturation of (3) with an anal-

ogous MOSFET square law model that includes the body effect

coefficient m [15] gives

IJFETdsIMOSds

= mneff

sox

toxa

. (9)

Here, the MOSFET inversion layer effective electron mobility

is eff, and the gate oxide permittivity and thickness are ox andtox . For m = 1.4, tox /a = 1/10, s /ox = 3, and equal mobili-ties, the idealized JFET drain current is approximately 2/5 the

magnitude of a similarly sized MOSFET. This can be improved

by making a smaller, while increasing Nd to maintain a given

TABLE ISCALING OF JFET AND MOSFET PARAMETERS AND PROPERTIES

Fig. 3. Modelfor 25 nm JFET simulation andPADREpotential solutions with

Vds = Vgs = 0 V and 0.8 V.

threshold voltage according to (1), though at the expense of

increasing band-to-band tunneling in the smallest devices.

Conversely, the JFET has an advantage of lower gate capaci-

tance. The ratio of JFET to MOSFET intrinsic gate capacitances

is

CgCox

=s

ox

toxa

. (10)

Using the same parameter estimates as for the drain currents

gives a JFET capacitance that is approximately 1/3 that of a

similar MOSFET.Table I compiles the JFET scaling results and their counter-

parts from a constant potential scaling of MOSFETs. Apart from

the dramatic difference in gate current scalings, JFETs behave

quite similarly to MOSFETs under scaling.

III. 25 nm JFET Simulation

The properties of a simple n-channel, enhancement mode

JFET model with a gate length ofL = 25 nm were investigatedusing the PADRE semiconductor device simulation tool [24].

Fig. 3 depicts the model geometry, where the 12.5-nm-deep

channel is doped to Nd = 5.0 1018 cm3 , and the 25-nm-

long gate that extends 10 nm into the substrate is doped to

p+ = 1.0 1020 cm3 . Thesource and drain contacts aredopedto n+ = 1.0 1020 cm3 andhave symmetric setbacks from thegate of 10 nm. The simulated device width was W = 100 nm.The back side contact to the 77.5 nm silicon dioxide was de-

fined as p-type silicon and its potential was held at zero. Thesimulations presented here included field- and concentration-

dependent mobilities, bandgap narrowing from heavy doping,

band-to-band tunneling, ShockleyReedHall recombination,

and FermiDirac statistics.

Adjusting the channel doping to the value given earlier gave

a threshold voltage of approximately 150 mV and the output

characteristics of Fig. 4. The electric potential solutions given


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Fig. 4. Simulated forward drain characteristics for a 25 nm JFET. The gatepotential increases in steps of 0.1 V from 0 to 0.8 V. At Vg = Vds = 0.7 V,gm = 690 mS/mm, and gd s = 84 mS/mm.

in Fig. 3 correspond to the equilibrium solution and to the solu-

tion for Vg = Vds = 0.8 V in the characteristics of Fig. 4. Thedrain current at Vg = Vds = 0.7 V, which will be taken hereas ION for comparison purposes, is around 200 A/m, at aforward gate current density of 12 A/cm2 . This ON current com-

pares well with the drain current of approximately 300 A/mat 0.7 V measured by Krivopavic et al. [25] for an experimental

MOSFET with L = 25 nmthough that MOSFET drive cur-rent increased to approximately 1 mA/m at 1.5 V; and thegate current density through its nitridated silicon dioxide gate

dielectric was 25 A/cm2 at 0.9 V. Doris et al. [26] reported a a

drive current of approximately 300 A/m for an experimentalMOSFET with L = 21nmat0.7V,whichincreasedto1mA/mat 1.5 V; however, the corresponding gate current density was

not reported. Bai et al. [7] reported a drive current of approxi-

mately 520 A/m for a production MOSFET with L = 35 nmat 0.7 V, which increased to 1 mA/m at 1.2 V. The aforemen-tioned JFET Ion is slightly better than, but consistent with, whatwould be expected from the JFET/MOSFET ratios of saturation

currents given by the ratio in (9). Optimizing the simple 25 nm

JFET design with some of the techniques proposed in Section IV

could well narrow this performance gap. The transconductance

at Vg = Vds = 0.7 V is approximately gm = 690 mS/mm, andthe output conductance gds = 84 mS/mm. These values give aratio ofgm /gds = 8.2, which would be suitable for many digitallogic applications.

Fig. 5 plots the gate current versus the gate potential for

two values of the drainsource potential, Vds = 0.0 and 0.7 V.Allocating the resulting gate currents to the gate area, W L,gives the two points plotted in Fig. 2 for Vg = 0.6 and 0.7 Vwith Vds = 0.0 V. These two values lie below the predictions ofthe scaling model of Section II. For comparison, Solomon et al.

reported a forward diode current density of 50 A/cm2 at a bias of

0.7 V for a p+ n diode with n-doping of 6.2 1018 cm3 (wafer

PN-BF2 , Q2), corresponding to the 25 nm JFET gate-channel

junction [23]. The discrepancy may be due to a combination of

the effective area being much less than the gate area, the effective

Fig. 5. Simulated gate current versus gate voltage for a 25 nm JFET at Vd s =0.0 and 0.7 V. For Vd s = 0.7 V, model runs with and without band-to-bandtunneling turned on show the relative contribution from tunneling.

Fig. 6. Simulated band-to-band tunneling in the reverse-biased gatedrainjunction. Tunneling currents were estimated by taking the difference betweenmodel runs with and without band-to-band tunneling turned ON.

neutral lengths in the 2-D simulation being larger than the 1-D

model lengths, and possibly the differing model minority carrier

diffusivities. The two curves for the simulated gate current with

Vds = 0.7 V correspond to two model runs, with and withoutband-to-band tunneling turned ON. These runs allow the band-

to-band tunneling at Vg = 0 V to be also plotted on the scalingaxes of Fig. 2, again using the gate area to estimate the current

density. The simulated tunneling current density is close to the

analytic estimate. Taking the difference of the curves with and

without band-to-band tunneling gives the curve of Fig. 6. The

point at 0.7 V gives a tunneling current of 60 pA per micrometer

of gate length.

Fig. 7 gives the transfer characteristics for the 25 nm JFET

model. At Vds = 0.7 V, Ioff = 60 nA/m. This OFF current ismuch larger than the band-to-band tunneling current, indicating

that the OFF current is a subthreshold diffusion current. Impor-

tantly, because the band-to-band tunneling current in this model

device is a factor of 103 less than the diffusion current, a larger

channel doping concentration for an increased drive current


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Fig. 7. Simulated transfer characteristics for a 25 nm JFET, on both semiloga-rithmic and linear axes. The upper curves on a logarithmic current scale exhibitinverse subthreshold slopes of 90100 mV/decade and DIBL of approximately115 mV/V. The lower curves on a linear current scale show threshold currentsofVt = 175 mV and 100 mV for Vds = 50 mV and 0.7 V, respectively.

could be used while tolerating its larger band-to-band tunneling

leakage. The simulated 25 nm JFET ION/IOFF ratio of 3.5 103

at 0.7 V compares well with the measured MOSFET ratios at

0.7 V for the devices cited earlier with ION/IOFF = 5.2 103 at

L = 35 nm [7], 2.1 103 at L = 25 nm [25], and 2.1 103 atL = 21 nm [26]. Those MOSFET ratios increased with supplypotential to, respectively, 1.46 104 at 1.2 V [7], 7.2 103 at

1.5 V [25], and 7.2 103 at 1.5 V [26]. The simulated JFET

shows a 90100 mV/decade inverse subthreshold slope. This

slope is slightly less than than the 115 mV/decade simulated for

a 25 nm MOSFET by Taur et al. [27] and comparable to the

95 mV/decade measurement reported by Krivokapic et al. [25].The simulated transfer characteristics of Fig. 7 exhibit the short-

channel effect of drain-induced barrier lowering (DIBL). Using

the threshold voltage shift between 0.05 V and 0.7 V rail volt-

ages of approximately 0.075 V, gives a DIBL of approximately

115 mV/V. This value compares favorably with a measured

DIBL of 146 mV/V reported by Krivokapic et al. [25] but more

than double the simulated value of 50 mV/V reported by Frank

et al. [1] for a 25 nm MOSFET.

While the abrupt junction model used here greatly simplifies

the doping profiles expected from fabrication, its concentra-

tions and depletion width are representative of reported junc-

tions and should reasonably capture most behaviors of an actual

JFET without introducing additional arbitrary model structure

parameters to describe doping implant profiles. For the 25 nm

JFET, relevantexperimental p-n junction examples include those

demonstrated by Parket al. [28] andthe implant profiles reported

by Walther et al. [29]. Orlowski [30] reviewed some research

underway to develop just such shallow, high-concentration junc-

tions that the ITRS roadmap [6] calls for by the end of the decade

for MOSFETs. The abrupt junction JFET model should give

quantitatively similar results to a graded junction, with graded

junctions improving the transconductance linearity [14]. Irre-

spective of profile, the threshold voltage and channel current

are determined by the designed channel charge and depth, and

thus quantitative comparisons with the abrupt junction model

should be meaningful. However, the abrupt junction will give

a noticeably higher maximum electric field, which will lead

to an overestimate of the reverse-bias band-to-band tunneling

leakage.

IV. DISCUSSION: NANOELECTRONIC JFET ENGINEERING

The scaling analysis and simulations of the preceding sec-tions strongly suggest that complementary silicon JFETs may

compete with MOSFETs, at gate lengths below approximately

25 nm. The first section that follows discusses optimizing and

scaling the simulated 25 nm device. Optimizing the design may

enable it essentially to stand in for a 25 nm MOSFET that has

a hafnia-based dielectric at lower supply voltages. Addition-

ally, the great geometric similarity of the two devices layouts,

and the materials and fabrication process compatibilities, should

confer an advantage to the JFETs over some other devices under

consideration for MOSFET replacement, as the impacts on the

system architecture would likely be modest. Scaling the opti-

mized 25 nm design to near 10 nm would benefit in part fromsome techniques already developed for MOSFETs. In this scale

range, the primary device engineering challenge will likely be

the leakage from band-to-band tunneling in the reverse-biased

gatedrain junction. The second section that follows discusses

the prospects for replacing silicon with IIIV semiconductors

in JFETs to increase channel mobilities, for example, and to

expand the range of possible heterostructures. Similar mate-

rial changes under consideration for MOSFETs would require

identifying suitable gate insulators [31]. The third section that

follows discusses how JFETs might effectively scale below the

10 nm barrier, imposed by leakage from source-to-drain tun-

neling [1]. Such scaling may require wraparound gates, to con-

trol short-channel effects, as well as source and drain materialchanges, to control sourcedrain tunneling.

A. Optimizing and Scaling Silicon-Based JFETs

Some straightforward improvements to the simple 25 nm de-

sign could increase the ON drain current, reduce the leakage

currents, and reduce the footprint. Referring to (3) for guidance,

decreasing the channel thickness a increases the ON current,and the threshold voltage can remain the same provided Nd in-creases to keep the product a2 Nd constant. Fig. 5 shows thatthe greatest gate current flows for large gate bias and small

sourcedrain potential, as would be found in an inverter with

a high input. About half of this current flows through the end

faces of the p-gate region simulated in Section III. Forming

the gate instead by depositing a heavily doped polycrystalline

silicon gate directly on the channel, using techniques similar

to those used for bipolar junction transistor emitters, would re-

duce the junction area and current. Such a raised gate would

similarly reduce band-to-band tunneling at the drain end of

the gate and reduce gatesource and gatedrain capacitances.

Importantly, the polycrystalline-silicon-raised gate would facil-

itate a self-aligned gate process directly analogous to that used

for MOSFETs. Reducing the source and drain contact setbacks

can reduce the device footprint, until band-to-band tunneling

at the gatedrain junction becomes prohibitive. Engineering the


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lateral doping gradient between the gate and drain can reduce

the maximum electric field, and consequently, the tunneling, al-

lowing a shorter setback, and the setbacks can be asymmetric,

with a smaller sourcegate setback.

The basic enhancement mode JFET can benefit from tech-

nologies developed to scale MOSFET performance without

changing the gate length [32]. The raised gate can serve asan ion implantation mask for a halo implant to reduce short-

channel effects. Uniaxial strain can improve mobility [33], [34].

Fabricating a p-channel transistor on (1 1 0) silicon can decrease

the effective mass, and thus, increase the hole current. The JFET

also lends itself to using higher mobility silicon germanium al-

loys in the channel, though material with smaller bandgaps can

greatly increase the band-to-band tunneling leakage.

Band-to-band tunneling in the reverse-biased gatedrainjunc-

tion presents a design challenge in scaling the 25 nm device to

10 nm. This problem is directly analogous, and of a similar mag-

nitude, to the well-studied drain-to-body tunneling problem in

MOSFETs [1]. For the JFET, the constant potential scaling of

Section II indicates that the channel thickness should decreasefrom 12.5 nm to 5 nm, and the channel doping should increase to

Nd = 4.0 1019 cm3 . Using the 1-D, one-sided abrupt junc-

tion model plotted in Fig. 2, with a 0.7 V reverse bias, band-to-

band tunneling would be of the order of 100 kA/cm2 . If, instead,

a linearly graded junction model is used, then the estimate is

of the order of 1 kA/cm2 [21]. The tunneling measurements

from Solomon et al. include data from two p+ n junctions with

n dopings of Nd = 2.21 1019 and 9.05 1019 cm3 (wafer

PN-BF2 Q5 and Q8) that gave tunneling currents of 3 A/cm2 and

70 A/cm2 , respectively. Those data show both that the tunnel-

ing estimates for the JFET are conservative and that the tun-

neling leakage at 10 nm may well be manageable. Generally,a too large leakage could in part be reduced by using a less

conservative L/a 1.5, enabled by a halo implant to controlshort-channel effects, and allowing for a lower channel doping.

Further reducing the doping gradient at the metallurgical junc-

tion also helps. For example, in the idealized limit of an undoped

10 nm layer between the gate and channel dopings, giving an

electric field of approximately 1.7 MV/cm, the tunneling current

would beon the order of1 A/cm2 [1]. This dopant gradient could

be approximated by having the peak of the channel doping occur

at the bottom of the channel, by not fully scaling the gatedrain

setback, and by having the gatechannel metallurgical junction

occur slightly up in the gate.

B. Compound Semiconductors and Heterostructures

Changing the JFET semiconductor from silicon to a IIIV

compound semiconductor can improve some device properties

and allow for a wider range of heterostructures for device en-

gineering. The semiconductors used for JFETs include Si, SiC,

GaAs, InP, GaP, and InGaAs/InP [35][38]. Enhancement mode

GaAs JFETs have been studied for ICs [39]. A similar semicon-

ductor change for MOSFETs entails developing suitable di-

electrics, greatly complicated by the ubiquitous interface states

at the IIIV semiconductoroxide interface [40]. The perfor-

mance benefits can include larger mobilities andlarger bandgaps

to decrease gate leakage. For example, Fig. 2 includes gate cur-

rent density estimates for enhancement mode GaAs JFETs using

a 1-D diode model. The curves in Fig. 2 use constant values for

the product of minority carrier diffusivity and effective intrin-

sic concentration, with nie D of 1013 cm4/s for electrons and

2 1015 cm4/s for holes, because for GaAs at very high dop-

ing levels, bandgap narrowing is counterbalanced by a wideningdue to degeneracy effects [41]. At a given forward bias, these

calculations give several orders of magnitude decease in gate

current density compared to silicon devices. This suggests that

GaAs-based JFETs could be the preferred devices for low-power

applications, which otherwise impose a minimum gate length of

approximately 35 nm for silicon MOSFETs [1]. Additionally,

the larger bandgap of GaAs would greatly reduce leakage from

band-to-band tunneling. The mobility of the channel can be

increased by defining the channel bottom with a heterobarrier

and using modulation or remote doping. Using a smaller

bandgap gate could significantly reduce gate injection into the

JFET channel, though a larger bandgap in the gate depletion

field would still be desirable to avoid band-to-band tunneling.Further modifications can include using high-mobility quantum

wells to define the channel, which have been shown to lead to

large transconductances [42].

C. Nanowire JFETs and the 10 nm Barrier

Double gate and wraparound gate geometries have been in-

vestigated for MOSFETs to control short-channel effects [32],

[43]. JFETs lend themselves to similar modifications, which

may be necessary for scaling below the 10 nm barrier. A cylin-

drical geometry has the best scaling properties for controlling

short-channel effects [44]. Nanowires grown with a catalyst nat-

urally have this geometry. They allow much greater compositionmodulation than planar structures because the strain constraint

is relaxed, and thus a greater range of electronic structure en-

gineering [45][48]. Well-defined heterostructures in both the

radial and axial direction have been reported [48], [49]. Radial

heterostructures can, in principle, be used to engineer the gate

leakage, and axial heterostructures to control the sourcedrain

tunneling. Epitaxial IIIV nanowires have been grown directly

on silicon [50]. Nanowire MOSFETs have been made both in

silicon and IIIV semiconductors [51][54]. Schottky contacts

for the source and drain can be utilized to reduce the source

to drain leakage current, with nickel disilicide contacts to sili-

con nanowire reported [55]. However, practical nanowire JFETspresent great challenges in growth and doping control.

V. CONCLUSION

This paper has examined the implications of a gate leakage

crossover point from MOSFETs to JFETs under scaling. A sim-

ple scaling analysis suggests that a practical crossover point

lies in the vicinity of 25 nm, depending on the supply voltage

and the MOSFET gate insulator being considered. Otherwise,

the analysis indicates that while the JFET drain current can be

somewhat smaller than a similar MOSFET, the gate capacitance

is also smaller, and other properties scale similarly to those of

MOSFETs. Numerical simulations of a 25 nm JFET showed


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behavior and performance comparable to reported 25 nm MOS-

FETs at the same lower supply voltage and consistent with

the JFET scaling analysis. A number of modifications to the

idealized 25 nm model to increase its performance, including

a self-aligned gate proposal and the application of techniques

already developed for MOSFETs, were outlined that may en-

able it to stand in for 25 nm MOSFETs in some circumstances,and subsequently, be scaled to the 10 nm range. If IIIV semi-

conductors replace silicon in future 10-nm-scale technologies,

JFETs have a natural advantage over MOSFETs because of the

great challenge of developing a high-quality insulator for IIIV

semiconductors. Because of the geometrical and electrical sim-

ilarities of the JFET and the MOSFET, the consequences for the

system architecture may well be modest, especially compared to

the architectural changes that would be needed for other devices

under development for MOSFET replacements. Taken together,

the results presented here suggest that the crossover point oc-

curs at a technologically relevant point between 20 and 30 nm

for silicon devices, and that JFETs may well be of interest for

upcoming silicon technology nodes, and perhaps beyond.

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