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JESD204B IP Core User Guide

Last updated for Quartus Prime Design Suite: 15.1

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Contents

JESD204B IP Core Quick Reference................................................................... 1-1

About the JESD204B IP Core..............................................................................2-1Datapath Modes........................................................................................................................................... 2-3IP Core Variation.........................................................................................................................................2-3JESD204B IP Core Configuration..............................................................................................................2-4

Run-Time Configuration................................................................................................................2-4Channel Bonding......................................................................................................................................... 2-5Performance and Resource Utilization.....................................................................................................2-6

Getting Started.................................................................................................... 3-1Introduction to Altera IP Cores.................................................................................................................3-1Licensing IP Cores....................................................................................................................................... 3-1OpenCore Plus IP Evaluation.................................................................................................................... 3-2Upgrading IP Cores..................................................................................................................................... 3-2IP Catalog and Parameter Editor...............................................................................................................3-6Design Walkthrough................................................................................................................................... 3-7

Creating a New Quartus Prime Project........................................................................................ 3-7Parameterizing and Generating the IP Core................................................................................ 3-7Generating and Simulating the IP Core Testbench.................................................................... 3-8Compiling the JESD204B IP Core Design..................................................................................3-11Programming an FPGA Device................................................................................................... 3-11

JESD204B IP Core Design Considerations............................................................................................ 3-11Integrating the JESD204B IP core in Qsys................................................................................. 3-11Pin Assignments.............................................................................................................................3-12Adding External Transceiver PLL............................................................................................... 3-13Timing Constraints For Input Clocks.........................................................................................3-13

JESD204B IP Core Parameters.................................................................................................................3-16JESD204B IP Core Component Files...................................................................................................... 3-21JESD204B IP Core Testbench.................................................................................................................. 3-21

Testbench Simulation Flow.......................................................................................................... 3-23

JESD204B IP Core Functional Description........................................................4-1Transmitter................................................................................................................................................... 4-4

TX Data Link Layer..........................................................................................................................4-5TX PHY Layer.................................................................................................................................. 4-8

Receiver......................................................................................................................................................... 4-8RX Data Link Layer..........................................................................................................................4-9RX PHY Layer................................................................................................................................ 4-12

Operation.................................................................................................................................................... 4-13

TOC-2 JESD204B IP Core User Guide

Altera Corporation

Operating Modes........................................................................................................................... 4-13Scrambler/Descrambler................................................................................................................ 4-14SYNC_N Signal.............................................................................................................................. 4-14Link Reinitialization...................................................................................................................... 4-16Link Startup Sequence...................................................................................................................4-17Error Reporting Through SYNC_N Signal................................................................................ 4-18

Clocking Scheme........................................................................................................................................4-18Device Clock................................................................................................................................... 4-20Link Clock.......................................................................................................................................4-21Local Multi-Frame Clock..............................................................................................................4-22Clock Correlation...........................................................................................................................4-23

Reset Scheme.............................................................................................................................................. 4-24Reset Sequence............................................................................................................................... 4-26

Signals..........................................................................................................................................................4-27Transmitter..................................................................................................................................... 4-27Receiver........................................................................................................................................... 4-36

Registers...................................................................................................................................................... 4-44Register Access Type Convention............................................................................................... 4-44

JESD204B IP Core Design Examples.................................................................. 5-1Supported Configurations.......................................................................................................................... 5-1Generic Design Example.............................................................................................................................5-4Presets............................................................................................................................................................ 5-5Selecting and Generating the Design Example........................................................................................ 5-6Design Example with RTL State Machine Control Unit........................................................................ 5-8

Design Example Components......................................................................................................5-10System Parameters......................................................................................................................... 5-47System Interface Signals................................................................................................................5-51Example Feature: Dynamic Reconfiguration.............................................................................5-56Generating and Simulating the Design Example.......................................................................5-62Generating the Design Example For Compilation....................................................................5-64Compiling the JESD204B IP Core Design Example................................................................. 5-64

Design Example with Nios II Processor Control Unit......................................................................... 5-65Design Example Components......................................................................................................5-65System Clocking.............................................................................................................................5-75Nios II Processor Design Example Files..................................................................................... 5-75Nios II Processor Design Example System Parameters............................................................5-77Nios II Processor Design Example System Interface Signals...................................................5-79Compiling the Design Example for Synthesis............................................................................5-81Implementing the Design on the Development Kit..................................................................5-82Running the Software Control Flow........................................................................................... 5-86Customizing the Design Example............................................................................................... 5-98

JESD204B IP Core Deterministic Latency Implementation Guidelines........... 6-1Constraining Incoming SYSREF Signal....................................................................................................6-1Programmable RBD Offset.........................................................................................................................6-2Programmable LMFC Offset......................................................................................................................6-5

JESD204B IP Core User Guide TOC-3

Altera Corporation

Maintaining Deterministic Latency during Link Reinitialization...................................................... 6-10

JESD204B IP Core Debug Guidelines.................................................................7-1Clocking Scheme..........................................................................................................................................7-1JESD204B Parameters................................................................................................................................. 7-1SPI Programming.........................................................................................................................................7-2Converter and FPGA Operating Conditions........................................................................................... 7-2Signal Polarity and FPGA Pin Assignment.............................................................................................. 7-2Debugging JESD204B Link Using SignalTap II and System Console.................................................. 7-3

Additional Information...................................................................................... 8-1JESD204B IP Core Document Revision History..................................................................................... 8-1How to Contact Altera................................................................................................................................ 8-4

TOC-4 JESD204B IP Core User Guide

Altera Corporation

JESD204B IP Core Quick Reference 12015.11.02

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The Altera JESD204B MegaCore® function is a high-speed point-to-point serial interface intellectualproperty (IP).

The JESD204B MegaCore function is part of the MegaCore IP Library, which is distributed with theQuartus® Prime software and downloadable from the Altera website at www.altera.com.

Note: For system requirements and installation instructions, refer to Altera Software Installation &Licensing.

Table 1-1: Brief Information About the JESD204B IP Core

Item Description

ReleaseInforma‐tion

Version 15.1

Release Date November 2015

Ordering Code IP-JESD204B

Product ID 0116

Vendor ID 6AF7

IP CoreInforma‐tion

Protocol Features

• Joint Electron Device Engineering Council (JEDEC) JESD204B.01, 2012 standard release specification

• Device subclass:

• Subclass 0—Backwards compatible to JESD204A.• Subclass 1—Uses SYSREF signal to support deterministic

latency.• Subclass 2—Uses SYNC_N detection to support determin‐

istic latency.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified astrademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performanceof its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.

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Item Description

IP CoreInforma‐tion

Core Features • Run-time configuration of parameters L,M, and F• Data rates up to 13.5 gigabits per second (Gbps)• Single or multiple lanes (up to 8 lanes per link)• Serial lane alignment and monitoring• Lane synchronization• Modular design that supports multidevice synchronization• MAC and PHY partitioning• Deterministic latency support• 8B/10B encoding• Scrambling/Descrambling• Avalon® Streaming (Avalon-ST) interface for transmit and

receive datapaths• Avalon Memory-Mapped (Avalon-MM) interface for Configu‐

ration and Status registers (CSR)• Dynamic generation of simulation testbench

Typical Application • Wireless communication equipment• Broadcast equipment• Military equipment• Medical equipment• Test and measurement equipment

Device Family Support • Cyclone® V FPGA device families• Arria® V FPGA device families• Arria V GZ FPGA device families• Arria 10 FPGA device families• Stratix® V FPGA device families

Refer to the device support table and What’s New in Altera IP pageof the Altera website for detailed information.

Design Tools • Qsys parameter editor in the Quartus Prime software for designcreation and compilation

• TimeQuest timing analyzer in the Quartus Prime software fortiming analysis

• ModelSim®-Altera, Aldec Riviera-Pro, VCS/VCS MX, andNCSim software for design simulation or synthesis

Related Information

• Altera Software Installation and Licensing• What's New in Altera IP• JESD204B IP Core Release Notes• Errata for JESD204B IP Core in the Knowledge Base

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Altera Corporation JESD204B IP Core Quick Reference

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About the JESD204B IP Core 22015.11.02


The Altera JESD204B IP core is a high-speed point-to-point serial interface for digital-to-analog (DAC) oranalog-to-digital (ADC) converters to transfer data to FPGA devices. This unidirectional serial interfaceruns at a maximum data rate of 13.5 Gbps. This protocol offers higher bandwidth, low I/O count andsupports scalability in both number of lanes and data rates. The JESD204B IP core addresses multi-devicesynchronization by introducing Subclass 1 and Subclass 2 to achieve deterministic latency.

The JESD204B IP core incorporates:

• Media access control (MAC)—data link layer (DLL) block that controls the link states and characterreplacement.

• Physical layer (PHY)—physical coding sublayer (PCS) and physical media attachment (PMA) block.

The JESD204B IP core does not incorporate the Transport Layer (TL) that controls the frame assemblyand disassembly. The TL and test components are provided as part of a design example component whereyou can customize the design for different converter devices.





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Figure 2-1: Typical System Application for JESD204B IP Core

The JESD204B IP core utilizes the Avalon-ST source and sink interfaces, with unidirectional flow of data,to transmit and receive data on the FPGA fabric interface.

JESD204B TXIP Core

FPGA

M Converters1 Link, L Lanes

SYNC_N

M Converters

M Converters

SYNC_N

SYNC_N

M ConvertersSYNC_N

JESD204B RXIP Core

1 Link, L Lanes

1 Link, L Lanes

1 Link, L Lanes

DAC DeviceClock 1

ADC DeviceClock 1

Multi-DeviceSynchronizationthrough Subclass 1 or Subclass 2

Multi-DeviceSynchronizationthrough Subclass 1or Subclass 2

Logic Device (TX)Device Clock 2

Logic Device (RX)Device Clock 2

JESD204B TXIP Core

JESD204B RXIP Core

Key features of the JESD204B IP core:

• Data rate of up to 13.5 Gbps• Run-time JESD204B parameter configuration (L, M, F, S, N, K, CS, CF)• MAC and PHY partitioning for portability• Subclass 0 mode for backward compatibility to JESD204A• Subclass 1 mode for deterministic latency support (using SYSREF) between the ADC/DAC and logic

device• Subclass 2 mode for deterministic latency support (using SYNC_N) between the ADC/DAC and logic

device• Multi-device synchronization

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Altera Corporation About the JESD204B IP Core

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Datapath ModesThe JESD204B IP core supports TX-only, RX-only, and Duplex (TX and RX) mode. The IP core is aunidirectional protocol where interfacing to ADC utilizes the transceiver RX path and interfacing to DACutilizes the transceiver TX path.

The JESD204B IP core generates a single link with a single lane and up to a maximum of 8 lanes. If thereare two ADC links that need to be synchronized, you have to generate two JESD204B IP cores and thenmanage the deterministic latency and synchronization signals, like SYSREF and SYNC_N, at your customwrapper level.

The JESD204B IP core supports duplex mode only if the LMF configuration for ADC (RX) is the same asDAC (TX) and with the same data rate. This use case is mainly for prototyping with internal serialloopback mode. This is because typically as a unidirectional protocol, the LMF configuration of converterdevices for both DAC and ADC are not identical.

IP Core VariationThe JESD204B IP core has three core variations:

• JESD204B MAC only• JESD204B PHY only• JESD204B MAC and PHY

In a subsystem where there are multiple ADC and DAC converters, you need to use the Quartus Primesoftware to merge the transceivers and group them into the transceiver architecture. For example, tocreate two instances of the JESD204B TX IP core with four lanes each and four instances of the JESD204RX IP core with two lanes each, you can apply one of the following options:

• MAC and PHY option

1. Generate JESD204B TX IP core with four lanes and JESD204B RX IP core with two lanes.2. Instantiate the desired components.3. Use the Quartus Prime software to merge the PHY lanes.

• MAC only and PHY only option—based on the configuration above, there are a total of eight lanes induplex mode.

1. Generate the JESD204B Duplex PHY with a total of eight lanes. (TX skew is reduced in thisconfiguration as the channels are bonded).

2. Generate the JESD204B TX MAC with four lanes and instantiate it two times.3. Generate the JESD204B RX MAC with two lanes and instantiate it four times.4. Create a wrapper to connect the JESD204B TX MAC and RX MAC with the JESD204B Duplex

PHY.

Note: If the data rate for TX and RX is different, the transceiver does not allow duplex mode to generate aduplex PHY. In this case, you have to generate a RX-only PHY on the RX data rate and a TX-onlyPHY on the TX data rate.

UG-011422015.11.02 Datapath Modes 2-3

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JESD204B IP Core ConfigurationTable 2-1: JESD204B IP Core Configuration

Symbol Description Value

L Number of lanes per converter device 1-8M Number of converters per device 1-256F Number of octets per frame 1, 2, 4-256S Number of transmitted samples per converter per frame 1-32N Number of conversion bits per converter 1-32N' Number of transmitted bits per sample (JESD204 word size,

which is in nibble group)1-32

K Number of frames per multiframe 17/F ≤ K ≤ 32 ; 1-32CS Number of control bits per conversion sample 0-3CF Number of control words per frame clock period per link 0-32HD High Density user data format 0 or 1LMFC Local multiframe clock (F × K /4) link clock counts (1)

Run-Time ConfigurationThe JESD204B IP core allows run-time configuration of LMF parameters.

The most critical parameters that must be set correctly during IP generation are the L and F parameters.Parameter L denotes the maximum lanes supported while parameter F denotes the size of the deskewbuffer needed for deterministic latency. The hardware generates during parameterization, which meansthat run-time programmability can only fall back from the parameterized and generated hardware, butnot beyond the parameterized IP core.

You can use run-time configuration for prototyping or evaluating the performance of converter deviceswith various LMF configurations. However, in actual production,Altera recommends that you generatethe JESD204B IP core with the intended LMF to get an optimized gate count.

For example, if a converter device supports LMF = 442 and LMF = 222, to check the performance for bothconfigurations, you need to generate the JESD204B IP core with maximum F and L, which is L = 4 and F= 2. During operation, you can use the fall back configuration to disable the lanes that are not used inLMF = 222 mode. You must ensure that other JESD204B configurations like M, N, S, CS, CF, and HD donot violate the parameter F setting. You can access the Configuration and Status Register (CSR) space tomodify other configurations such as:

• K (multi-frame)• device and lane IDs• enable or disable scrambler• enable or disable character replacement

(1) The value of F x K must be divisible by 4.

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F Parameter

This parameter indicates how many octets per frame per lane that the JESD204B link is operating in. Youmust set the F parameter according to the JESD204B IP Specification for a correct data mapping.

To support the High Density (HD) data format, the JESD204B IP core tracks the start of frame and end offrame because F can be either an odd or even number. The start of frame and start of multi-frame wraparound the 32-bits data width architecture. The RX IP core outputs the start of frame (sof[3:0]) andstart of multiframe (somf[3:0]), which act as markers, using the Avalon-ST data stream. Based on thesemarkers, the transport layer build the frames.

In a simpler system where the HD data format is set to 0, the F will always be 1, 2, 4, 6, 8, and so forth.This simplifies the transport layer design, so you do not need to use the sof[3:0] and somf[3:0]markers.

Channel BondingThe JESD204B IP core supports channel bonding—bonded and non-bonded modes.

The channel bonding mode that you select may contribute to the transmitter channel-to-channel skew. Abonded transmitter datapath clocking provides low channel-to-channel skew as compared to non-bondedchannel configurations.

Table 2-2: Maximum Number of Lanes (L) Supported in Bonded and Non-Bonded Mode

• In PHY-only mode, you can generate up to 32 channels, provided that the channels are on the same side. InMAC and PHY integrated mode, you can generate up to 8 channels.

• In bonded channel configuration, the lower transceiver clock skew and equal latency in the transmitter phasecompensation FIFO for all channels result in a lower channel-to-channel skew. You must use contiguouschannels when you select bonded mode. The JESD204B IP core automatically selects between ×6, ×N orfeedback compensation (fb_compensation) bonding depending on the number of transceiver channels you set.

• In non-bonded channel configuration, the transceiver clock skew is higher and latency is unequal in thetransmitter phase compensation FIFO for each channel. This may result in a higher channel-to-channel skew.

Device Family Core Variation Bonding Mode Configuration Maximum Number ofLanes (L)

Arria VPHY only

Bonded 32 (2)

Non-bonded 32 (2)

MAC and PHYBonded 6Non-bonded 8

Arria V GZ

Arria 10

Stratix V

PHY onlyBonded 32 (2)

Non-bonded 32 (2)

MAC and PHYBonded 8Non-bonded 8

(2) The maximum lanes listed here is for configuration simplicity. Refer to the Altera Transceiver PHY UserGuide for the actual number of channels supported.

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Table 2-3: Clock Network Selection for Bonded Mode

Device Family L ≤ 6 L > 6

Arria 10 ×6 ×N or feedback compensation (3)

Stratix V ×6 feedback compensationArria V ×N ×NArria V GZ ×6 feedback compensationCyclone V ×N ×N

Related InformationArria 10 Device Datasheet

Performance and Resource UtilizationTable 2-4: JESD204B IP Core FPGA Performance

Device Family PMA SpeedGrade

FPGA FabricSpeed Grade

Data RateLink Clock FMAX

(MHz)Enable Hard PCS(Gbps)

Enable Soft PCS(Gbps) (4)

Cyclone V5 <Any supported

speed grade>1.0 to 5.0 — 125.00

6 6 or 7 1.0 to 3.125 — 78.125Arria V GX/SX <Any supported

speed grade><Any supportedspeed grade>

1.0 to 6.55 — (5) 163.84

Arria V GT/ST <Any supportedspeed grade>

<Any supportedspeed grade>

1.0 to 7.50 — (5) 187.50

Arria V GZ2 3 2.0 to 9.9 — (5) 247.503 4 2.0 to 8.8 — (5) 220.00

(3) Feedback compensation can be enabled in the ATX PLL and fPLL parameter editor. Refer to the Arria 10datasheet for the maximum data rate and channel span supported by the ×N and feedback compensationclock network.

(4) Select Enable Soft PCS to achieve maximum data rate. For the TX IP core, enabling soft PCS incurs anadditional 3–8% increase in resource utilization. For the RX IP core, enabling soft PCS incurs an additional10–20% increase in resource utilization.

(5) Enabling Soft PCS does not increase the data rate for the device family and speed grade. You arerecommended to select the Enable Hard PCS option.

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Device Family PMA SpeedGrade

FPGA FabricSpeed Grade

Data RateLink Clock FMAX

(MHz)Enable Hard PCS(Gbps)

Enable Soft PCS(Gbps) (4)

Arria 10

1 1 2.0 to 12.0 2.0 to 13.5 337.50

2 1 2.0 to 12.0 2.0 to 13.5 337.502 2 2.0 to 9.83 2.0 to 13.5 337.503 1 2.0 to 12.0 2.0 to 13.5 337.503 2 2.0 to 9.83 2.0 to 13.5 —4 3 2.0 to 8.83 2.0 to 12.5 312.505 3 2.0 to 8.0 2.0 to 8.0 200.00

Stratix V

1 1 or 2 2.0 to 12.2 2.0 to 12.5 312.502 1 or 2 2.0 to 12.2 2.0 to 12.5 312.502 3 2.0 to 9.8 2.0 to 12.5 (6) 312.503 1, 2, 3, or 4 2.0 to 8.5 2.0 to 8.5 212.50

The following table lists the resources and expected performance of the JESD204B IP core. These resultsare obtained using the Quartus Prime software targeting the following Altera FPGA devices:

• Cyclone V : 5CGTFD9E5F31I7• Arria V : 5AGXFB3H4F35C5• Arria V GZ : 5AGZME5K2F40C3• Arria 10 : 10AX115H2F34I2SGES• Stratix V : 5SGXEA7H3F35C3

All the variations for resource utilization are configured with the following parameter settings:

Table 2-5: Parameter Settings To Obtain the Resource Utilization Data

Parameter Setting

JESD204B Wrapper Base and PHYJESD204B Subclass 1Data Rate 5 GbpsPCS Option Enabled Hard PCSPLL Type • ATX (for 10 series devices)

• CMU (for V series devices)

Bonding Mode Non-bonded

(4) Select Enable Soft PCS to achieve maximum data rate. For the TX IP core, enabling soft PCS incurs anadditional 3–8% increase in resource utilization. For the RX IP core, enabling soft PCS incurs an additional10–20% increase in resource utilization.

(6) When using Soft PCS mode at 12.5 Gbps, the timing margin is very limited. You are advised to enableHIGH fitter effort, register duplication, and register retiming to improve timing performance.

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Parameter Setting

Reference Clock Frequency 125.0 MHzOctets per frame (F) 1Enable Scrambler (SCR) OffEnable Error Code Correction (ECC_EN) Off

Table 2-6: JESD204B IP Core Resource Utilization

The numbers of ALMs and logic registers in this table are rounded up to the nearest 10.

Note: The resource utilization data are extracted from a full design which includes the Altera Transceiver PHYReset Controller IP Core. Thus, the actual resource utilization for the JESD204B IP core should be smallerby about 15 ALMs and 20 registers.

Device Family Data Path Number ofLanes (L)

ALMs ALUTs LogicRegisters

Memory Block(M10K/M20K) (7) (8)

Cyclone V

RX

1 1029 1513 1198 12 1562 2297 1827 24 2787 3955 3081 48 5238 7389 5585 8

TX

1 728 1147 950 02 881 1417 1066 04 1204 1930 1300 08 1723 2837 1770 0

Arria V

RX

1 1028 1513 1197 12 1569 2297 1827 24 2776 3955 3080 48 5207 7389 5581 8

TX

1 735 1147 947 02 888 1417 1066 04 1200 1930 1300 08 1728 2853 1768 0

(7) M10K for Arria V device, M20K for Arria V GZ, Stratix V and Arria 10 devices.(8) The Quartus Prime software may auto-fit to use MLAB when the memory size is too small. Conversion from

MLAB to M20K or M10K was performed for the numbers listed above.

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Device Family Data Path Number ofLanes (L)

ALMs ALUTs LogicRegisters

Memory Block(M10K/M20K) (7) (8)

Arria V GZ

RX

1 1051 1520 1214 0

2 1610 2328 1857 04 2890 4025 3145 08 5430 7511 5710 0

TX

1 728 1150 949 02 938 1489 1085 04 1363 2134 1361 08 2122 3355 1907 0

Arria 10

RX

1 1045 1500 1205 02 1616 2249 1828 04 2813 3850 3070 08 5437 7157 5555 0

TX

1 721 1121 949 02 911 1404 1070 04 1259 1937 1309 08 1892 2938 1791 0

Stratix V

RX

1 1051 1520 1215 02 1619 2328 1857 04 2897 4025 3142 08 5427 7511 5712 0

TX

1 727 1150 948 02 948 1489 1085 04 1356 2134 1359 08 2120 3355 1907 0

Related Information

• JESD204B IP Core Parameters on page 3-16• Fitter Resources Reports in the Quartus Prime Help

Information about the Quartus Prime resource utilization reporting, including ALMs needed.

(7) M10K for Arria V device, M20K for Arria V GZ, Stratix V and Arria 10 devices.(8) The Quartus Prime software may auto-fit to use MLAB when the memory size is too small. Conversion from

MLAB to M20K or M10K was performed for the numbers listed above.

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Getting Started 32015.11.02


The JESD204B IP core is part of the MegaCore IP Library distributed with the Quartus Prime softwareand downloadable from the Altera website at www.altera.com.

Related Information

• Altera Software Installation & Licensing• Introduction to Altera IP Cores

Provides general information about all Altera IP cores, including parameterizing, generating,upgrading, and simulating IP.

• Creating Version-Independent IP and Qsys Simulation ScriptsCreate simulation scripts that do not require manual updates for software or IP version upgrades.

• Project Management Best PracticesGuidelines for efficient management and portability of your project and IP files.

Introduction to Altera IP CoresAltera® and strategic IP partners offer a broad portfolio of configurable IP cores optimized for Alteradevices. The Quartus Prime software installation includes the Altera IP library. You can integrateoptimized and verified Altera IP cores into your design to shorten design cycles and maximizeperformance. The Quartus Prime software also supports integration of IP cores from other sources. Usethe IP Catalog to efficiently parameterize and generate synthesis and simulation files for a custom IPvariation. The Altera IP library includes the following types of IP cores:

• Basic functions• DSP functions• Interface protocols• Low power functions• Memory interfaces and controllers• Processors and peripherals

Licensing IP CoresThe Altera IP Library provides many useful IP core functions for your production use without purchasingan additional license. Some Altera MegaCore IP functions require that you purchase a separate license forproduction use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulation





mailto:[email protected]?subject=Feedback%20on%20(UG-01142%202015.11.02)%20Getting%20Started&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.

http://www.altera.com/literature/manual/quartus_install.pdf



https://documentation.altera.com/#/link/mwh1409960181641/esc1444754592005/en-us




and compilation in the Quartus Prime software. After you are satisfied with functionality andperformance, visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 3-1: IP Core Installation Path

acds

quartus - Contains the Quartus Prime softwareip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code<IP core name> - Contains the IP core source files

Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is<home directory>/altera/ <version number>.

OpenCore Plus IP EvaluationAltera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation andhardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to takeyour design to production. OpenCore Plus supports the following evaluations:

• Simulate the behavior of a licensed IP core in your system.• Verify the functionality, size, and speed of the IP core quickly and easily.• Generate time-limited device programming files for designs that include IP cores.• Program a device with your IP core and verify your design in hardware.

OpenCore Plus evaluation supports the following two operation modes:

• Untethered—run the design containing the licensed IP for a limited time.• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a

connection between your board and the host computer.

Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design timesout.

Related Information

• Altera Licensing Site• Altera Software Installation and Licensing Manual

Upgrading IP CoresIP core variants generated with a previous version or different edition of the Quartus Prime software mayrequire upgrading before use in the current version or edition of the Quartus Prime software. When youopen a project containing outdated IP, the Project Navigator displays a banner indicating the IP upgradestatus. Click Launch IP Upgrade Tool, or Project > Upgrade IP Components to upgrade outdated IPcores.

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Figure 3-2: IP Upgrade Alert in Project Navigator

IP Upgradenotification

Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required, optional, orunsupported for IP cores in your design. You must upgrade IP cores that require upgrade before you cancompile the IP variation in the current version of the Quartus Prime software.

The upgrade process preserves the original IP variation file in the project directory as <my_variant>_BAK.qsys for IP targeting Arria 10 and later devices, and as <my_variant>_BAK.v, .sv, or .vhd for legacy IPtargeting 28nm devices and greater.

Note: Upgrading IP cores for Arria 10 and later devices may append a unique identifier to the original IPcore entity name(s), without similarly modifying the IP instance name. There is no requirement toupdate these entity references in any supporting Quartus Prime file; such as the Quartus PrimeSettings File (.qsf), Synopsys Design Constraints File (.sdc), or SignalTap File (.stp), if these filescontain instance names. The Quartus Prime software reads only the instance name and ignores theentity name in paths that specify both names. Use only instance names in assignments.

Table 3-1: IP Core Upgrade Status

IP Core Status Description

IP Upgraded

Your IP variation uses the lastest version of the IP core.

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IP Core Status Description

IP Upgrade Optional

Upgrade is optional for this IP variation in the current version of the QuartusPrime software. You can upgrade this IP variation to take advantage of thelatest development of this IP core. Alternatively you can retain previous IPcore characteristics by declining to upgrade. Refer to the Description fordetails about IP core version differences. If you do not upgrade the IP, the IPvariation synthesis and simulation files are unchanged and you cannot modifyparameters until upgrading.

IP Upgrade Required

You must upgrade the IP variation before compiling in the current version ofthe Quartus Prime software. Refer to the Description for details about IP coreversion differences.

IP Upgrade Unspported

Upgrade of the IP variation is not supported in the current version of theQuartus Prime software due to incompatibility with the current version of theQuartus Prime software. You are prompted to replace the unsupported IP corewith a supported equivalent IP core from the IP Catalog. Refer to the Descrip‐tion for details about IP core version differences and links to Release Notes.

IP End of Life

Altera designates the IP core as end-of-life status. You may or may not be ableto edit the IP core in the parameter editor. Support for this IP corediscontinues in future releases of the Quartus Prime software.

IP Upgrade MismatchWarning

Warning of non-critical IP core differences in migrating IP to another devicefamily.

Encrypted IP Core

The IP variation is encrypted.

Follow these steps to upgrade IP cores:

1. In the latest version of the Quartus Prime software, open the Quartus Prime project containing anoutdated IP core variation. The Upgrade IP Components dialog automatically displays the status of IPcores in your project, along with instructions for upgrading each core. Click Project > Upgrade IPComponents to access this dialog box manually.

2. To upgrade one or more IP cores that support automatic upgrade, ensure that the Auto Upgradeoption is turned on for the IP core(s), and then click Perform Automatic Upgrade. The Status and

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Version columns update when upgrade is complete. Example designs provided with any Altera IP coreregenerate automatically whenever you upgrade an IP core.

3. To manually upgrade an individual IP core, select the IP core and then click Upgrade in Editor (orsimply double-click the IP core name. The parameter editor opens, allowing you to adjust parametersand regenerate the latest version of the IP core.

Figure 3-3: Upgrading IP Cores

Runs “Auto Upgrade” on all supported outdated coresOpens editor for manual IP upgrade

“Auto Upgrade”supported

Upgrade required

Upgrade details

“Auto Upgrade”successful

Note: IP cores older than Quartus Prime software version 12.0 do not support upgrade. Altera verifiesthat the current version of the Quartus Prime software compiles the previous version of each IPcore. The Altera IP Release Notes reports any verification exceptions for Altera IP cores. Alteradoes not verify compilation for IP cores older than the previous two releases.

Related InformationAltera IP Release Notes

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IP Catalog and Parameter EditorThe IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate IPcores into your project. Use the IP Catalog and parameter editor to select, customize, and generate filesrepresenting the custom IP variation in your project.

Search for installed IP

Double-click to customizeright-click for details

Filter IP by device

The IP Catalog displays the installed IP cores available for your design. Double-click any IP core to launchthe parameter editor and generate files representing your IP variation. Use the following features to helpyou quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have noproject open, select the Device Family in IP Catalog.

• Type in the Search field to locate any full or partial IP core name in IP Catalog.• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's

installation folder, and click links to IP documentation.• Click Search for Partner IP, to access partner IP information on the Altera website.

The parameter editor prompts you to specify an IP variation name, optional ports, and output filegeneration options. The parameter editor generates a top-level Qsys system file (.qsys) or Quartus PrimeIP file (.qip) representing the IP core in your project. You can also parameterize an IP variation without anopen project.

The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes exclusivesystem interconnect, video and image processing, and other system-level IP that are not available in theQuartus Prime IP Catalog. For more information about using the Qsys IP Catalog, refer to Creating aSystem with Qsys in the Quartus Prime Handbook.

Note: The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-InManager for IP selection and parameterization, beginning in Quartus II software version 14.0. Usethe IP Catalog and parameter editor to locate and paramaterize Altera IP cores.

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Design WalkthroughThis walkthrough explains how to create a JESD204B IP core design using Qsys in the Quartus Primesoftware. After you generate a custom variation of the JESD204B IP core, you can incorporate it into youroverall project.

Creating a New Quartus Prime ProjectYou can create a new Quartus Prime project with the New Project Wizard. This process allows you to:

• specify the working directory for the project.• assign the project name.• designate the name of the top-level design entity.

1. Launch the Quartus Prime software.2. On the File menu, click New Project Wizard.3. In the New Project Wizard: Directory, Name, Top-Level Entity page, specify the working directory,

project name, and top-level design entity name. Click Next.4. In the New Project Wizard: Add Files page, select the existing design files (if any) you want to include

in the project.(9) Click Next.5. In the New Project Wizard: Family & Device Settings page, select the device family and specific

device you want to target for compilation. Click Next.6. In the EDA Tool Settings page, select the EDA tools you want to use with the Quartus Prime software

to develop your project.7. Review the summary of your chosen settings in the New Project Wizard window, then click Finish to

complete the Quartus Prime project creation.

Parameterizing and Generating the IP Core

Before you begin

Refer to Table 3-6 for the IP core parameter values and description.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click on the JESD204B IP core.2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files

in your project. If prompted, also specify the target Altera device family and output file HDLpreference. Click OK.

3. In the Main tab, set the following options:

• Jesd204b wrapper• Data path• Jesd204b subclass• Data Rate• PCS Option• PLL Type

(9) To include existing files, you must specify the directory path to where you installed the JESD204B IP core.You must also add the user libraries if you installed the MegaCore IP Library in a different directory fromwhere you installed the Quartus Prime software.

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• Bonding Mode• PLL/CDR Reference Clock Frequency• Enable Bit reversal and Byte reversal• Enable Transceiver Dynamic Reconfiguration• Enable Altera Debug Master Endpoint• Enable Capability Registers• Set user-defined IP identifier• Enable Control and Status Registers• Enable Prbs Soft Accumulators

4. In the Jesd204b Configurations tab, select the following configurations:

• Common configurations (L, M, Enable manual F configuration, F, N, N', S, K)• Advanced configurations (SCR, CS, CF, HD, ECC_EN, PHADJ, ADJCNT, ADJDIR)

5. In the Configurations and Status Registers tab, set the the following configurations:

• Device ID• Bank ID• Lane ID• Lane checksum

6. After parameterizing the core, go to the Example Design tab and click Generate Example Design tocreate the simulation testbench. Skip to step 8 if you do not want to generate the design example.

7. Set a name for your <example_design_directory> and click OK to generate supporting files and scripts.The testbench and scripts are located in the <example_design_directory>/ip_sim folder.

The Generate Example Design option generates supporting files for the following entities:

• IP core for simulation—refer to Generating and Simulating the IP Core Testbench on page 3-8• IP core design example for simulation—refer to Generating and Simulating the Design Example

on page 5-62• IP core design example for synthesis—refer to Compiling the JESD204B IP Core Design Example

on page 5-648. Click Finish or Generate HDL to generate synthesis and other optional files matching your IP

variation specifications. The parameter editor generates the top-level .qip or .qsys IP variation file andHDL files for synthesis and simulation.

The top-level IP variation is added to the current Quartus Prime project. Click Project > Add/RemoveFiles in Project to manually add a .qip or .qsys file to a project. Make appropriate pin assignments toconnect ports.

Note: Some parameter options are grayed out if they are not supported in a selected configuration or it isa derived parameter.

Related InformationSelecting and Generating the Design Example on page 5-6

Generating and Simulating the IP Core TestbenchYou can simulate your JESD204B IP core variation by using the provided IP core demonstrationtestbench.

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To use the JESD204B IP core testbench, follow these steps:

1. Generate the simulation model. Refer to Generating the Testbench Simulation Model on page 3-9.2. Simulate the testbench using the simulator-specific scripts that you have generated. Refer to

Simulating the IP Core Testbench on page 3-9.

Note: Some configurations are preset and are not programmable in the JESD204B IP core testbench. Formore details, refer to JESD204B IP Core Testbench on page 3-21 or the README.txt file locatedin the <example_design_directory>/ip_sim folder.

Generating the Testbench Simulation Model

To generate the testbench simulation model, execute the generated script (gen_sim_verilog.tcl orgen_sim_vhdl.tcl) located in the <example_design_directory>/ip_sim folder.

To run the Tcl script using the Quartus Prime sofware, follow these steps:

1. Launch the Quartus Prime software.2. On the View menu, click Utility Windows > Tcl Console.3. In the Tcl Console, type cd <example_design_directory>/ip_sim to go to the specified

directory.4. Type source gen_sim_verilog.tcl (Verilog) or source gen_sim_vhdl.tcl (VHDL)

to generate the simulation files.

To run the Tcl script using the command line, follow these steps:

1. Obtain the Quartus Prime software resource.2. Type cd <example_design_directory>/ip_sim to go to the specified directory.3. Type quartus_sh -t gen_sim_verilog.tcl (Verilog) or quartus_sh -t

gen_sim_vhdl.tcl (VHDL) to generate the simulation files.

Simulating the IP Core Testbench

The JESD204B IP core simulation supports the following simulators:

• ModelSim-Altera SE/AE• VCS• VCS MX• Cadence• Aldec Riviera

Note: VHDL is not supported in VCS and Aldec Riviera (for Arria 10 devices only) simulators.

Table 3-2: Simulation Setup Scripts

This table lists the simulation setup scripts and run scripts.Simulator File Directory Script

ModelSim®-AlteraSE/AE

<example_design_directory>/ip_sim/testbench/setup_scripts/mentor

msim_setup.tcl

VCS <example_design_directory>/ip_sim/testbench/setup_scripts/synopsys/vcs

vcs_setup.sh

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Simulator File Directory Script

VCS MX <example_design_directory>/ip_sim/testbench/setup_scripts/synopsys/vcsmx

vcsmx_setup.sh

synopsys_sim.setup

Aldec Riviera <example_design_directory>/ip_sim/testbench/setup_scripts/aldec

rivierapro_setup.tcl

Cadence <example_design_directory>/ip_sim/testbench/setup_scripts/cadence

ncsim_setup.sh

Table 3-3: Simulation Run Scripts

Simulator File Directory Script

ModelSim-AlteraSE/AE

<example_design_directory>/ip_sim/testbench/mentor run_altera_jesd204_tb.tcl

VCS <example_design_directory>/ip_sim/testbench/synopsys/vcs run_altera_jesd204_tb.sh

VCS MX <example_design_directory>/ip_sim/testbench/synopsys/vcsmx

run_altera_jesd204_tb.sh

Aldec Riviera <example_design_directory>/ip_sim/testbench/aldec run_altera_jesd204_tb.tcl

Cadence <example_design_directory>/ip_sim/testbench/cadence run_altera_jesd204_tb.sh

To simulate the testbench design using the ModelSim-Altera or Aldec Riviera-PRO simulator, followthese steps:

1. Launch the ModelSim-Altera or Aldec Riviera-PRO simulator.2. On the File menu, click Change Directory > Select <example_design_directory>/ip_sim/testbench/

<simulator name>.3. On the File menu, click Load > Macro file. Select run_altera_jesd204_tb.tcl. This file compiles the

design and runs the simulation automatically, providing a pass/fail indication on completion.

To simulate the testbench design using the VCS, VCS MX (in Linux), or Cadence simulator, follow thesesteps:

1. Launch the VCS, VCS MX, or Cadence simulator.2. On the File menu, click Change Directory > Select <example_design_directory>/ip_sim/testbench/

<simulator name>.3. Run the run_altera_jesd204_tb.sh file. This file compiles the design and runs the simulation automat‐

ically, providing a pass/fail indication on completion.

Related InformationSimulating Altera DesignsMore information about Altera simulation models.

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Compiling the JESD204B IP Core Design

Before you begin

Refer to the JESD204B IP Core Design Considerations on page 3-11 before compiling the JESD204BIP core design.

To compile your design, click Start Compilation on the Processing menu in the Quartus Prime software.You can use the generated .qip file to include relevant files into your project.

Related Information

• JESD204B IP Core Design Considerations on page 3-11• Quartus Prime Help

More information about compilation in Quartus Prime software.

Programming an FPGA DeviceAfter successfully compiling your design, program the targeted Altera device with the Quartus PrimeProgrammer and verify the design in hardware. For instructions on programming the FPGA device, referto the Device Programming section in the Quartus Prime Handbook.

Related InformationDevice Programming

JESD204B IP Core Design ConsiderationsYou must be aware of the following conditions when integrating the JESD204B IP core in your design:

• Intergrating the IP core in Qsys• Pin assignments• Adding external transceiver PLL• Timing constraints for the input clock

Integrating the JESD204B IP core in QsysYou can integrate the JESD204B IP core with other Qsys components within Qsys.

You can connect standard interfaces like clock, reset, Avalon-MM, Avalon-ST, HSSI bonded clock, HSSIserial clock, and interrupt interfaces within Qsys. However, for conduit interfaces, you are advised toexport all those interfaces and handle them outside of Qsys. (10) This is because conduit interfaces are notpart of the standard interfaces. Thus, there is no guarantee on compatibility between different conduitinterfaces.

Note: The Transport Layer provided in this JESD204B IP core design example is not supported in Qsys.Therefore, you must export all interfaces that connect to the Transport Layer (for example,jesd204_tx_link interface) and connect them to a transport layer outside of Qsys.

(10) You can also connect conduit interfaces within Qsys but you must create adapter components to handle allthe incompatibility issues like incompatible signal type and width.

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Figure 3-4: Example of Connecting JESD204B IP Core with Other Qsys Components in Qsys

Figure shows an example of how you can connect the IP core with other Qsys components in Qsys.

Related InformationTransport Layer on page 5-15

Pin AssignmentsSet the pin assignments before you compile to provide direction to the Quartus Prime software Fitter tool.You must also specify the signals that should be assigned to device I/O pins.

You can create virtual pins to avoid making specific pin assignments for top-level signals. This is usefulwhen you want to perform compilation, but are not ready to map the design to hardware. Alterarecommends that you create virtual pins for all unused top-level signals to improve timing closure.

Note: Do not create virtual pins for the clock or reset signals.

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Adding External Transceiver PLLThe JESD204B IP core variations that target an Arria 10 FPGA device require external transceiver PLLsfor compilation.

JESD204B IP core variations that target a V-series FPGA device contain transceiver PLLs. Therefore, noexternal PLLs are required for compilation.

You are recommend to use an ATX PLL or CMU PLL to get a better jitter performance.

Note: The PMA width is 20 bits for Hard PCS and 40 bits for Soft PCS.

Related InformationArria 10 Transceiver PHY User GuideMore information about the Arria 10 transceiver PLLs and clock network.

Timing Constraints For Input ClocksWhen you generate the JESD204B IP core variation, the Quartus Prime software generates a SynopsysDesign Constraints File (.sdc) that specifies the timing constraints for the input clocks to your IP core.

When you generate the JESD204B IP core, your design is not yet complete and the JESD204B IP core isnot yet connected in the design. The final clock names and paths are not yet known. Therefore, theQuartus Prime software cannot incorporate the final signal names in the .sdc file that it automaticallygenerates. Instead, you must manually modify the clock signal names in this file to integrate theseconstraints with the timing constraints for your full design.

This section describes how to integrate the timing constraints that the Quartus Prime software generateswith your IP core into the timing constraints for your design.

The Quartus Prime software automatically generates the altera_jesd204.sdc file that contains the JESD204BIP core's timing constraints.

Three clocks are created at the input clock port:

• JESD204B TX IP core:

• txlink_clk

• reconfig_to_xcvr[0] (for Arria V, Cyclone V, and Stratix V devices only)• reconfig_clk (for Arria 10 device only)• tx_avs_clk

• JESD204B RX IP core:

• rxlink_clk

• reconfig_to_xcvr[0] (for Arria V, Cyclone V, and Stratix V devices only)• reconfig_clk (for Arria 10 device only)• rx_avs_clk

In a functional system design, these clocks (except for reconfig_to_xcvr[0] clock) are typicallyprovided by the core PLL.

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In the .sdc file for your project, make the following command changes:

• Specify the PLL clock reference pin frequency using the create_clock command.• Derive the PLL generated output clocks from the Altera PLL IP Core (for Arria V, Cyclone V and

Stratix V) or Altera I/O PLL IP Core (for Arria 10) using the derive_pll_clocks command.• Comment out the create_clock commands for the txlink_clk, reconfig_to_xcvr[0] or

reconfig_clk, and tx_avs_clk, rxlink_clk, and rx_avs_clk clocks in the altera_jesd204.sdc file.• Identify the base and generated clock name that correlates to the txlink_clk, reconfig_clk, and

tx_avs_clk, rxlink_clk, and rx_avs_clk clocks using the report_clock command.• Describe the relationship between base and generated clocks in the design using the

set_clock_groups command.

After you complete your design, you must modify the clock names in your .sdc file to the full-design clocknames, taking into account both the IP core instance name in the full design, and the design hierarchy. Becareful when adding the timing exceptions based on your design, for example, when the JESD204B IPcore handles asynchronous timing between the txlink_clk, rxlink_clk, pll_ref_clk, tx_avs_clk,rx_avs_clk, and reconfig_clk (for Arria 10 only) clocks.

The table below shows an example of clock names in the altera_jesd204.sdc and input clock names in theuser design. In this example, there is a dedicated input clock for the transceiver TX PLL and CDR at therefclk pin. The device_clk is the input to the core PLL clkin pin. The IP core and transceiver Avalon-MM interfaces have separate external clock sources with different frequencies.

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Table 3-4: Example A

Original clocknames in altera_

jesd204.sdc

User design inputclock names

Frequency(MHz)

Recommended SDC timing constraint

tx_pll_ref_clkxcvr_tx_rx_refclk 250 create_clock -name xcvr_tx_rx_refclk -period 4.0

[get_ports xcvr_tx_rx_refclk ]

create_clock -name device_clk -period 8.0 [get_portsdevice_clk]

create_clock -name jesd204_avs_clk -period 10.0[get_ports jesd204_avs_clk]

create_clock -name phy_mgmt_clk -period 13.3 [get_ports phy_mgmt_clk]

derive_pll_clocks

set_clock_groups -asynchronous \

-group {xcvr_tx_rx_refclk \

<base and generated clock names as reported byreport_clock commands> \

} \

-group {device_clk \


} \

-group {jesd204_avs_clk} \

-group {phy_mgmt_clk \


}

rx_pll_ref_clk

txlink_clkdevice_clk 125

rxlink_clk

tx_avs_clkjesd204_avs_clk 100

rx_avs_clk

reconfig_clk(11)

phy_mgmt_clk 75

However, if your design requires you to connect the rx_avs_clk and reconfig_clk to the same clock,you need to put them in the same clock group.

The table below shows an example where the device_clk in this design is an input into the transceiverrefclk pin. The IP core's Avalon-MM interface shares the same clock source as the transceivermanagement clock.

(11) For Arria 10 device only.

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Table 3-5: Example B

Original clocknames in altera_

jesd204.sdc

User design inputclock names

Frequency(MHz)

Recommended SDC timing constraint

tx_pll_ref_clk

device_clk 125

create_clock -name device_clk -period 8.0 [get_portsdevice_clk]

create_clock -name mgmt_clk -period 10.0 [get_portsmgmt_clk]

derive_pll_clocks

set_clock_groups -asynchronous \

-group {device_clk \


} \

-group {mgmt_clk \


}

rx_pll_ref_clk

txlink_clk

rxlink_clk

tx_avs_clk

mgmt_clk 100

rx_avs_clk

reconfig_clk(12)

JESD204B IP Core ParametersTable 3-6: JESD204B IP Core Parameters

Parameter Value Description

Main TabDevice Family • Arria V

• Arria V GZ• Arria 10• Cyclone V• Stratix V

Select the targeted device family.

JESD204B Wrapper • Base Only• PHY Only• Both Base

and PHY

Select the JESD204B wrapper.

• Base Only—generates the DLL only.• PHY Only—generates the transceiver PHY layer only (soft

and hard PCS).• Both Base and PHY—generates both DLL and transceiver

PHY layers.

(12) For Arria 10 device only.

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Data Path • Receiver• Transmitter• Duplex

Select the operation modes. This selection enables or disablesthe receiver and transmitter supporting logic.

• RX—instantiates the receiver to interface to the ADC.• TX—instantiates the transmitter to interface to the DAC.• Duplex—instantiates the receiver and transmitter to

interface to both the ADC and DAC.

JESD204B Subclass • 0• 1• 2

Select the JESD204B subclass modes.

• 0—Set subclass 0• 1—Set subclass 1• 2—Set subclass 2

Data Rate 1.0–13.5 Set the data rate for each lane. (13)

• Cyclone V—1.0 Gbps to 5.0 Gbps• Arria V—1.0 Gbps to 7.5 Gbps• Arria V GZ—2.0 Gbps to 9.9 Gbps• Arria 10—2.0 Gbps to 13.5 Gbps• Stratix V—2.0 Gbps to 12.5 Gbps

PCS Option • EnabledHard PCS

• Enabled SoftPCS

• EnabledPMA Direct

Select the PCS modes.

• Enabled Hard PCS—utilize Hard PCS components. Selectthis option to minimize resource utilization with data ratethat supports up to the limitation of the Hard PCS.

Note: For this setting, you will utilize 8G PCS modewith 20 bits PMA width and 32 bits PCS width.

• Enabled Soft PCS—utilize Soft PCS components. Select thisoption to allow higher supported data rate but increases theresource utilization. This option is applicable for all devicesexcept Cyclone V and Arria V GT/ST.

Note: For this setting, you will utilize 10G PCS modewith 40 bits PMA width and 40 bits PCS width.

• Enabled PMA Direct—NativePHY is set to PMA Directmode. Select this option to allow the highest supported datarate and to maximize the resource utilization. This option isapplicable only for Arria V GT/ST devices.

Note: For this setting, you will utilize PMA Directmode with 80 bits PMA width.

(13) The maximum data rate is limited by different device speed grade, transceiver PMA speed grade, andPCS options. Refer to Performance and Resource Utilization on page 2-6 for the maximum data ratesupport.

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PLL Type • CMU• ATX

Select the Phase-Locked Loop (PLL) types, depending on theFPGA device family. (14)

• Cylone V—CMU• Arria V—CMU• Stratix V—CMU, ATX

Bonding Mode • Bonded• Non-bonded

Select the bonding modes.

• Bonded—select this option to minimize inter-lanes skewfor the transmitter datapath.

• Non-bonded—select this option to disable inter-lanes skewcontrol for the transmitter datapath.

Note: The bonding type is automatically selected based onthe device family and number of lanes that you set.

PLL/CDR ReferenceClock Frequency

50.0–625.0 Set the transceiver reference clock frequency for PLL or CDR.

Enable Bit reversal andByte reversal

On, Off Turn on this option to set the data transmission order in MSB-first serialization. If this option is off, the data transmissionorder is in LSB-first serialization.

Enable TransceiverDynamic Reconfigura‐tion

On, Off Turn on this option to enable dynamic data rate change. Whenyou enable this option, you need to connect the reconfigura‐tion interface to the transceiver reconfiguration controller. (15)

For Arria 10 devices, turn on this option to enable theTransceiver Native PHY reconfiguration interface with "ShareReconfiguration Interface" enabled for multiple channels.

Enable Altera DebugMaster Endpoint (16)

On, Off Turn on this option for the Transceiver Native PHY IP core toinclude an embedded Altera Debug Master Endpoint (ADME).This ADME connects internally to the Avalon-MM slaveinterface of the Transceiver Native PHY and can access thereconfiguration space of the transceiver. It can perform certaintest and debug functions via JTAG using System Console.

This parameter is valid only for Arria 10 devices and when youturn on the Enable Transceiver Dynamic Reconfigurationparameter.

Enable CapabilityRegisters (16)

On, Off Turn on this option to enable capability registers, whichprovides high level information about the transceiver channel'sconfiguration.

(14) This parameter is not applicable to Arria 10 devices.(15) To perform dynamic reconfiguration, you have to instantiate the Transceiver Reconfiguration Controller

from the IP Catalog and connect it to the JESD204B IP core through the reconfig_to_xcvr andreconfig_from_xcvr interface.

(16) To support the Transceiver Toolkit in your design, you must turn on this option.


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Set user-defined IPidentifier

0–255 Set a user-defined numeric identifier that can be read from theuser identifer offset when you turn on the Enable CapabilityRegisters parameter.

Enable Control andStatus Registers (16)

On, Off Turn on this option to enable soft registers for reading statussignals and writing control signals on the PHY interfacethrough the embedded debug. Signals include rx_is_locktoref, rx_is_locktodata, tx_cal_busy, rx_cal_busy,rx_serial_loopback, set_rx_locktodata, set_rx_locktoref, tx_analogreset, tx_digitalreset, rx_analogreset, and rx_digitalrest. For more information,refer to the Arria 10 Transceiver User Guide.

Enable Prbs SoftAccumulators (16)

On, Off Turn on this option to set the soft logic to perform PRBS bitand error accumulation when using the hard PRBS generatorand checker.

JESD204B Configurations Tab

Lanes per converter device(L)

1–8 Set the number of lanes per converter device. (17)

Converters per device (M) 1–256 Set the number of converters per converter device.

Enable manual F configu‐ration

On, Off Turn on this option to set parameter F in manual modeand enable this parameter to be configurable. Otherwise,the parameter F is in derived mode.

You have to enable this parameter and configure theappropriate F value if the transport layer in your design issupporting Control Word (CF) and/or High Densityformat(HD).

Note: The auto derived F value using formulaF=M*S*N\'/(8*L) may not apply if parameterCF and/or parameter HD are enabled.

Octets per frame (F) 1, 2, 4–256 The number of octets per frame derived from the formulaof F= M*N'*S/(8*L).

Converter resolution (N) 1–32 Set the number of conversion bits per converter.

Transmitted bits persample (N')

1–32 Set the number of transmitted bits per sample (JESD204word size, which is in nibble group).

Note: If parameter CF equals to 0 (no control word),parameter N' must be larger than or equal tosum of parameter N and parameter CS (N' ≥ N+ CS). Otherwise, parameter N' must be largerthan or equal to parameter N (N'≥N).

(17) Refer to Performance and Resource Utilization on page 2-6 for the common supported range for L andthe resource utilization.

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Samples per converter perframe (S)

1–32 Set the number of transmitted samples per converter perframe.

Frames per multiframe(K)

1–32 Set the number of frames per multiframe. This value isdependent on the value of F and is derived using thefollowing constraints:

• The value of K must fall within the range of 17/F <= K<= min(32, floor (1024/F))

• The value of F*K must be divisible by 4

Enable scramble (SCR) On, Off Turn on this option to scramble the transmitted data ordescramble the receiving data.

Control Bits (CS) 0–3 Set the number of control bits per conversion sample.

Control Words (CF) 0–32 Set the number of control words per frame clock periodper link.

High density user dataformat (HD)

On, Off Turn on this option to set the data format. This parametercontrols whether a sample may be divided over morelanes.

• On: High Density format• Off: Data should not cross the lane boundary

Enable Error CodeCorrection (ECC_EN)

On, Off Turn on this option to enable error code correction (ECC)for memory blocks.

Phase adjustment request(PHADJ)

On, Off Turn on this option to specify the phase adjustmentrequest to the DAC.

• On: Request for phase adjustment• Off: No phase adjustment

This parameter is valid for Subclass 2 mode only.

Adjustment resolutionstep count (ADJCNT)

0–15 Set the adjustment resolution for the DAC LMFC.


Direction of adjustment(ADJDIR)

• Advance• Delay

Select to adjust the DAC LMFC direction.


Configurations and Status Registers Tab

Device ID 0–255 Set the device ID number.

Bank ID 0–15 Set the device bank ID number.

Lane# ID 0–31 Set the lane ID number.


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Lane# checksum 0–255 Set the checksum for each lane ID.

Related InformationPerformance and Resource Utilization on page 2-6

JESD204B IP Core Component FilesThe following table describes the generated files and other files that may be in your project directory. Thenames and types of generated files specified may vary depending on whether you create your design withVHDL or Verilog HDL.

Table 3-7: Generated Files

Extension Description

<variation name>.v or .vhd IP core variation file, which defines a VHDL or Verilog HDL description ofthe custom IP core. Instantiate the entity defined by this file inside of yourdesign. Include this file when compiling your design in the Quartus Primesoftware.

<variation name>.cmp A VHDL component declaration file for the IP core variation. Add thecontents of this file to any VHDL architecture that instantiates the IP core.

<variation name>.sdc Contains timing constraints for your IP core variation.

<variation name>.qip Contains Quartus Prime project information for your IP core variation.

<variation name>.tcl Tcl script file to run in Quartus Prime software.

<variation name>.sip Contains IP core library mapping information required by the QuartusPrime software.The Quartus Prime software generates a . sip file duringgeneration of some Altera IP cores. You must add any generated .sip file toyour project for use by NativeLink simulation and the Quartus PrimeArchiver.

<variation name>.spd Contains a list of required simulation files for your IP core.

JESD204B IP Core TestbenchThe JESD204B IP core includes a testbench to demonstrate a normal link-up sequence for the JESD204BIP core with a supported configuration. The testbench also provides an example of how to control theJESD204B IP core interfaces.

The testbench instantiates the JESD204B IP core in duplex mode and connects with the AlteraTransceiver PHY Reset Controller IP core. Some configurations are preset and are not programmable inthe JESD204B IP core testbench. For example, the JESD204B IP core always instantiates in duplex modeeven if RX or TX mode is selected in the JESD204B parameter editor.

Note: Dynamic reconfiguration is not supported in this JESD204B IP core testbench.

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Table 3-8: Preset Configurations for JESD204B IP Core Testbench

Configuration Preset Value

JESD204B Wrapper Base and PHY (MAC and PHY)Data Path DuplexPLL/CDR Reference ClockFrequency

• Data_rate/20 (if you turn on Enabled Hard PCS)• Data_rate/40 (if you turn on Enabled Soft PCS)

Link Clock • Data rate/40• Data rate/80 (if you turn on Enabled PMA Direct)

AVS Clock 125 MHz

Figure 3-5: JESD204B IP Core Testbench Block Diagram

The external ATX PLL is present only in the JESD204B IP core testbench targeting an Arria 10 FPGAdevice family.

Reference ClockGenerator

Link ClockGenerator

AVS ClockGenerator

PacketGenerator

PacketChecker

ATX PLL

Transceiver PHY Reset ControllerIP Core

JESD204BIP Core

(Duplex)Loopback

JESD204B Testbench

Related InformationGenerating and Simulating the IP Core Testbench on page 3-8

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Testbench Simulation FlowThe JESD204B testbench simulation flow:

1. At the start, the system is under reset (all the components are in reset).2. After 100 ns, the Transceiver Reset Controller IP core power up and wait for the tx_ready signal from

the Transceiver Reset Controller IP to assert.3. The reset signal of the JESD204B TX Avalon-MM interface is released (go HIGH) once the tx_ready

signal is asserted. At the next positive edge of the link_clk signal, the JESD204B TX link powers up byreleasing its reset signal.

4. The JESD204B TX link starts transmitting K28.5 characters and wait for the Transceiver ResetController IP core to assert the rx_ready signal.

5. The reset signal of the JESD204B RX Avalon-MM interface is released (go HIGH) once the rx_readysignal is asserted. At the next positive edge of the link_clk signal, the JESD204B RX link powers up byreleasing its reset signal.

6. Once the link is out of reset, a SYSREF pulse is generated to reset the LMFC counter inside both theJESD204B TX and RX IP core.

7. When the txlink_ready signal is asserted, the packet generator starts sending packets to the TXdatapath.

8. The packet checker starts comparing the packet sent from the TX datapath and received at the RXdatapath after the rxlink_valid signal is asserted.

9. The testbench reports a pass or fail when all the packets are received and compared.

The testbench concludes by checking that all the packets have been received.

If no error is detected, the testbench issues a TESTBENCH PASSED message stating that the simulationwas successful. If an error is detected, the testbench issues a TESTBENCH FAILED message to indicatethat the testbench has failed.

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JESD204B IP Core Functional Description 42015.11.02


The JESD204B IP core implements a transmitter (TX) and receiver (RX) block. Each block has two layersand consists of the following components:

• Media access control (MAC)—DLL block that consists of the link layer (link state machine andcharacter replacement), CSR, Subclass 1 and 2 deterministic latency, scrambler or descrambler, andmultiframe counter.

• Physical layer (PHY)—PCS and PMA block that consists of the 8B/10B encoder, word aligner,serializer, and deserializer.

You can specify the datapath and wrapper for your design and generate them separately.

The TX and RX blocks in the DLL utilizes the Avalon-ST interface to transmit or receive data and theAvalon-MM interface to access the CSRs. The TX and RX blocks operate on 32-bit data width perchannel, where the frame assembly packs the data into four octets per channel. Multiple TX and RXblocks can share the clock and reset if the link rates are the same.





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Figure 4-1: Overview of the JESD204B IP Core Block Diagram

RX Driver

TX Driver

Deserializer

SerializerFrame/Lane

AlignmentCharacter

Generation

Descrambler

ScramblerData Frame Assembly

Data Frame Deassembly

SYSREF

Frame Clock

ADC ApplicationLayer

DAC ApplicationLayer

Transport Layer Data Link Layer Physical Layer

Word Aligner

Soft Logic Hard Logic

JESD204B IP CoreJESD204BDesign Example

jesd204_tx_topMAC (jesd204_tx_base)

MAC (jesd204_rx_base) PHY (jesd204_rx_phy)

PHY (jesd204_tx_phy)

jesd204_rx_top

8B/10BEncoder

8B/10BDecoder

SYNC~

SYNC~

Frame/LaneAlignment

Character Buffer/Replace/Monitor

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Altera Corporation JESD204B IP Core Functional Description

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Figure 4-2: JESD204B IP Core TX and RX Datapath Block Diagram

The JESD204B IP core utilizes the Avalon-ST source and sink interfaces, with unidirectional flow of data,to transmit and receive data on the FPGA fabric interface.

TX FrameAssembly

Per Device

TX CSRPer Device

TX CTLPer Device

Scrambler Data LinkLayer (TX)

SoftPCS(TX)

Hard PCSand

TransceiverJESD204B(TX) Per Device

CSR

CSR

CSR

32 Bit PCSPer Channel

Transceiver (Duplex)Per Device

SYNC_NSYSREFTX_INTTXLINK_CLKTXFRAME_CLK

Avalon-MM

Avalon-ST

To AvalonInterface

Bus

RX FrameDeassemblyPer Device

RX CSRPer Device

RX CTLPer Device

Descrambler Data LinkLayer (RX)

SoftPCS(RX)

Hard PCSand

TransceiverJESD204B(RX) Per Device

CSR

CSR

CSR CSR

CSR


32/40/80PCS

SYNC_NSYSREFRX_INTRXLINK_CLKRXFRAME_CLK

Avalon-MM

Avalon-ST

To AvalonInterface

Bus

JESD204B TX and RX Transport Layer with Base and Transceiver (Design Example)

Avalon-ST32 Bits per Channel Serial Interface

(TX_n, TX_p)


(RX_n, RX_p)

32-Bits Architecture

The JESD204B IP core consist of 32-bit internal datapath per lane. This means that JESD204B IP Coreexpects the data samples to be assembled into 32-bit data (4 octets) per lane in the transport layer beforesending the data to the Avalon-ST data bus. The JESD204 IP core operates in the link clock domain. Thelink clock runs at (data rate/40) because it is operating in 32-bit data bus after 8B/10B encoding.

As the internal datapath of the core is 32-bits, the (F × K) value must be in the order of 4 to align themulti-frame length on a 32-bit boundary. Apart from this, the deterministic latency counter values suchas LMFC counter, RBD counter, and Subclass 2 adjustment counter will be in link clock count instead offrame clock count.

Avalon-ST Interface

The JESD204 IP core and transport layer in the design example use the Avalon-ST source and sinkinterfaces. There is no backpressure mechanism implemented in this core. The JESD204B IP core expectscontinuous stream of data samples from the upstream device.

UG-011422015.11.02 JESD204B IP Core Functional Description 4-3

JESD204B IP Core Functional Description Altera Corporation

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Avalon-MM Interface

The Avalon-MM slave interface provides access to internal CSRs. The read and write data width is 32-bits(DWORD access). The Avalon-MM slave is asynchronous to the txlink_clk, txframe_clk, rxlink_clk,and rxframe_clk clock domains. You are recommended to release the reset for the CSR configurationspace first. All run-time JESD204B configurations like L, F, M, N, N', CS, CF, and HD should be set beforereleasing the reset for link and frame clock domain.

Each write transfer has a writeWaitTime of 0 cycle while a read transfer has a readWaitTime of 1 cycle andreadLatency of 1 cycle.

Related InformationAvalon Interface SpecificationMore information about the Avalon-ST and Avalon-MM interfaces, including timing diagrams.

TransmitterThe transmitter block, which interfaces to DAC devices, takes one of more digital sample streams andconverts them into one or more serial streams.

The transmitter performs the following functions:

• Data scrambling• Frame or lane alignment• Character generation• Serial lane monitoring• 8B/10B encoding• Data serializer

Figure 4-3: Transmitter Data Path Block Diagram

TX FrameDeassemblyPer Device

TX CSRPer Device

TX CTLPer Device

Scrambler Data LinkLayer (TX)

SoftPCS(TX)

Hard PCSand

TransceiverJESD204B(TX) Per Device

CSR

CSR

CSR


Transceiver (TX)Per Device

SYNC_NSYSREFTX_INTTXLINK_CLKTXFRAME_CLK

Avalon-MM

Avalon-ST

To AvalonInterface

Bus

JESD204 TX Transport Layer withBase and Transceiver Design Example


(TX_n, TX_p)

The transmitter block consists of the following modules:

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http://www.altera.com/literature/manual/mnl_avalon_spec.pdf


• TX CSR—manages the configuration and status registers.• TX_CTL—manages the SYNC_N signal, state machine that controls the data link layer states, LMFC,

and also the deterministic latency throughout the link.• TX Scrambler and Data Link Layer—takes in 32-bits of data that implements the Initial Lane

Alignment Sequence (ILAS), performs scrambling, lane insertion and frame alignment of characters.

TX Data Link LayerThe JESD204B IP core TX data link layer includes three phases to establish a synchronized link—CodeGroup Synchronization (CGS), Initial Lane Synchronization (ILAS), and User Data phase.

TX CGS

The CGS phase is achieved through the following process:

• Upon reset, the converter device (RX) issues a synchronization request by driving SYNC_N low. TheJESD204 TX IP core transmits a stream of /K/ = /K28.5/ symbols. The receiver synchronizes when itreceives four consecutive /K/ symbols.

• For Subclass 0, the RX converter devices deassert SYNC_N signal at the frame boundary. After allreceivers have deactivated their synchronization requests, the JESD204 TX IP core continues toemit /K/ symbols until the start of the next frame. The core proceeds to transmit ILAS data sequenceor encoded user data if csr_lane_sync_en signal is disabled.

• For Subclass 1 and 2, the RX converter devices deassert SYNC_N signal at the LMFC boundary. After allreceivers deactivate the SYNC_N signal, the JESD204 TX IP core continues to transmit /K/ symbols untilthe next LMFC boundary. At the next LMFC boundary, the JESD204B IP core transmits ILAS datasequence. (There is no programmability to use a later LMFC boundary.)

TX ILAS

When lane alignment sequence is enabled through the csr_lane_sync_en register, the ILAS sequence istransmitted after the CGS phase. The ILAS phase takes up four multi-frames. For Subclass 0 mode, youcan program the CSR (csr_ilas_multiframe) to extend the ILAS phase to a maximum of 256 multi-frames before transitioning to the encoded user data phase. The ILAS data is not scrambled regardless ofwhether scrambling is enabled or disabled.

The multi-frame has the following structure:

• Each multi-frame starts with a /R/ character (K28.0) and ends with a /A/ character (K28.3)• The second multi-frame transmits the ILAS configuration data. The multi-frame starts with /R/

character (K28.0), followed by /Q/ character (K28.4), and then followed by the link configuration data,which consists of 14 octets as illustrated in the table below. It is then padded with dummy data andends with /A/ character (K28.3), marking the end of multi-frame.

• Dummy octets are an 8-bit counter and is always reset when it is not in ILAS phase.• For a configuration of more than four multi-frames, the multi-frame follows the same rule above and

is padded with dummy data in between /R/ character and /A/ character.

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Table 4-1: Link Configuration Data Transmitted in ILAS Phase

Configura‐tion Octet

BitsDescription

MSB 6 5 4 3 2 1 LSB

0 DID[7:0] DID = Device ID

1 ADJCNT[3:0] BID[3:0] ADJCNT = Number of adjustmentresolution steps (18)

BID = Bank ID

2 0 ADJDIR

PHADJ

LID[4:0] ADJDIR = Direction to adjust DACLMFC (18)

PHADJ = Phase adjustmentrequest (18)

LID = Lane ID

3 SCR 0 0 L[4:0] SCR = Scrambling enabled/disabled

L = Number of lanes per device(link)

4 F[7:0] F = Number of octets per frame perlane

5 0 0 0 K[4:0] K = Number of frames per multi-frame

6 M[7:0] M = Number of converters perdevice

7 CS[1:0] 0 N[4:0] CS = Number of control bits persample

N = Converter resolution

8 SUBCLASSV[2:0] N_PRIME[4:0] SUBCLASSV = Subclass version

N_PRIME = Total bits per sample

9 JESDV[2:0] S[4:0] JESDV = JESD204 version

S = Number of samples perconverter per frame

10 HD 0 0 CF[4:0] HD = High Density data format

CF = Number of control words perframe clock per link

(18) Applies to Subclass 2 only.

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Configura‐tion Octet

BitsDescription

MSB 6 5 4 3 2 1 LSB

11 RES1[7:0] RES1 = Reserved. Set to 8'h00

12 RES2[7:0] RES2 = Reserved. Set to 8'h00

13 FCHK[7:0]; automatically calculated using run-timeconfiguration.

FCHK is the modulus 256 of thesum of the 13 configuration octetsabove.

If you change any of the octetsduring run-time, make sure toupdate the new FCHK value in theregister.

The JESD204 TX IP core also supports debug feature to continuously stay in ILAS phase without exiting.You can enable this feature by setting the bit in csr_ilas_loop register. There are two modes of entry:

• RX asserts SYNC_N and deasserts it after CGS phase. This activity triggers the ILAS phase and the CSRwill stay in ILAS phase indefinitely until this setting changes.

• Link reinitialization through CSR is initiated. The JESD204B IP core transmits /K/ character andcauses the RX converter to enter CGS phase. After RX deasserts SYNC_N, the CSR enters ILAS phaseand will stay in that phase indefinitely until this setting changes.

In ILAS loop, the multi-frame transmission is the same where /R/ character (K28.0) marks the start ofmulti-frame and /A/ character (K28.3) marks the end of multi-frame, with dummy data in between. Thedummy data is an increment of Dx.y.

User Data PhaseDuring the user data phase, character replacement at the end of frame and end of multi-frame isopportunistically inserted so that there is no additional overhead for data bandwidth.

Character replacement for non-scrambled data

The character replacement for non-scrambled mode in the IP core follows these JESD204B specificationrules:

• At end of frame (not coinciding with end of multi-frame), which equals the last octet in the previousframe, the transmitter replaces the octet with /F/ character (K28.7). However, if an alignment characterwas transmitted in the previous frame, the original octet will be encoded.

• At the end of a multi-frame, which equals to the last octet in the previous frame, the transmitterreplaces the octet with /A/ character (K28.3), even if a control character was already transmitted in theprevious frame.

For devices that do not support lane synchronization, only /F/ character replacement is done. At everyend of frame, regardless of whether the end of multi-frame equals to the last octet in previous frame, thetransmitter encodes the octet as /F/ character (K28.7) if it fits the rules above.

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Character replacement for scrambled data

The character replacement for scrambled data in the IP core follows these JESD204B specification rules:

• At end of frame (not coinciding with end of multi-frame), which equals to 0xFC (D28.7), thetransmitter encodes the octet as /F/ character (K28.7).

• At end of multi-frame, which equals to 0x7C, the transmitter replaces the current last octet as /A/character (K28.3).

For devices that do not support lane synchronization, only /F/ character replacement is done. At everyend of frame, regardless of whether the end of multi-frame equals to 0xFC (D28.7), the transmitterencodes the octet as /F/ character (K28.7) if it fits the rules above.

TX PHY Layer

The 8B/10B encoder encodes the data before transmitting them through the serial line. The 8B/10Bencoding has sufficient bit transition density (3-8 transitions per 10-bit symbol) to allow clock recovery bythe receiver. The control characters in this scheme allow the receiver to:

• synchronize to 10-bit boundary.• insert special character to mark the start and end of frames and start and end of multi-frames.• detect single bit errors.

The JESD204 IP core supports transmission order from MSB first as well as LSB first. For MSB firsttransmission, the serialization of the left-most bit of 8B/10B code group (bit "a") is transmitted first.

ReceiverThe receiver block, which interfaces to ADC devices, receives the serial streams from one or more TXblocks and converts the streams into one or more sample streams.

The receiver performs the following functions:

• Data deserializer• 8B/10B decoding• Lane alignment• Character replacement• Data descrambling

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Figure 4-4: Receiver Data Path Block Diagram

Transceiver (RX)Per Device

RX FrameDeassemblyPer Device

RX CSRPer Device

RX CTLPer Device

Descrambler Data LinkLayer (RX)

SoftPCS(RX)

Hard PCSand

TransceiverJESD204B(RX) Per Device

CSR

CSR

CSR


32/40/80PCS

SYNC_NSYSREFRX_INTRXLINK_CLKRXFRAME_CLK

Avalon-MM

Avalon-ST

To AvalonInterface

Bus

JESD204 RX Transport Layer withBase and Transceiver Design Example


(RX_n, RX_p)

The receiver block includes the following modules:

• RX CSR—manages the configuration and status registers.• RX_CTL—manages the SYNC_N signal, state machine that controls the data link layer states, LMFC,

and also the buffer release, which is crucial for deterministic latency throughout the link.• RX Scrambler and Data Link Layer—takes in 32-bits of data that decodes the ILAS, performs descram‐

bling, character replacement as per the JESD204B specification, and error detection (code group error,frame and lane realignment error).

RX Data Link LayerThe JESD204B IP core RX data link layer buffers incoming user data on all lanes until the RX elasticbuffers can be released. Special character substitution are done in the TX link so that the RX link canexecute frame and lane alignment monitoring based on the JESD204B specification.

RX CGSThe CGS phase is the link up phase that monitors the detection of /K28.5/ character.

The CGS phase is achieved through the following process:

• Once the word boundary is aligned, the RX PHY layer detects the /K28.5/ 20-bit boundary andindicate that the character is valid.

• The receiver deasserts SYNC_N on the next frame boundary (for Subclass 0) or on the next LMFCboundary (for Subclass 1 and 2) after the reception of four successive /K/ characters.

• After correct reception of another four 8B/10B characters, the receiver assumes full code groupsynchronization. Error detected in this state machine is the code group error. Code group error alwaystrigger link reinitialization through the assertion of SYNC_N signal and this cannot be disabled throughthe CSR. The CS state machine is defined as CS_INIT, CS_CHECK, and CS_DATA.

• The minimum duration for a synchronization request on the SYNC_N is five frames plus nine octets.

Frame Synchronization

After CGS phase, the receiver assumes that the first non-/K28.5/ character marks the start of frame andmulti-frame. If the transmitter emits an initial lane alignment sequence, the first non-/K28.5/ character

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will be /K28.0/. Similar to the JESD204 TX IP core, the csr_lane_sync_en is set to 1 by default, thus theRX core detects the /K/ character to /R/ character transition. If the csr_lane_sync_en is set to 0, the RXcore detects the /K/ character to the first data transition. An ILAS error and unexpected /K/ character isflagged if either one of these conditions are violated.

When csr_lane_sync_en is set to 0, you have to disable data checking for the first 16 octets of data as thecharacter replacement block takes 16 octets to recover the end-of-frame pointer for character replace‐ment. When csr_lane_sync_en is set to 1 (default JESD204B setting), the number of octets to bediscarded depends on the scrambler or descrambler block.

The receiver assumes that a new frame starts in every F octets. The octet counter is used for framealignment and lane alignment.

Related Information

• Scrambler/Descrambler on page 4-14

Frame Alignment

The frame alignment is monitored through the alignment character /F/. The transmitter inserts thischaracter at the end of frame. The /A/ character indicates the end of multi-frame. The character replace‐ment algorithm depends on whether scrambling is enabled or disabled, regardless of thecsr_lane_sync_en register setting.

The alignment detection process:

• If two successive valid alignment characters are detected in the same position other than the assumedend of frame—without receiving a valid or invalid alignment character at the expected positionbetween two alignment characters—the receiver realigns its frame to the new position of the receivedalignment characters.

• If lane realignment can result in frame alignment error, the receiver issues an error.

In the JESD204 RX IP core, the same flexible buffer is used for frame and lane alignment. Lane realign‐ment gives a correct frame alignment because lane alignment character doubles as a frame alignmentcharacter. A frame realignment can cause an incorrect lane alignment or link latency. The course of actionis for the RX to request for reinitialization through SYNC_N. (19)

Lane Alignment

After the frame synchronization phase has entered FS_DATA, the lane alignment is monitored via /A/character (/K28.3/) at the end of multi-frame. The first /A/ detection in the ILAS phase is important forthe RX core to determine the minimum RX buffer release for inter-lane alignment. There are two types oferror that is detected in lane alignment phase:

• Arrival of /A/ character from multiple lanes exceed one multi-frame.• Misalignment detected during user data phase.

(19) Dynamic frame realignment and correction is not supported.

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The realignment rules for lane alignment are similar to frame alignment:

• If two successive and valid /A/ characters are detected at the same position other than the assumed endof multi-frame—without receiving a valid/invalid /A/ character at the expected position betweentwo /A/ characters—the receiver aligns the lane to the position of the newly received /A/ characters.

• If a recent frame alignment causes the loss of lane alignment, the receiver realigns the lane frame—which is already at the position of the first received /A/ character—at the unexpected position.

ILAS Data

The JESD204 RX IP core captures 14 octets of link configuration data that are transmitted on the 2nd

multi-frame of the ILAS phase. The receiver waits for the reception of /Q/ character that marks the start oflink configuration data and then latch it into ILAS octets, which are per lane basis. You can read the 14octets captured in the link configuration data through the CSR. You need to first set thecsr_ilas_data_sel register to select which link configuration data lane it is trying to read from. Then,proceed to read from the csr_ilas_octet register.

Initial Lane Synchronization

The receivers in Subclass 1 and Subclass 2 modes store data in a memory buffer (Subclass 0 mode does notstore data in the buffer but immediately releases them on the frame boundary as soon as the latest lanearrives.). The RX IP core detects the start of multi-frame of user data per lane and then wait for the latestlane data to arrive. The latest data is reported as RBD count (csr_rbd_count) value which you can readfrom the status register. This is the earliest release opportunity of the data from the deskew FIFO (referredto as RBD offset).

The JESD204 RX IP core supports RBD release at 0 offset and also provides programmable offset throughRBD count. By default, the RBD release can be programmed through the csr_rbd_offset to release atthe LMFC boundary. If you want to implement an early release mechanism, program it in thecsr_rbd_offset register. The csr_rbd_offset and csr_rbd_count is a counter based on the link clockboundary (not frame clock boundary). Therefore, the RBD release opportunity is at every four octets.

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Figure 4-5: Subclass 1 Deterministic Latency and Support for Programmable Release Opportunity

K K K K K K K K K K K K K K K K K K K K K K K K K KR D D D D A R Q C C D D D AL Transmit Lanes

SYSREF

SYNC_N

LMFC

Deterministic Delay from SYSREF Sampled High to LMFC Zero-Crossing

TX ILA Begins on First LMFC Zero-Crossing after SYNC_N Is Deasserted

Multi-Frame

TXDevice

K K K K K K K K K K K K K R D D D D A R Q C C D D D A R D DEarliest Arrival Lane

SYSREF

SYNC_N

LMFC

Deterministic Delay fromSYSREF Sampled Highto LMFC Zero-Crossing

RX Elastic Buffers Released

RXDevice

K K

K K K K K K K K K K K K K R D D D D A R Q C C D D D A R D DK K

K K K K K K K K K K K K K R D D D D A R Q C C D D D A R D DK K

K K K K K K K K K K K KK K K K

K K K K K K K KK K K K

K KK K K K K K K K K K KK KK K K

Latest Arrival Lane

Aligned Output on All Lanes

RX Elastic BufferRelease Opportunity

RBD FrameCycles

SYNC_N Deasserted Directly after LMFC Zero Crossing

RBD FrameCycles

RBD FrameCycles

RBD FrameCycles

2 Character Elastic Buffer Delay for Latest Arrival6 Character Elastic Buffer Delay for Latest Arrival

Deterministic Delayfrom TX ILA Output

to RX ILA Output

RX PHY Layer

The word aligner block identifies the MSB and LSB boundaries of the 10-bit character from the serial bitstream. Manual alignment is set because the /K/ character must be detected in either LSB first or MSB firstmode. When the programmed word alignment pattern is detected in the current word boundary, the PCSindicates a valid pattern in the rx_sync_status (mapped as pcs_valid to the IP core). The codesynchronization state is detected after the detection of the /K/ character boundary for all lanes.

In a normal operation, whenever synchronization is lost, JESD204 RX IP core always return back to theCS_INIT state where the word alignment is initiated. For debug purposes, you can bypass this alignmentby setting the csr_patternalign_en register to 0.

The 8B/10B decoder decode the data after receiving the data through the serial line. The JESD204 IP coresupports transmission order from MSB first as well as LSB first.

The PHY layer can detect 8B/10B not-in-table (NIT) error and also running disparity error.

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Operation

Operating ModesThe JESD204B IP core supports Subclass 0, 1, and 2 operating modes.

Subclass 0

The JESD204 IP core maintains a LMFC counter that counts from 0 to (F × K/4)–1 and wraps aroundagain. The LMFC counter starts counting at the deassertion of SYNC_N signal from multiple DACs aftersynchronization. This is to align the LMFC counter upon transmission and can only be done after all theconverter devices have deasserted its synchronization request signal.

Subclass 1

The JESD204 IP core maintains a LMFC counter that counts from 0 to (F × K/4)–1 and wraps aroundagain. The LMFC counter will reset within two link clock cycles after converter devices issue a commonSYSREF frequency to all the transmitters and receivers. The SYSREF frequency must be the same forconverter devices that are grouped and synchronized together.

Table 4-2: Example of SYSREF Frequency Calculation

In this example, you can choose to perform one of the following options:

• provide two SYSREF and device clock, where the ADC groups share both the device clock and SYSREF (18.75MHz and 9.375 MHz)

• provide one SYSREF (running at 9.375 MHz) and device clock for all the ADC and DAC groups because theSYSREF period in the DAC is a multiplication of n integer.

Group Configuration SYSREF Frequency

ADC Group 1 (2 ADCs) • LMF = 222• K = 16• Data rate = 6 Gbps

(6 GHz / 40) / (2 x 16 / 4) = 18.75 MHz

ADC Group 2 (2 ADCs) • LMF = 811• K = 32• Data rate = 6 Gbps

(6 GHz / 40) / (1 x 32 / 4) = 18.75 MHz

DAC Group 3 (2 DACs) • LMF = 222• K = 16• Data rate = 3 Gbps

(3 GHz / 40) / (2 x 16 / 4) = 9.375 MHz

Subclass 2

The JESD204 IP core maintains a LMFC counter that counts from 0 to (F × K/4)–1 and wraps aroundagain. The LMFC count starts upon reset and the logic device always acts as the timing master. Theconverters adjust their own internal LMFC to match the master's counter. The alignment of LMFC withinthe system relies on the correct alignment of SYNC_N signal deassertion at the LMFC boundary.

The alignment of LMFC to RX logic is handled within the TX converter. The RX logic releases SYNC_N atthe LMFC tick and the TX converter adjust its internal LMFC to match the RX LMFC.

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For the alignment of LMFC to the TX logic, the JESD204 TX IP core samples SYNC_N from the DACreceiver and reports the relative phase difference between the DAC and TX logic device LMFC in the TXCSR (dbg_phadj, dbg_adjdir, and dbg_adjcnt). Based on the reported value, you can calculate theadjustment required. Then, to initiate the link reinitialization through the CSR, set the value in the TXCSR (csr_phadj, csr_adjdir, and csr_adjcnt). The values on the phase adjustment are embedded inbytes 1 and 2 of the ILAS sequence that is sent to the DAC during link initialization. On the reception ofthe ILAS, the DAC adjusts its LMFC phase by step count value and sends back an error report with thenew LMFC phase information. This process may be repeated until the LMFC at the DAC and the logicdevice are aligned.

Scrambler/DescramblerBoth the scrambler and descrambler are designed in a 32-bit parallel implementation and the scrambling/descrambling order starts from first octet with MSB first.

The JESD204 TX and RX IP core support scrambling by implementing a 32-bit parallel scrambler in eachlane. The scrambler and descrambler are located in the JESD204 IP MAC interfacing to the Avalon-STinterface. You can enable or disable scrambling and this option applies to all lanes. Mixed modeoperation, where scrambling is enabled for some lanes, is not permitted.

The scrambling polynomial:

1 + x14 + x15

The descrambler can self-synchronize in eight octets. In a typical application where the reset value of thescrambler seed is different from the converter device to FPGA logic device, the correct user data isrecovered in the receiver in two link clocks (due to the 32-bit architecture). The PRBS pattern checker onthe transport layer should always disable checking of the first eight octets from the JESD204 RX IP core.

SYNC_N SignalFor Subclass 0 implementation, the SYNC_N signal from the DAC converters in the same group path mustbe combined.

In some applications, multiple converters are grouped together in the same group path to sample a signal(referred as multipoint link). The FPGA can only start the LMFC counter and its transition to ILAS afterall the links deassert the synchronization request. The JESD204B TX IP core provides three signals tofacilitate this application. The SYNC_N is the direct signal from the DAC converters. The error signalingfrom SYNC_N is filtered and sent out as dev_sync_n signal. For Subclass 0, you need to multiplex all thedev_sync_n signals in the same multipoint link and then input them to the IP core through mdev_sync_nsignal.

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Figure 4-6: Subclass 0 — Combining the SYNC_N Signal for JESD204B TX IP Core

SYSREF Tied to0 for Subclass 0

JESD204B IP CoreTX

SYSREF SYNC_NDEV_SYNC_N

MDEV_SYNC_N


MDEV_SYNC_N


MDEV_SYNC_N

FPGA Device

Converter Device 0

L

Converter Device 1

L

Converter Device 2

L

SYNC_N

SYNC_N

SYNC_N

Clock ChipFPGA Reference Clock SYNC* (1)

DAC ReferenceClock

Note:1. SYNC* is not associated to SYNC_N in the JESD204B specification. SYNC* refers to JESD204A (Subclass 0) converter devices that may support synchronization via additional SYNC signalling.

JESD204B IP CoreTX

JESD204B IP CoreTX

For Subclass 1 implementation, you may choose to combine or not to combine the SYNC_N signal from theconverter device. If you implement two ADC converter devices as a multipoint link and one of theconverter is unable to link up, the functional link will still operate. You must manage the trace length forthe SYSREF signal and also the differential pair to minimize skew.

The SYNC_N is the direct signal from the DAC converters. The error signaling from SYNC_N is filtered andsent out as dev_sync_n output signal. The dev_sync_n signal from the JESD204B TX IP core mustloopback into the mdev_sync_n signal of the same instance without combining the SYNC_N signal.

Apart from that, you must set the same RBD offset value (csr_rbd_offset) to all the JESD204B RX IPcores within the same multipoint link for the RBD release (the latest lane arrival for each of the links). TheJESD204 RX IP core will deskew and output the data when the RBD offset value is met. The total latencyis consistent in the system and is also the same across multiple resets. Setting a different RBD offset toeach link or setting an early release does not guarantee deterministic latency and data alignment.

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Figure 4-7: Subclass 1 — Combining the SYNC_N Signal for JESD204B TX IP Core

SYSREF (Subclass 1)

SYSREF

SYNC_NDEV_SYNC_N

MDEV_SYNC_N

SYSREF

SYNC_NDEV_SYNC_N

MDEV_SYNC_N

SYSREF

SYNC_NDEV_SYNC_N

MDEV_SYNC_N

FPGA Device

Converter Device 0

L

Converter Device 1

L

Converter Device 2

L

SYNC_N

SYNC_N

SYNC_N

Clock Chipand SYSREF

FPGA Reference Clock

SYSREF

DAC ReferenceClock

SYSREF

JESD204B IP CoreTX

JESD204B IP CoreTX

JESD204B IP CoreTX

Related InformationProgrammable RBD Offset on page 6-2

Link ReinitializationThe JESD204B TX and RX IP core support link reinitialization.

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There are two modes of entry for link reinitialization:

• Hardware initiated link reinitialization:

• For TX, the reception of SYNC_N for more than five frames and nine octets triggers link reinitializa‐tion.

• For RX, the loss of code group synchronization, frame alignment and lane alignment errors causethe IP core to assert SYNC_N and request for link reinitialization.

• Software initiated link reinitialization—both the TX and RX IP core allow software to request for linkreinitialization.

• For TX, the IP core transmits /K/ character and wait for the receiver to assert SYNC_N to indicatethat it has entered CS_INIT state.

• For RX, the IP core asserts SYNC_N to request for link reinitialization.

Hardware initiated link reinitialization can be globally disabled through the csr_link_reinit_disableregister for debug purposes.

Hardware initiated link reinitialization can be issued as interrupt depending on the error type andinterrupt error enable. If lane misalignment has been detected as a result of a phase change in local timingreference, the software can rely on this interrupt trigger to initiates a LMFC realignment. The realignmentprocess occurs by first resampling SYSREF and then issuing a link reinitialization request.

Link Startup SequenceSet the run-time LMF configuration when the txlink_rst_n or rxlink_rst_n signals are asserted. Upontxlink_rst_n or rxlink_rst_n deassertion, the JESD204B IP core begins operation. The followingsections describe the detailed operation for each subclass mode.

TX (Subclass 0)

Upon reset deassertion, the JESD204B TX IP core is in CGS phase. SYNC_N deassertion from the converterdevice enables the JESD204B TX IP core to exit CGS phase and enter ILAS phase (if csr_lane_sync_en =1) or User Data phase (if csr_lane_sync_en = 0).

TX (Subclass 1)

Upon reset deassertion, the JESD204B TX IP core is in CGS phase. SYNC_N deassertion from the converterdevice enables the JESD204B TX IP core to exit CGS phase. The IP core ensures that at least one SYSREFrising edge is sampled before exiting CGS phase and entering ILAS phase. This is to prevent a racecondition where the SYNC_N is deasserted before SYSREF is sampled. SYSREF sampling is crucial to ensuredeterministic latency in the JESD204B Subclass 1 system.

TX (Subclass 2)

Similar to Subclass 1 mode, the JESD204B TX IP core is in CGS phase upon reset deassertion. The LMFCalignment between the converter and IP core starts after SYNC_N deassertion. The JESD204B TX IP coredetects the deassertion of SYNC_N and compares the timing to its own LMFC. The required adjustment inthe link clock domain is updated in the register map. You need to update the final phase adjustment valuein the registers for it to transfer the value to the converter during the ILAS phase. The DAC adjusts theLMFC phase and acknowledge the phase change with an error report. This error report contains the newDAC LMFC phase information, which allows the loop to iterate until the phase between them is aligned.

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RX (Subclass 0)

The JESD204B RX IP core drives and holds SYNC_N (dev_sync_n signal) low when it is in reset. Uponreset deassertion, the JESD204B RX IP core checks if there is sufficient /K/ character to move its statemachine out of synchronization request. Once sufficient /K/ character is detected, the IP core deassertsSYNC_N.

RX (Subclass 1)

The JESD204B RX IP core drives and holds the SYNC_N (dev_sync_n signal) low when it is in reset. Uponreset deassertion, the JESD204B RX IP core checks if there is sufficient /K/ character to move its statemachine out of synchronization request. The IP core also ensures that at least one SYSREF rising edge issampled before deasserting SYNC_N. This is to prevent a race condition where the SYNC_N is deassertedbased on internal free-running LMFC count instead of the updated LMFC count after SYSREF is sampled.

RX (Subclass 2)

The JESD204B RX IP core behaves the same as in Subclass 1 mode. In this mode, the logic device is alwaysthe master timing reference. Upon SYNC_N deassertion, the ADC adjusts the LMFC timing to match the IPcore.

Error Reporting Through SYNC_N Signal

The JESD204 TX IP core can detect error reporting through SYNC_N when SYNC_N is asserted for twoframe clock periods (if F >= 2) or four frame clock periods (if F = 1). When the downstream devicereports an error through SYNC_N, the TX IP core issues an interrupt. The TX IP core samples the SYNC_Npulse width using the link clock.

For a special case of F = 1, two frame clock periods are less than one link clock. Therefore, the errorsignaling from the receiver may be lost. You must program the converter device to extend the SYNC_Npulse to four frame clocks when F = 1.

The JESD204 RX IP core does not report an error through SYNC_N signaling. Instead, the RX IP coreissues an interrupt when any error is detected.

You can check the csr_tx_err, csr_rx_err0, and csr_rx_err1 register status to determine the errortypes.

Clocking SchemeThis section describes the clocking scheme for the JESD204B IP core and transceiver.

Table 4-3: JESD204B IP Core Clocks

Clock Signal Formula Description

TX/RX Device Clock:

pll_ref_clk

PLL selection during IPcore generation

The PLL reference clock used by the TX TransceiverPLL or RX CDR.

This is also the recommended reference clock to theAltera PLL IP Core (for Arria V or Stratix Vdevices) or Altera IOPLL (for Arria10 devices).

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TX/RX Link Clock:

txlink_clk

rxlink_clk

Data rate/40 The timing reference for the JESD204B IP core.Thelink clock runs at data rate/40 because the IP core isoperating in a 32-bit data bus architecture after 8B/10B encoding.

The JESD204B transport layer in the designexample requires both the link clock and frameclock to be synchronous.

TX/RX Frame Clock(in design example):

txframe_clk

rxframe_clk

Data rate/(10 × F) The frame clock as per the JESD204B specification.This clock is applicable to the JESD204B transportlayer and other upstream devices that run in frameclock such as the PRBS generator/checker or anydata processing blocks that run at the same rate asthe frame clock.

The JESD204B transport layer in the designexample also supports running the frame clock inhalf rate or quarter rate by using the FRAMECLK_DIV parameter. The JESD204B transport layerrequires both the link clock and frame clock to besynchronous. For more information, refer to the F1/F2_FRAMECLK_DIV parameter description andits relationship to the frame clock.

TX/RX TransceiverSerial Clock andParallel Clock

Internally derived fromthe data rate during IPcore generation

The serial clock is the bit clock to stream outserialized data. The transceiver PLL supplies thisclock and is internal to the transceiver.

The parallel clock is for the transmitter PMA andPCS within the PHY. This clock is internal to thetransceiver and is not exposed in the JESD204B IPcore.

For Arria V and Stratix V devices, these clocks areinternally generated as the transceiver PLL isencapsulated within the JESD204B IP core's PHY.

For Arria 10 devices, you need to generate thetransceiver PLL based on the data rate and connectthe serial and parallel clock. These clocks arereferred to as *serial_clk and *bonding_clock inArria 10 devices. Refer to the Arria10 TransceiverPHY IP Core User Guide for more information.

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TX/RX PHY Clock:

txphy_clk

rxphy_clk

Data rate/40 (for alldevices exceptArria V GT/ST in PMADirect mode)

Data rate/80 (forArria V GT/ST devices inPMA Direct mode)

The PHY clock generated from the transceiverparallel clock for the TX path or the recovered clockgenerated from the CDR for the RX path.

There is limited use for this clock. Avoid using thisclock when PMA Direct mode is selected. Use thisclock only if the JESD204B configuration is F=4 andthe core is operating at Subclass 0 mode. This clockcan be used as input for both the txlink_clk andtxframe_clk, or rxlink_clk and rxframe_clk.

When you set the PCS option to enable Hard PCSor Soft PCS mode, the txphy_clk connects to thetransceiver tx_std_clkout signal and the rxphy_clk connects to the rx_std_clkout signal. Theseare the clock lines at the PCS and FPGA fabricinterface. When you enable PMA Direct mode (forArria V GT/ST only), the txphy_clk connects tothe transceiver tx_pma_clkout signal and therxphy_clk connects to the rx_pma_clkout signal.These are the clock lines at the PMA and PCSinterface.

TX/RX AVS Clock:

jesd204_tx_avs_clk

jesd204_rx_avs_clk

75–125 MHz The configuration clock for the JESD204B IP coreCSR through the Avalon-MM interface.

TransceiverManagement Clock:

reconfig_clk

100 MHz–125 MHz The configuration clock for the transceiver CSRthrough the Avalon-MM interface. This clock isexported only when the transceiver dynamicreconfiguration option is enabled.

This clock is only applicable for Arria 10 devices.

Device ClockIn a converter device, the sampling clock is typically the device clock.

For the JESD204 IP core in an FPGA logic device, the device clock is used as the transceiver PLL referenceclock and also the core PLL reference clock. The available frequency depends on the PLL type, bondingoption, number of lanes, and device family. During IP core generation, the Quartus Prime softwarerecommends the available device clock frequency for the transceiver PLL based on the user selection.

Note: You need to utilize the Altera PLL IP core (in Arria V and Stratix V devices) or Altera IOPLL IPcore (in Arria 10 devices) to generate the link clock and frame clock. The link clock is used in theJESD204 IP core (MAC) and the transport layer. You are recommended to use a dedicatedreference clock pin as the input reference clock source.

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Based on the JESD204B specification, the device clock is the timing reference and is source synchronouswith SYSREF. Due to the clock network architecture in the FPGA, you are recommended to use the deviceclock to generate the link clock and use the link clock as timing reference. For Subclass 1, to avoid halflink clock latency variation, you must supply the device clock at the same frequency as the link clock.

The JESD204B protocol does not support rate matching. Therefore, you must ensure that the TX or RXdevice clock (pll_ref_clk) and the PLL reference clock that generates link clock (txlink_clk or rxlink_clk)and frame clock (txframe_clk or rxframe_clk) have 0 ppm variation. Both PLL reference clocks shouldcome from the same clock chip.

Figure 4-8: JESD204B Subsystem Clock Diagram (For Arria V and Stratix V Devices)

Clock Jitter Cleaner

Converter Device 2

Converter Devicedevice_clock

SYSREF

Trace Matching (1)

MAC PHY

TransceiverPLL (2)

JESD204B IP Core

L

SYNC_N

Core PLLFPGA Device

(Normal Mode) (3)

JESD204BTransport

Layer

Avalon-ST

Link Clock

Frame Clock avs_clock

Test Pattern

Generator/Checker

Trace Matching (1)SYSREF

FPGA DeviceClock

Notes:1. The device clock to the Altera core PLL and SYSREF must be trace matched. The device clock to the converter device and SYSREF must be trace matched. The phase offset between the SYSREF to the FPGA and converter devices should be minimal.2. For Arria 10 devices, the transceiver PLL is outside of the JESD204B IP core. For Arria V and Stratix V devices, the transceiver PLL is part of the JESD204B IP core.3. The Altera core PLL provdes the link clock, frame clock, and AVS clock. The link clock and frame clock must be synchronous.

Related InformationClock Correlation on page 4-23

Link ClockThe device clock is the timing reference for the JESD204B system.

Due to the clock network architecture in the FPGA, JESD204 IP core does not use the device clock toclock the SYSREF signal because the GCLK or RCLK is not fully compensated. You are recommended to

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use the Altera PLL IP core (in Arria V and Stratix V devices) or Altera IOPLL IP core (in Arria 10 devices)to generate both the link clock and frame clock. The Altera PLL IP core must operate in normal mode orsource synchronous mode and uses a dedicated reference clock pin as the input reference clock source toachieve the following state:

• the GCLK and RCLK clock network latency is fully compensated.• the link clock and frame clock at the registers are phase-aligned to the input of the clock pin.

To provide consistency across the design regardless of frame clock and sampling clock, the link clock isused as a timing reference.

The Altera PLL IP core should provide both the frame clock and link clock from the same PLL as thesetwo clocks are treated as synchronous in the design.

For Subclass 0 mode, the device clock is not required to sample the SYSREF signal edge. The link clockdoes not need to be phase compensated to capture SYSREF. Therefore, you can generate both the linkclock and frame clock using direct mode in the Altera PLL IP core. If F = 4, where link clock is the same asthe frame clock, you can use the parallel clock output from the transceiver (txphy_clk or rxphy_clksignal) except when the PCS option is in PMA Direct mode.


Local Multi-Frame ClockThe Local Multi-Frame Clock (LMFC) is a counter generated from the link clock and depends on the Fand K parameter.

The K parameter must be set between 1 to 32 and meet the requirement of at least a minimum of 17 octetsand a maximum of 1024 octets in a single multi-frame. In a 32-bit architecture, the K × F must also be inthe order of four.

In a Subclass 1 deterministic latency system, the SYSREF frequency is distributed to the devices to alignthem in the system. The SYSREF resets the internal LMFC clock edge when the sampled SYSREF signal'srising edge transition from 0 to 1. Due to source synchronous signaling of SYSREF with respect to thedevice clock sampling (provided from the clock chip), the JESD204 IP core does not directly use thedevice clock to sample SYSREF but instead uses the link clock to sample SYSREF. Therefore, the AlteraPLL IP core that provides the link clock must to be in normal mode to phase-compensate the link clockto the device clock.

Based on hardware testing, to get a fixed latency, at least 32 octets are recommended in an LMFC periodso that there is a margin to tune the RBD release opportunity to compensate any lane-to-lane deskewacross multiple resets. If F = 1, then K = 32 would be optimal as it provides enough margin for systemlatency variation. If F = 2, then K = 16 and above (18/20/22/24/26/28/30/32) is sufficient to compensatelane-to-lane deskew.

The JESD204B IP core implements the local multi-frame clock as a counter that increments in link clockcounts. The local multi-frame clock counter is equal to (F × K/4) in link clock as units. The rising edge ofSYSREF resets the local multi-frame clock counter to 0. There are two CSR bits that controls SYSREFsampling.

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• csr_sysref_singledet—resets the local multi-frame clock counter once and automatically clearedafter SYSREF is sampled. This register also prevents CGS exit to bypass SYSREF sampling.

• csr_sysref_alwayson—resets the local multi-frame clock counter at every rising edge of SYSREF thatit detects. This register also enables the SYSREF period checker. If the provided SYSREF period violatesthe F and K parameter, an interrupt is triggered. However, this register does not prevent CGS-SYSREFrace condition.

The following conditions occur if both CSR bits are set:

• resets the local multi-frame clock counter at every rising edge of SYSREF.• prevents CGS-SYSREF race condition.• checks SYSREF period.


Clock CorrelationThis section describes the clock correlation between the device clock, link clock, frame clock, and localmulti-frame clock.

Example 1

Targeted device with LMF=222, K=16 and Data rate = 6.5 Gbps

Device Clock selected = 325 MHz (obtained during IP core generation)

Link Clock = 6.5 GHz/40 = 162.5 MHz Frame Clock = 6.5 GHz/(10x2) = 325 MHz

Local Multi-frame clock = 325 MHz / 16 = 20.3125 MHz

SYSREF Frequency = Local Multi-frame Clock / n; (n = integer; 1, 2, …)

Local multi-frame clock counter = (F × K/4) = (2×16/4) = 8 link clocks (20)

Example 2



Link Clock = 5 GHz/40 = 125 MHz (21)

Frame Clock = 5 GHz /(10×4) = 125 MHz (21)

Local Multi-frame clock = 125 MHz / 16 = 7.8125 MHz



Example 3


(20) Eight link clocks means that the local multi-frame clock counts from value 0 to 7 and then loopback to 0.(21) The link clock and frame clock are running at the same frequency. You only need to generate one clock from

the Altera PLL or Altera IO PLL IP core.

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Link Clock = 10 GHz/40 = 250 MHz

Frame Clock = 10 GHz/(10×1) = 1 GHz (22)

Local Multi-frame clock = 1 GHz / 32 = 31.25 MHz



Related Information

• Device Clock on page 4-20• Link Clock on page 4-21• Local Multi-Frame Clock on page 4-22

Reset SchemeAll resets in the JESD204B IP core are synchronous reset signals and should be asserted and deassertedsynchronously.

Note: Ensure that the resets are synchronized to the respective clocks for reset assertion and deassertion.

(22) For this example, the frame clock may not be able to run up to 1 GHz in the FPGA fabric. The JESD204Btransport layer in the design example supports running the data stream of half rate (1 GHz/2 = 500 MHz), attwo times the data bus width or of quarter rate (1GHz/4 = 250MHz), at four times the data bus width.

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Table 4-4: JESD204B IP Core Resets

Reset Signal Associated Clock Description

txlink_rst_n

rxlink_rst_n

TX/RX Link Clock Active low reset controlled by the clock andreset unit.

Altera recommends that you:

• Assert the txlink_rst_n/rxlink_rst_nand txframe_rst_n /rxframe_rst_nsignals when the transceiver is in reset.

• Deassert the txlink_rst_n and txframe_rst_n signals after the Altera PLL IP core islocked and the tx_ready[] signal from theTransceiver Reset Controller is asserted.

• Deassert the rxlink_rst_n and rxframe_rst_n signals after the Transceiver CDRrx_islockedtodata[] signal and rx_ready[] signal from the Transceiver ResetController are asserted.

The txlink_rst_n/rxlink_rst_n andtxframe_rst_n /rxframe_rst_n signals canbe deasserted at the same time. These resetscan only be deasserted after you configure theCSR registers.

txframe_rst_n

rxframe_rst_n

TX/RX Frame Clock Active low reset controlled by the clock andreset unit. If the TX/RX link clock and the TX/RX frame clock has the same frequency, bothcan share the same reset.

tx_analogreset[L-1:0]

rx_analogreset[L-1:0]

Transceiver Native PHYAnalog Reset

Active high reset controlled by the transceiverreset controller. This signal resets the TX/RXPMA.

The link clock, frame clock, and AVS clockreset signals (txlink_rst_n/rxlink_rst_n,txframe_rst_n/rxframe_rst_n andjesd204_tx_avs_rst_n/jesd204_rx_avs_rst_n) can only be deasserted after thetransceiver comes out of reset. (23)

(23) Refer to the Altera Transceiver PHY IP Core User Guide and Altera Arria 10 Transceiver PHY IP CoreUser Guide for the timing diagram of the tx_analogreset, rx_analogreset, tx_digitalreset, andrx_digitalreset signals.

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Reset Signal Associated Clock Description

tx_digitalreset[L-1:0]

rx_digitalreset[L-1:0]

Transceiver Native PHYDigital Reset

Active high reset controlled by the transceiverreset controller. This signal resets the TX/RXPCS.

The link clock, frame clock, and AVS clockreset signals (txlink_rst_n/rxlink_rst_n,txframe_rst_n/rxframe_rst_n andjesd204_tx_avs_rst_n/jesd204_rx_avs_rst_n) can only be deasserted after thetransceiver comes out of reset. (23)

jesd204_tx_avs_rst_n

jesd204_rx_avs_rst_n

TX/RX AVS (CSR)Clock

Active low reset controlled by the clock andreset unit. Typically, both signals can bedeasserted after the core PLL and transceiverPLL are locked and out of reset. If you want todynamically modify the LMF at run-time, youcan program the CSRs after AVS reset isdeasserted. This phase is referred to as theconfiguration phase.

After the configuration phase is complete, thenonly the txlink_rst_n/rxlink_rst_n andtxframe_rst_n/rxframe_rst_n signals can bedeasserted.

Related Information

• Altera Transceiver PHY IP Core User Guide• Altera Arria 10 Transceiver PHY IP Core User Guide

Reset SequenceAltera recommends that you assert reset for the JESD204B IP core and transport layer when powering upthe PLLs and transceiver.

The bring-up sequence:

1. Ensure that the core PLL and transceiver PLL are out of reset first.

If the Transceiver PHY Reset Controller and Transceiver Reconfiguration blocks rely on the clockfrom the core PLL output (for example, the management clocks and reset), then the core PLL must beout of reset first. If the Transceiver PHY Reset Controller and Transceiver Reconfiguration blocks areclocked by the external clock generator, the core PLL and transceiver PLL can be out of resetconcurrently.

2. Deassert the transceiver reset.3. Ensure that all core PLL and transceiver PLL are locked.4. Once the transceiver is out of reset, deassert the AV-MM interface reset for the IP core. At the configu‐

ration phase, the subsystem can program the converter devices through the SPI interface. During this

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https://documentation.altera.com/#/link/nik1398984401269/nik1398983846907/en-us



configuration phase, the subsystem may program the JESD204B IP core if the default IP core registersettings need to change.

5. Deassert both the link reset for the IP core and the frame reset for the transport layer.

Figure 4-9: Reset Sequence Timing Diagram

pll_ref_clk (tx/rx pll)

GENERIC STATES TRANSCEIVER & PLL POWERUP JESD204B IP OPERATION

pll_locked (from TX PLL)

txlink_clk/rxlink_clk

txlink_rst_n/rxlink_rst_n

txframe_clk/rxframe_clk

txframe_rst_n/rxframe_rst_n

JESD204B IP core register configuration and converter devices SPI programming JESD204B IP core link initialization begins

AVALON SLAVE CONFIGURATION PHASE

reconfig_clk (Arria 10 only)

Transceiver PHY Reset Controllerreset input (active high)

jesd204_tx_avs_clk/jesd204_rx_avs_clk

Transceiver PHY Reset Controllertx_ready/rx_ready

jesd204_tx_avs_rst_n/jesd204_rx_avs_rst_n

SignalsThe JESD204B IP core signals are listed by interface:

• Transmitter• Receiver

Note: You should terminate any unused signals.

Transmitter

Table 4-5: Transmitter Signals

Signal Width Direction Description

Clocks and Resets

pll_ref_clk 1 Input Transceiver reference clock signal. Thereference clock selection depends on theFPGA device family and data rate.

This signal is only applicable for V seriesFPGA variants.

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txlink_clk 1 Input TX link clock signal. This clock is equal to theTX data rate divided by 40.

For Subclass 1, you cannot use the output oftxphy_clk signal as txlink_clk signal . Tosample SYSREF correctly, the core PLL mustprovide the txlink_clk signal and must beconfigured as normal operating mode.

txlink_rst_n_reset_n 1 Input Reset for the TX link clock signal. This reset isan active low signal.

txphy_clk[] L Output TX parallel clock output for the TX transceiverwith PCS option in Hard PCS or Soft PCSmode. This clock has the same frequency astxlink_clk signal. For PCS option in PMADirect mode, this clock is half the frequency oftxlink_clk signal.

This clock is output as an optional port foruser if the txlink_clk and txframe_clksignals are operating at the same frequency inSubclass 0 operating mode.

tx_digitalreset[] (24) L Input Reset for the transceiver PCS block. This resetis an active high signal.

tx_analogreset[] (24) L Input Reset for the transceiver PMA block. Thisreset is an active high signal.

pll_locked[] (24) L Output PLL locked signal for the hard transceiver.This signal is asserted to indicate that the TXtransceiver PLL is locked.

This signal is an output signal for V seriesFPGA variants but an input signal for 10 seriesFPGA variants and above.

tx_cal_busy[] (24) L Output TX calibration in progress signal. This signal isasserted to indicate that the TX transceivercalibration is in progress.

(24) The Transceiver PHY Reset Controller IP Core controls this signal.


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pll_powerdown[] (24) • 1 if bondingmode = "xN"

• L if bondingmode =feedback_compensation

Input TX transceiver PLL power down signal.


tx_bonding_clocks

(Single Channel)

tx_bonding_clocks_

ch<0..L-1> (MultipleChannels)

6 Input The transceiver PLL bonding clocks. Thetransceiver PLL generation provides theseclocks.

This signal is only available if you selectBonded mode for Arria 10 FPGA variants.

tx_serial_clk0 (SingleChannel)

tx_serial_clk0_

ch<0..L-1> (MultipleChannels)

1 Input The transceiver PLL serial clock. This is theserializer clock in the PMA. The transceiverPLL generation provides these clocks.

This signal is only available if you select Non-bonded mode for Arria 10 FPGA variants.


Transceiver Interface

tx_serial_data[] L Output Differential high speed serial output data. Theclock is embedded in the serial data stream.

reconfig_to_xcvr[] • (L+1)*70 ifbonding mode ="xN"

• L*140 ifbonding mode =feedbackcompensation

Input Reconfiguration signals from the TransceiverReconfiguration Controller IP core to the PHYdevice.


You must connect these signals to theTransceiver Reconfiguration Controller IPcore regardless of whether run-time reconfigu‐ration is enabled or disabled. The TransceiverReconfiguration Controller IP core alsosupports various calibration function duringtransceiver power up.

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reconfig_from_xcvr[] • (L+1)*46 ifbonding mode ="xN"

• L*92 if bondingmode =feedbackcompensation

Output Reconfiguration signals to the TransceiverReconfiguration Controller IP core.


You must connect these signals to theTransceiver Reconfiguration Controller IPcore regardless of whether run-time reconfigu‐ration is enabled or disabled. The TransceiverReconfiguration Controller IP core alsosupports various calibration function duringtransceiver power up.

reconfig_clk 1 Input The Avalon-MM clock input. The frequencyrange is 100–125 MHz.

This signal is only available if you enabledynamic reconfiguration for Arria 10 FPGAvariants.

reconfig_reset 1 Input Reset signal for the Transceiver Reconfigura‐tion Controller IP core. This signal is activehigh and level sensitive.


reconfig_avmm_

address[]log2L*1024 Input The Avalon-MM address.


reconfig_avmm_

writedata[]32 Input The input data.


reconfig_avmm_

readdata[]32 Output The output data.



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reconfig_avmm_write 1 Input Write signal. This signal is active high.


reconfig_avmm_read 1 Input Read signal. This signal is active high.


reconfig_avmm_

waitrequest1 Output Wait request signal.



Avalon-ST Interface

jesd204_tx_link_

data[]L*32 Input Indicates a 32-bit user data at txlink_clk

clock rate, where four octets are packed into a32-bit data width per lane. The data format isbig endian.

The first octet is located at bit[31:24], followedby bit[23:16], bit[15:8], and the last octet isbit[7:0]. Lane 0 data is always located in thelower 32-bit data. If more than one lane isinstantiated, lane 1 is located at bit[63:32],with the first octet position at bit[63:56].

jesd204_tx_link_

valid1 Input Indicates whether the data from the transport

layer is valid or invalid. The Avalon-ST sinkinterface in the TX core cannot be backpres‐sured and assumes that data is always valid onevery cycle when the jesd204_tx_link_readysignal is asserted.

• 0—data is invalid• 1—data is valid

jesd204_tx_link_

ready1 Output Indicates that the Avalon-ST sink interface in

the TX core is ready to accept data. TheAvalon-ST sink interface asserts this signal onthe JESD204B link state of USER_DATAphase. The ready latency is 0.

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jesd204_tx_frame_

ready1 Output Indicates that the Avalon-ST sink interface in

the transport layer is ready to accept data. TheAvalon-ST sink interface asserts this signal onthe JESD204B link state of ILAS 4th

multiframe and also the USER_DATA phase.The ready latency is 0.


Avalon-MM Interface

jesd204_tx_avs_clk 1 Input The Avalon-MM interface clock signal. Thisclock is asynchronous to all the functionalclocks in the JESD204B IP core. TheJESD204B IP core can handle any cross clockratio and therefore the clock frequency canrange from 75 MHz to 125 MHz.

jesd204_tx_avs_rst_n 1 Input This reset is associated with the jesd204_tx_avs_clk signal. This reset is an active lowsignal. You can assert this reset signalasynchronously but must deassert it synchro‐nously to the jesd204_tx_avs_clk signal.After you deassert this signal, the CPU canconfigure the CSRs.

jesd204_tx_avs_

chipselect1 Input When this signal is present, the slave port

ignores all Avalon-MM signals unless thissignal is asserted. This signal must be used incombination with read or write. If the Avalon-MM bus does not support chip select, you arerecommended to tie this port to 1.

jesd204_tx_avs_

address[]8 Input For Avalon-MM slave, the interconnect

translates the byte address into a word addressin the address space so that each slave access isfor a word of data. For example, address = 0selects the first word of the slave and address =1 selects the second word of the slave.

jesd204_tx_avs_

writedata[]32 Input 32-bit data for write transfers. The width of

this signal and the jesd204_tx_avs_readdata[31:0] signal must be the same ifboth signals are present


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jesd204_tx_avs_read 1 Input This signal is asserted to indicate a readtransfer. This is an active high signal andrequires the jesd204_tx_avs_readdata[31:0] signal to be in use.

jesd204_tx_avs_write 1 Input This signal is asserted to indicate a writetransfer. This is an active high signal andrequires the jesd204_tx_avs_writedata[31:0] signal to be in use.

jesd204_tx_avs_

readdata[]32 Output 32-bit data driven from the Avalon-MM slave

to master in response to a read transfer.

jesd204_tx_avs_

waitrequest1 Output This signal is asserted by the Avalon-MM slave

to indicate that it is unable to respond to aread or write request. The JESD204B IP coreties this signal to 0 to return the data in theaccess cycle.


JESD204 Interface

sysref 1 Input SYSREF signal for JESD204B Subclass 1implementation.

For Subclass 0 and Subclass 2 mode, tie-offthis signal to 0.

sync_n 1 Input Indicates SYNC_N from the converter device orreceiver. This is an active low signal and isasserted 0 to indicate a synchronizationrequest or error reporting from the converterdevice.

To indicate a synchronization request, theconverter device must assert this signal for atleast five frames and nine octets.

To indicate an error reporting, the converterdevice must ensure that the pulse is at leastone cycle of the txlink_clk signal or twocycles of the txframe_clk signal (whicheverperiod is longer).

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dev_sync_n 1 Output Indicates a clean synchronization request. Thisis an active low signal and is asserted 0 toindicate a synchronization request only. Thesync_n signal error reporting is being maskedout of this signal. This signal is also assertedduring software-initiated synchronization.

mdev_sync_n 1 Input Indicates a multidevice synchronizationrequest. Synchronize signal combinationshould be done externally and then input tothe JESD204B IP core through this signal.

• For subclass 0—combine the dev_sync_nsignal from all multipoint links beforeconnecting to the mdev_sync_n signal.

• For subclass 1—connect the dev_sync_nsignal to the mdev_sync_n signal for eachlink respectively.

In a single link instance where multidevicesynchronization is not needed, tie the dev_sync_n signal to this signal.


CSR

jesd204_tx_frame_

error1 Input Optional signal to indicate an empty data

stream due to invalid data. This signal isasserted high to indicate an error during datatransfer from the transport layer to the TXcore.

csr_l[] 5 Output Indicates the number of active lanes for thelink. The transport layer can use this signal asa run-time parameter.

csr_f[] 8 Output Indicates the number of octets per frame. Thetransport layer can use this signal as a run-time parameter.

csr_k[] 5 Output Indicates the number of frames permultiframe. The transport layer can use thissignal as a run-time parameter.


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csr_m[] 8 Output Indicates the number of converters for thelink. The transport layer can use this signal asa run-time parameter.

csr_cs[] 2 Output Indicates the number of control bits persample. The transport layer can use this signalas a run-time parameter.

csr_n[] 5 Output Indicates the converter resolution. Thetransport layer can use this signal as a run-time parameter.

csr_np[] 5 Output Indicates the total number of bits per sample.The transport layer can use this signal as arun-time parameter.

csr_s[] 5 Output Indicates the number of samples per converterper frame cycle. The transport layer can usethis signal as a run-time parameter.

csr_hd 1 Output Indicates the high density data format. Thetransport layer can use this signal as a run-time parameter.

csr_cf[] 5 Output Indicates the number of control words perframe clock period per link. The transportlayer can use this signal as a run-timeparameter.

csr_lane_powerdown[] L Output Indicates which lane is powered down. Youneed to set this signal if you have configuredthe link and want to reduce the number ofactive lanes.

csr_tx_testmode[] 4 Output Indicates the address space that is reserved forDLL testing within the JESD204B IP core.

• 0—reserved for the IP core.• 1—program different tests in the transport

layer.

Refer to csr_tx_testmode register.

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csr_tx_testpattern_

a[]32 Output A 32-bit fixed data pattern for the test

mode. (25)

csr_tx_testpattern_

b[]32 Output A 32-bit fixed data pattern for the test

mode. (25)

csr_tx_testpattern_

c[]32 Output A 32-bit fixed data pattern for the test

mode. (25)

csr_tx_testpattern_

d[]32 Output A 32-bit fixed data pattern for the test

mode. (25)


Out-of-band (OOB)

jesd204_tx_int 1 Output Interrupt pin for the JESD204B IP core.Interrupt is asserted when any error orsynchronization request is detected. Configurethe tx_err_enable register to set the type oferror that can trigger an interrupt.


Debug or Testing

jesd204_tx_dlb_

data[]L*32 Output Optional signal for parallel data from the DLL

in TX to RX loopback testing. (26)

jesd204_tx_dlb_

kchar_data[]L*4 Output Optional signal to indicate the K character

value for each byte in TX to RX loopbacktesting. (26)

Receiver

Table 4-6: Receiver Signals


Clocks and Resets

pll_ref_clk 1 Input Transceiver reference clock signal.

(25) You can use this signal in the transport layer to configure programmable test pattern.(26) This signal is only for internal testing purposes. You can leave this signal disconnected.

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rxlink_clk 1 Input RX link clock signal used by the Avalon-STinterface. This clock is equal to RX data ratedivided by 40.

For Subclass 1, you cannot use the output ofrxphy_clk signal as rxlink_clk signal. To sampleSYSREF correctly, the core PLL must provide therxlink_clk signal and must be configured asnormal operating mode.

rxlink_rst_n_reset_n 1 Input Reset for the RX link clock signal. This reset is anactive low signal.

rxphy_clk[] L Output Recovered clock signal. This clock is derived fromthe clock data recovery (CDR) and the frequencydepends on the JESD204B IP core data rate.

For PCS option in Hard PCS or Soft PCS mode,this clock has the same frequency as the rxlink_clk signal. For PCS option in PMA Direct mode,this clock is half the frequency of rxlink_clksignal.

rx_digitalreset[] (27) L Input Reset for the transceiver PCS block. This reset is anactive high signal.

rx_analogreset[] (27) L Input Reset for the CDR and transceiver PMA block.This reset is an active high signal.

rx_islockedtodata[] (27) L Output This signal is asserted to indicate that the RX CDRPLL is locked to the RX data and the RX CDR haschanged from LTR to LTD mode.

rx_cal_busy[] (27) L Output RX calibration in progress signal. This signal isasserted to indicate that the RX transceiver calibra‐tion is in progress.


Transceiver Interface

rx_serial_data[] L Input Differential high speed serial input data. The clockis recovered from the serial data stream.

(27) The Transceiver PHY Reset Controller IP Core controls this signal.

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reconfig_to_xcvr[] L*70 Input Dynamic reconfiguration input for the hardtransceiver.

This signal is only applicable for V series FPGAvariants.

You must connect these signals to the TransceiverReconfiguration Controller IP core regardless ofwhether run-time reconfiguration is enabled ordisabled. The Transceiver ReconfigurationController IP core also supports various calibra‐tion function during transceiver power up.

reconfig_from_xcvr[] L*46 Output Dynamic reconfiguration output for the hardtransceiver.

This signal is only applicable for V series FPGAvariants.

You must connect these signals to the TransceiverReconfiguration Controller IP core regardless ofwhether run-time reconfiguration is enabled ordisabled. The Transceiver ReconfigurationController IP core also supports various calibra‐tion function during transceiver power up.

reconfig_clk 1 Input The Avalon-MM clock input. The frequency rangeis 100–125 MHz.

This signal is only available if you enable dynamicreconfiguration for Arria 10 FPGA variants.

reconfig_reset 1 Input Reset signal for the Transceiver ReconfigurationController IP core. This signal is active high andlevel sensitive.


reconfig_avmm_

address[]log2L*1024 Input The Avalon-MM address.


reconfig_avmm_

writedata[]32 Input The input data.



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reconfig_avmm_

readdata[]32 Output The output data.


reconfig_avmm_write 1 Input Write signal. This signal is active high.


reconfig_avmm_read 1 Input Read signal. This signal is active high.


reconfig_avmm_

waitrequest1 Output Wait request signal.



Avalon-ST Interface

jesd204_rx_link_data[] L*32 Output Indicates a 32-bit data from the DLL to thetransport layer. The data format is big endian,where the earliest octet is placed in bit [31:24] andthe latest octet is placed in bit [7:0].

jesd204_rx_link_valid 1 Output Indicates whether the data to the transport layer isvalid or invalid. The Avalon-ST source interface inthe RX core cannot be backpressured and willtransmit the data when the jesd204_rx_data_valid signal is asserted.


jesd204_rx_link_ready 1 Input Indicates that the Avalon-ST sink interface in thetransport layer is ready to receive data.

jesd204_rx_frame_error 1 Input Indicates an empty data stream due to invalid data.This signal is asserted high to indicate an errorduring data transfer from the RX core to thetransport layer.


Avalon-MM Interface

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jesd204_rx_avs_clk 1 Input The Avalon-MM interface clock signal. This clockis asynchronous to all the functional clocks in theJESD204B IP core. The JESD204B IP core canhandle any cross clock ratio and therefore theclock frequency can range from 75 MHz to 125MHz.

jesd204_rx_avs_rst_n 1 Input This reset is associated with the jesd204_rx_avs_clk signal. This reset is an active low signal. Youcan assert this reset signal asynchronously butmust deassert it synchronously to the jesd204_rx_avs_clk signal. After you deassert this signal,the CPU can configure the CSRs.

jesd204_rx_avs_

chipselect1 Input When this signal is present, the slave port ignores

all Avalon-MM signals unless this signal isasserted. This signal must be used in combinationwith read or write. If the Avalon-MM bus does notsupport chip select, you are recommended to tiethis port to 1.

jesd204_rx_avs_

address[]8 Input For Avalon-MM slave, the interconnect translates

the byte address into a word address in the addressspace so that each slave access is for a word of data.For example, address = 0 selects the first word ofthe slave and address = 1 selects the second wordof the slave.

jesd204_rx_avs_

writedata[]32 Input 32-bit data for write transfers. The width of this

signal and the jesd204_rx_avs_readdata[31:0]signal must be the same if both signals are present.

jesd204_rx_avs_read 1 Input This signal is asserted to indicate a read transfer.This is an active high signal and requires thejesd204_rx_avs_readdata[31:0] signal to be inuse.

jesd204_rx_avs_write 1 Input This signal is asserted to indicate a write transfer.This is an active high signal and requires thejesd204_rx_avs_writedata[31:0] signal to bein use.

jesd204_rx_avs_

readdata[]32 Output 32-bit data driven from the Avalon-MM slave to

master in response to a read transfer.


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jesd204_rx_avs_

waitrequest1 Output This signal is asserted by the Avalon-MM slave to

indicate that it is unable to respond to a read orwrite request. The JESD204B IP core ties thissignal to 0 to return the data in the access cycle.


JESD204 Interface

sysref 1 Input SYSREF signal for JESD204B Subclass 1implementation.

For Subclass 0 and Subclass 2 mode, tie-off thissignal to 0.

dev_sync_n 1 Output Indicates a SYNC~ from the receiver. This is anactive low signal and is asserted 0 to indicate asynchronization request. Instead of reporting thelink error through this signal, the JESD204B IPcore uses the jesd204_rx_int signal to interruptthe CPU.

sof[] 4 Output Indicates a start of frame.

• [3]—start of frame for jesd204_rx_link_data[31:24]




somf[] 4 Output Indicates a start of multiframe.

• [3]—start of multiframe for jesd204_rx_link_data[31:24]




dev_lane_aligned 1 Output Indicates that all lanes for this device are aligned.

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alldev_lane_aligned 1 Input Aligns all lanes for this device.

For multidevice synchronization, multiplex all thedev_lane_aligned signals before connecting tothis signal pin.

For single device support, connect the dev_lane_aligned signal back to this signal.


CSR

csr_l[] 5 Output Indicates the number of active lanes for the link.The transport layer can use this signal as a run-time parameter.

csr_f[] 8 Output Indicates the number of octets per frame. Thetransport layer can use this signal as a run-timeparameter.

csr_k[] 5 Output Indicates the number of frames per multiframe.The transport layer can use this signal as a run-time parameter.

csr_m[] 8 Output Indicates the number of converters for the link.The transport layer can use this signal as a run-time parameter.

csr_cs[] 2 Output Indicates the number of control bits per sample.The transport layer can use this signal as a run-time parameter.

csr_n[] 5 Output Indicates the converter resolution. The transportlayer can use this signal as a run-time parameter.

csr_np[] 5 Output Indicates the total number of bits per sample. Thetransport layer can use this signal as a run-timeparameter.

csr_s[] 5 Output Indicates the number of samples per converter perframe cycle. The transport layer can use this signalas a run-time parameter.

csr_hd 1 Output Indicates the high density data format. Thetransport layer can use this signal as a run-timeparameter.


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csr_cf[] 5 Output Indicates the number of control words per frameclock period per link. The transport layer can usethis signal as a run-time parameter.

csr_lane_powerdown[] L Output Indicates which lane is powered down. You needto set this signal if you have configured the linkand want to reduce the number of active lanes.

csr_rx_testmode[] 4 Output Indicates the address space that is reserved for DLLtesting within the JESD204B IP core.

• 0—reserved for the IP core.• 1—program different tests in the transport

layer.

Refer to the csr_rx_testmoderegister.


Out-of-band (OOB)

jesd204_rx_int 1 Output Interrupt pin for the JESD204B IP core. Interruptis asserted when any error is detected. Configurethe rx_err_enable register to set the type of errorthat can trigger an interrupt.


Debug or Testing

jesd204_rx_dlb_data[] L*32 Input Optional signal for parallel data to the DLL in TXto RX loopback testing. (28)

jesd204_rx_dlb_data_

valid[]L Input Optional signal to indicate valid data for each byte

in TX to RX loopback testing. (28)

jesd204_rx_dlb_kchar_

data[]L*4 Input Optional signal to indicate the K character value

for each byte in TX to RX loopback testing. (28)

jesd204_rx_dlb_

errdetect[]L*4 Input Optional signal to indicate 8B/10B error. (28)

jesd204_rx_dlb_

disperr[]L*4 Input Optional signal to indicate running disparity. (28)

(28) This signal is only for internal testing purposes. Tie this signal to low.

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RegistersThe JESD204B IP core supports a basic one clock cycle transaction bus. There is no support for burstmode and wait-state feature (the avs_waitrequest signal is tied to 0). The JESD204B IP core Avalon-MM slave interface has a data width of 32 bits and is implemented based on word addressing. TheAvalon-MM slave interface does not support byte enable access.

Each write transfer has a writeWaitTime of 0 cycle while a read transfer has a readWaitTime of 1 cycle andreadLatency of 1 cycle.

The following HTML files list the TX and RX core registers. The register address in the register map iswritten based on byte addressing. The Qsys interconnect automatically converts from byte to wordaddressing. You do not need to manually shift the address bus. If the Avalon-MM master interfaces to theIP core Avalon-MM slave without the Qsys interconnect, to perform byte to word addressing conversion,you are recommended to shift the Avalon-MM master address bus by 2 bits (divide by 4) whenconnecting to the IP core's Avalon-MM slave. In this connection, the Avalon-MM master address bit[2]connects to the IP core (Avalon-MM slave) address bit[0], while the Avalon-MM master bit[9] connectsto the IP core address bit[7].

• TX register map• RX register map

Register Access Type ConventionThis table describes the register access type for Altera IP cores.

Table 4-7: Register Access Type and Definition

Access Type Definition

RO Software read only (no effect on write). The value is hard-tied internally to either '0'or '1' and does not vary.

RO/v Software read only (no effect on write). The value may vary.

RC • Software reads shall return the current bit value, then the bit is self-clear to 0.• Software reads also cause the bit value to be cleared to 0.

RW • Software reads shall return the current bit value.• Software writes shall set the bit to the desired value.

RW1C • Software reads shall return the current bit value.• Software writes 0 shall have no effect.• Software writes 1 shall clear the bit to 0, if the bit has been set to 1 by hardware.• Hardware sets the bit to 1.• Software clear has higher priority than hardware set.

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Access Type Definition

RW1S • Software reads shall return the current bit value.• Software writes 0 shall have no effect.• Software writes 1 shall set the bit to 1.• Hardware clears the bit to 0, if the bit has been set to 1 by software.• Software set has higher priority than hardware clear.

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JESD204B IP Core Design Examples 52015.11.02


This section describes the JESD 204B IP core design examples that you can generate through the IPcatalog in the Quartus Prime software.This section also describes the implementation guidelines.

The Altera JESD204B IP core offers two design examples:

• RTL State Machine Control (supports Arria V, Cyclone V, Stratix V, and Arria 10 devices only)• Nios II Control (supports Arria 10 devices only)

Supported ConfigurationsThe design examples only support a limited set of JESD204B IP core parameter configurations.

The IP Catalog parameter editor allows you to generate a design example only if the parameter configura‐tions matches those in the tables below.

Table 5-1: Supported JESD204B IP Core Parameter Configurations (L, M, F Values)

JESD204B IP Parameters

L M F

1 1 21 1 41 2 41 4 82 1 12 1 22 1 42 2 22 2 42 4 44 2 14 2 2





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L M F

4 4 24 4 44 8 48 1 18 2 18 4 18 4 2

Table 5-2: Supported JESD204B IP Core Parameter Configurations

JESD204B IP Parameters Value

Wrapper Options Both Base and PhyData Path DuplexJESD204B Subclass 1Data Rate • 6144 (Arria V, Stratix V, and Arria 10)

• 5000 (Cyclone V)

PCS Option Enabled Hard PCSPLL Type CMUBonding Mode • Bonded (For Enable Transceiver Dynamic

Reconfiguration option set to No)• Non-bonded (For Enable Transceiver Dynamic

Reconfiguration option set to Yes)

Enable Transceiver Dynamic Reconfiguration • No (Bonding Mode must be set to Bonded)• Yes (Bonding Mode must be set to Non-bonded)• For Arria 10:

• No (only the RTL state machine controldesign example is available for generation)

• Yes (only Nios control design example isavailable for generation)

PLL/CDR Reference Clock Frequency • 153.6 (Arria V, Stratix V, and Arria 10; allsupported L parameter values except L=8)

• 307.2 (Arria V, Stratix V, and Arria 10; L=8)• 125 (Cyclone V; all supported L parameter

values except L=8)• 250 (Cyclone V; L=8)

Enable Bit Reversal And Byte Reversal No

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Altera Corporation JESD204B IP Core Design Examples

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JESD204B IP Parameters Value

N 16N’ 16CS 0CF 0High Density User Data Format (HD) 0Enable scramble (SCR) YesEnable Error Code Correction (ECC_EN) Yes

Table 5-3: Valid Options Available for Design Example Generation

Device SupportedJESD204B IP

Core Configura‐tions

ExampleDesign Type

GenerateGenericExampleDesign?

ExampleDesign Files

HDL Format Target Develop‐ment Kit

Stratix V,Arria V,CycloneV

No None No — — —No None Generic RTL Simulation Verilog,

VHDL—

No None Generic RTL Synthesis Verilog (29) —Yes RTL — Simulation Verilog,

VHDL—

Yes RTL — Synthesis Verilog (29) —

(29) For synthesis flow, only the Verilog HDL format is available.

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JESD204B IP Core Design Examples Altera Corporation

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Device SupportedJESD204B IP

Core Configura‐tions

ExampleDesign Type

GenerateGenericExampleDesign?

ExampleDesign Files

HDL Format Target Develop‐ment Kit

Arria 10

No None No — — —

No None Generic RTL Simulation Verilog,VHDL

—

No None Generic RTL Synthesis Verilog (29) —No None Generic Nios Synthesis (30) Verilog (29) • None

• Arria10 (31)

Yes RTL — Simulation Verilog,VHDL

—

Yes RTL — Synthesis Verilog (29) —Yes Nios — Synthesis (30) Verilog (29) • None

• Arria10 (31)

Generic Design ExampleIf the JESD204B IP parameters that you select does not match any design example that is available, there isan option for you to generate a generic design example.

A generic design example is a design that has pre-selected IP parameters that matches the list of supportedIP parameters for the design example.

Note: The generated generic example design may have IP parameters that differ from the parameters ofyour IP core. Modify the generic example design according to your system specifications.

The table below lists the parameters in the generic design example.

Table 5-4: IP Parameter Settings for Generic Design Example


Design Example

Generic RTL State MachineControl

Generic Nios II Control

Devices Support V series and Arria 10 Arria 10L 2 2M 2 2

(30) For Nios II control unit example design option, only synthesis filesets are available and only Verilog HDLformat is supported.

(31) For Nios II control unit example design option, you can choose not to target your design to any develop‐ment kit or choose to target the Arria 10 GX FPGA Development Kit.

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Design Example

Generic RTL State MachineControl

Generic Nios II Control

F 2 2K 16 16S 1 1Wrapper Options Both Base and Phy Both Base and PhyData Path Duplex DuplexJESD204B Subclass 1 1Data Rate 6144 6144PCS Option Enabled Hard PCS Enabled Hard PCSPLL Type CMU CMUBonding Mode Bonded Non-bondedEnable Transceiver Dynamic Reconfiguration No YesPLL/CDR Reference Clock Frequency 153.6 153.6Enable Bit Reversal And Byte Reversal No NoN 16 16N’ 16 16CS 0 0CF 0 0High Density User Data Format (HD) 0 0Enable scramble (SCR) Yes YesEnable Error Code Correction (ECC_EN) Yes Yes

PresetsStandard presets allow instant entry of pre-selected parameter values in the IP and Example Design tabs.You can select the presets at the lower right window in the parameter editor.

The parameter values chosen for the presets belong to the group of supported JESD204B IP configura‐tions for design example generation. You can select one of the presets available for your target device toquickly generate a design example without having to manually set each parameter in the IP tab andverifying that the parameter matches the supported configurations set. There are two preset settingsavailable in the library:

• RTL State Machine Control example design• Nios II Control example design

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Note: Selecting a preset will overwrite any pre-existing parameter selections for the IP core under the IPtab. Use the generic example design option instead if you want to retain your pre-selected IP coreparameter selections.

Table 5-5: Preset Settings

JESD204B IP ParametersPresets

RTL State Machine Control Nios II Control

Devices Support V series and Arria 10 Arria 10

L 2 2

M 2 2

F 2 2

K 16 16

S 1 1

Wrapper Options Both Base and Phy Both Base and Phy

Data Path Duplex Duplex

JESD204B Subclass 1 1

Data Rate 6144 6144

PCS Option Enabled Hard PCS Enabled Hard PCS

PLL Type CMU CMU

Bonding Mode Bonded Non-bonded

Enable Transceiver Dynamic Reconfiguration Yes Yes

PLL/CDR Reference Clock Frequency 153.6 153.6

Enable Bit Reversal And Byte Reversal No No

N 16 16

N’ 16 16

CS 0 0

CF 0 0

High Density User Data Format (HD) 0 0

Enable scramble (SCR) Yes Yes

Enable Error Code Correction (ECC_EN) Yes Yes

Selecting and Generating the Design ExampleYou can access and generate the IP core design example through the IP Catalog parameter editor.

Follow the steps below to launch the design example GUI and generate the design example.

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1. In the IP Catalog (Tools > IP Catalog), select the JESD204B IP core.2. Specify an entity name and location for your custom IP variation. This name identifies the IP core

variation files in your project. If prompted, also specify the target Altera device family. Click OK.3. In the parameter editor, click on the IP tab and set the JESD204B IP core parameters as per your

specifications. If you want to pre-fill the parameters with the set of parameter values that result in avalid example design, use the presets in the Presets tab. Refer to Presets on page 5-5 for more details.

4. In the parameter editor, click on the Example Design tab.5. Under the Available Example Designs section, select the available designs. The options you can select

are based on the design examples that are available.

• None: No design example available that matches the IP parameters selected.• RTL State Machine Control: Design example has RTL state machine as control unit.• Nios II Control: Design example has Nios II processor as control unit. This option is available for

Arria 10 devices only.6. If the Select Design option under the Available Example Designs section displays None, the Generate

generic example design selection appears. In the Generate generic example design list, select one ofthe options available to generate a generic design example.

• No: No generic design example will be generated.• Generic RTL State Machine Control: Generic design example has RTL state machine as control

unit.• Generic Nios Control: Generic design example has Nios II processor as control unit. This option is

available for Arria 10 devices only.

Note: The generic design example parameter selection may not match the parameters that youselected in the IP tab. You can modify the generated generic design example files to match yourdesired IP parameter settings.

7. Under the Example Design Files section, select the desired design example files. The options you canselect are based on the design examples that are available.

• Simulation: Generate simulation files.• Synthesis: Generate synthesis files.

8. Under the Generated HDL Format for Simulation section (only available if the Simulation option ischecked), select the desired HDL format. The options you can select are based on the design examplesthat are available.

9. Under the Generated HDL Format for Synthesis section (only available if the Synthesis option ischecked), select the desired HDL format. The options you can select are based on the design examplesthat are available.

10.Under the Target Development Kit section, select the development kit that the design example willtarget. The options you can select are based on the design example that are available.

• None: Design example does not target any board. The target device is set to a default device andmay not match your selected target device in the Quartus project.

• Arria 10 GX FPGA Development Kit: Design example is targeted for Arria 10 GX FPGA develop‐ment kit. This option is available for Arria 10 devices only. The target device is Arria 10 GX FPGAand may not match your selected target device in the Quartus project.

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Note: The hardware example design targets an Arria 10 ES3 device. It cannot function correctly on anArria 10 production device.

11.Click the Generate Example Design button on the top right corner to generate the design examplebased on your settings.

a. If the selected design example in step 5 is None, and the generate generic design example selectionin step 6 is No, an error message is displayed and no design example will be generated.

b. If the selected design example in step 5 is RTL State Machine Control or Nios II Control, therelevant design example is generated with the JESD204B parameters matching the JESD204B IPparameter settings in the IP tab.

c. If the selected design example in step 5 is None, and the generate generic design example selectionfrom Step 6 is Generic RTL State Machine Control or Generic Nios II Control, the relevantgeneric design example is generated with the pre-set JESD204B parameters. You can then modifythe JESD204B parameters directly in the generated design files to match your desired parametersettings.

The design example files are generated in the folder that you specified when you clicked on GenerateExample Design. This is a self-contained design example folder that is in the same directory that containsthe generated IP files. All the files necessary to compile and run the design example, including anindependently generated JESD204B IP core module that is separate from the core module generated fromthe IP tab is stored in this folder and its sub directories.

Related Information

• Generating and Simulating the Design Example on page 5-62• Generating the Design Example For Compilation on page 5-64• Compiling the Design Example for Synthesis on page 5-81• Running the Software Control Flow on page 5-86

Design Example with RTL State Machine Control UnitThis design example with RTL state machine control unit is the legacy design example that was firstreleased in Quartus II version 13.1. The design example has the following key features:

• Supports Arria V, Cyclone V, Stratix V, and Arria 10 devices.• Purely hardware-implemented control path, no software control features.• Lower FPGA core resource utilization compared to Nios II processor control unit design example.• Available as a synthesizable design entity and a simulation model.

The design example entity consists of various components that interface with the JESD204B IP core todemonstrate the following features:

• single or multiple link configuration• different LMF settings with scrambling and internal serial loopback enabled• interoperability against diverse converter devices• dynamic reconfiguration

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Figure 5-1: RTL State Machine Control Unit Design Example Block Diagram

This figure illustrates the high level system architecture of the JESD204B IP core design example.

PatternGenerator

SampleMapper

(2)

(3)

(3)

(2)

(3) (6)

PCS Ser

PCS DesDeassembler

(TransportLayer)

Avalon-ST32 Bit RX Base

Core(Link Layer)

DuplexSerDes

PHY

32 Bit

32 Bit

sync_nrx_dev_sync_n

DAC sync_n

ADCrx_dev_sync_n

SPI DeviceClocktx_sysref

DeviceClockrx_sysref

SPI

Avalon-ST User Data

Avalon-ST User Data

test_mode

PatternGenerator

(2)

PatternChecker

(2)

(3)

(3)0

(4) (4) (5)

(8)

(5)

(4)(4)

TransceiverReconfiguration

Controller

TransceiverReset

Controller

Reconfig

Ready

ResetStatus rx_seriallpbken

Control Unit (CU)(10)

Avalon-MM

ROM SPIMaster (7)

Avalon-MM

Clock andSYSREF

DeviceClock

tx_sysrefrx_sysref

PLL Reconfiguration(11)

Avalon-MM

Frame ResetLink Reset

Avalon-MM Slave Reset

CSR

PLL(9)

reconfig

1: Frame Clock2: Link Clock

Device Clock Management Clock

JESD204B IP Core(Duplex)

(1)

(11)

1: Frame Clock Domain2: Link Clock Domain

Management Clock Domain (100 MHz)Device Clock Domain

Assembler(Transport

Layer)

Avalon-STAvalon-ST

32 Bit TX BaseCore

(Link Layer)

tx_sysref

rx_sysref

The list below describes the mechanism of the design example architecture (with reference to the notenumbers in the design example block diagram).

1. For multiple links, the JESD204B IP core is instantiated multiple times. For example, in 2x112 (LMF)configuration, two cores are instantiated, where each core is configured at LMF=112.

2. The number of pattern generator or pattern checker instances is equivalent to the parameter value ofLINK. The data bus width per instance is equivalent to the value of FRAMECLK_DIV*M*S*N.

3. The number of transport layer instances is equivalent to the parameter value of LINK. The legal valueof LINK is 1 and 2. The data bus width per instance is equivalent to the value ofFRAMECLK_DIV*M*S*N. The test_mode = 0 signal indicates a normal operation mode, where theassembler takes data from the Avalon-ST source. Otherwise, the assembler takes data from the patterngenerator.

4. The Avalon-ST interface data bus is fixed at 32-bit. The number of 32-bit data bus is equal to thenumber of lanes (L).

5. The number of lanes per converter device (L).6. You can enable internal serial loopback by setting the rx_seriallpbken input signal. You can

dynamically toggle this input signal. When toggled to 1, the RX path takes the serial input from the TX

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path internally in the FPGA. When toggled to 0, the RX path takes the serial input from the externalconverter device. During internal serial loopback mode, the assembler takes input from the patterngenerator.

7. A single serial port interface (SPI) master instance can control multiple SPI slaves. The SPI master is a4-wire instance. If the SPI slave is a 3-wire instance, use a bidirectional I/O buffer in between themaster and slave to interface the 4-wire master to 3-wire slave.

8. The SPI protocol interface. All slaves share the same data lines (MISO and MOSI, or DATAIO). Eachslave has its own slave select or chip select line (SS_n).

9. The PLL takes the device clock from an external clock chip as the input reference. The PLL generatestwo output clocks (utilizing two output counters from a single VCO). Clock 1 is the frame clock for thetransport layer, pattern generator, and pattern checker. Clock 2 is the link clock for the transport andlink layer.

10.The control unit implements a memory initialization file (MIF) method for configuring the SPI. EachMIF corresponds to a separate external converter per device or clock chip. For example, in a systemthat interacts with both DAC and ADC, two MIFs are needed—one each for DAC and ADC.

11.The PLL reconfiguration and transceiver reconfiguration controller instances are only required for runtime reconfiguration of the data rate.

Related InformationSystem Parameters on page 5-47Shows illustrations of single and multiple JESD204B links.

Design Example ComponentsThe RTL State Machine Control Unit design example for the JESD204B IP core consists of the followingcomponents:

• PLL• PLL reconfiguration• Transceiver reconfiguration controller• Transceiver reset controller• Pattern generator• Pattern checker• Assembler and deassembler (in the transport layer)• SPI• Control unit

The following sections describe in detail the function of each component.

PLLThe design example requires four different clock domains—device clock, management clock, frame clock,and link clock.

Typically, the device clock is generated from an external converter or a clock device while themanagement clock (AVS clock) is generated from an on-board 100 MHz oscillator.

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For instance, if the JESD204B IP core is configured at data rate of 6.144 Gbps, transceiver reference clockfrequency of 153.6 MHz, and number of octets per frame (F) = 2, the example below indicates the PLLclock frequencies:

• device clock = transceiver reference clock frequency = 153.6 MHz• link clock = 6144 / 40 = 153.6 MHz• frame clock = 153.6 x 32 / (8 x 2) = 307.2 MHz

Related Information

• Clocking Scheme on page 4-18More information about the JESD204B IP core clocks.

PLL Reconfiguration

The PLL reconfiguration utilizes the ALTERA_PLL_RECONFIG IP core to implement reconfigurationlogic to facilitate dynamic real-time reconfiguration of PLLs in Altera devices. You can use this megafunc‐tion IP core to update the output clock frequency, PLL bandwidth, and phase shifts in real time, withoutreconfiguring the entire FPGA.

The design example uses the MIF approach to reconfigure the core PLL. The ALTERA_PLL_RECONFIGIP core has two parameter options—Enable MIF Streaming and Path to MIF file—for the MIF input.Turn on Enable MIF Streaming option and set the core_pll.mif as the value to Path to MIF fileparameter.

The following PLL reconfiguration Avalon-MM operations occurs during data rate reconfiguration.

Table 5-6: PLL Reconfiguration Operation

Operation Avalon-MMInterface

Signal

ByteAddress

Offset(6bits)

Bit Value

Arria V and Stratix V Devices

Set MIF base address pll_mgmt_* 0x01F [8:0] 0x000 (maximum configuration)or

0x02E (downscale configuration)

Write to the START register tobegin

pll_mgmt_* 0x02 [0:0] 0x01

Arria 10 Devices

Start MIF streaming with MIFbase address specified in datavalue

pll_mgmt_* 0x010 [31:0] 0x000 (maximum configuration)or

0x02E (downscale configuration)(32)

(32) The MIF base address is 9 bits (LSB). The remaining bits are reserved.

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Related InformationAN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL ReconfigMegafunctionsMore information about the MIF streaming option.

Transceiver Reconfiguration Controller

The transceiver reconfiguration controller allows you to change the device transceiver settings at anytime. Any portion of the transceiver can be selectively reconfigured. Each portion of the reconfigurationrequires a read-modify-write operation (read first, then write), in such a way that it modifies only theappropriate bits in a register and not changing other bits.

In the design example, MIF approach is used to reconfigure the ATX PLL and transceiver channel in theJESD204 IP core via the Transceiver Reconfiguration Controller. The number of reconfiguration interfaceis determined by number of lanes (L) + number of TX_PLL (different number of TX_PLL for bonded andnon-bonded mode). Since the MIF approach reconfiguration for transceiver only supports non-bondedmode, the number of TX_PLL is equal to number of lanes. The number of reconfiguration interface = 2 xnumber of lanes (L).

The transceiver reconfiguration controller interfaces:

• MIF Reconfiguration Avalon-MM master interface—connects to the MIF ROM.• Transceiver Reconfiguration interface—connects to the JESD204B IP core, which eventually connects

to the native PHY.• Reconfiguration Management Avalon-MM slave interface—connects to the control unit.

Note: The transceiver reconfiguration controller is only used in Arria V and Stratix V devices. For Arria10 devices, the control unit directly communicates with the transceiver in the JESD204B IP corethrough the reconfig_avmm_* interface signals.

The following transceiver reconfiguration controller Avalon-MM operations are involved during data ratereconfiguration.

Table 5-7: Transceiver Reconfiguration Controller Operation for Arria V and Stratix V Devices

Operation Avalon-MMInterface Signal

Byte AddressOffset (6bits)

Bit Value

Write logical channel number reconfig_mgmt_* 0x38 [9:0] 0

Write MIF mode reconfig_mgmt_* 0x3A [3:2] 2'b00

Write 0 to streamer offset register reconfig_mgmt_* 0x3B [15:0] 0

Write MIF base address to streamerdata register

reconfig_mgmt_* 0X3C [31:0] *32'h1000

Initiate a write of all the above data reconfig_mgmt_* 0x3A [0] 1'b1

Write 1 to streamer offset register reconfig_mgmt_* 0x3B [15:0] 1

Write to streamer data register to set upMIF streaming

reconfig_mgmt_* 0x3C [31:0] 3

Initiate a write of all the above data tostart streaming the MIF

reconfig_mgmt_* 0x3A [0] 1'b1

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Operation Avalon-MMInterface Signal

Byte AddressOffset (6bits)

Bit Value

Read the busy bit to determine whenthe write has completed

reconfig_mgmt_* 0x3A [8] 1: Busy

0: Operationcompleted

Note: The above steps are repeated for the number of channels and followed by the number of TX_PLLs.

For Arria 10 devices, the only Avalon-MM operation is a direct write to the transceiver register throughthe reconfig_avmm_* interface at the JESD204B IP core. Every line in the MIF isDPRIO_ADDR[25:16]+ BIT_MASK[15:8]+ DATA[7:0]. The control unit maps theDPRIO_ADDR to reconfig_avmm_address and BIT_MASK + DATA to reconfig_avmm_data.

Related Information

• Altera Transceiver PHY IP Core User GuideMore information about the transceiver reconfiguration controller.

• Altera Arria 10 Transceiver PHY IP Core User Guide

Transceiver Reset Controller

The transceiver reset controller uses the Altera's Transceiver PHY Reset Controller IP Core to ensure areliable initialization of the transceiver. The reset controller has separate reset controls per channel tohandle synchronization of reset inputs, hysteresis of PLL locked status, and automatic or manual resetrecovery mode.

In this design example, the reset controller targets both the TX and RX channels. The TX PLL, TXChannel, and RX Channel parameters are programmable to accommodate single and multiple (2)JESD204B links.

Related Information

• Altera Transceiver PHY IP Core User GuideMore information about the Transceiver PHY Reset Controller IP Core.

• Arria V Device Handbook, Volume 2: TransceiversMore information about the device usage mode.

Pattern GeneratorThe pattern generator instantiates any supported generators and has an output multiplexer to select whichgenerated pattern to forward to the transport layer based on the test mode during run time. Additionally,the pattern generator also supports run-time reconfiguration (downscale) on the number of convertersper device (M) & samples per converter per frame (S).

The pattern generator can be a parallel PRBS, alternate checkerboard, or ramp wave generator. The dataoutput bus width of the pattern generator is equivalent to the value of FRAMECLK_DIV × M × S × N.

The pattern generator includes a REVERSE_DATA parameter to control data arrangement at the output.The default value of this parameter is 0.

• 0—no data rearrangement at the output of the generator.• 1—data rearrangement at the output of the generator.

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http://www.altera.com/literature/ug/xcvr_user_guide.pdf

http://www/literature/hb/arria-v/av_53003.pdf


For example, when M=2, S=1, N=16, F1/F2_FRAMECLK_DIV=1, the input or output data width equalsto [31:0], with the following data arrangement:

0: {m1s0[31:16], m0s0[15:0]}1: {m0s0[31:16], m1s0[15:0]}

Parallel PRBS Generator

PRBS generator circuits often consists of simple shift registers with feedback that serve as test sources forserial data links. The output sequence is not truly random but repeats after 2X–1 bits, where X denotes thelength of the shift register. Polynomial notation—which the polynomial order corresponds to the lengthof the shift register and the period of PRBS—provides a method of describing the sequence.

Alternate Checkerboard Generator

The alternate checkerboard generator circuit consists of simple flip registers that serve as test sources forserial data links.

The output sequence of subsequent N-bits sample is generated by inverting the previous N-bits (countingfrom LSB to MSB) of the same data pattern at that clock cycle. The first N-bits sample from LSB of thedata pattern on next clock cycle is generated by inverting the last N-bits sample on the MSB of the datapattern on current clock cycle.

Ramp Wave Generator

The ramp wave generator circuit consists of a simple register and adders that serve as test sources forserial data links.

The output sequence of subsequent N-bits sample is an increment by one of the previous N-bits sample(counting from LSB to MSB) in the same data pattern at that clock cycle. The first N-bits sample from LSBof the data pattern on next clock cycle is generated by an increment by one of the last N-bits sample onthe MSB of the data pattern on current clock cycle.

Pattern CheckerThe pattern checker instantiates any supported checkers and support run time reconfiguration(downscale) of the number of converters per device (M) and samples per converter per frame (S).

The pattern checker can be either a parallel PRBS checker, alternate checkerboard checker, or ramp wavechecker. The data input bus width of the pattern checker is equivalent to the value of FRAMECLK_DIV ×M × S × N.

The pattern checker includes an ERR_THRESHOLD parameter to control the number of error toleranceallowed in the checker. The default value of this parameter is 1.

The pattern checker also includes a REVERSE_DATA parameter to control data arrangement at the input.The default value of this parameter is 0.

• 0—no data rearrangement at the input of the checker.• 1—data rearrangement at the input of the checker.

Parallel PRBS Checker

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The PRBS checker contains the same polynomial as in the PRBS generator. The polynomial is onlyupdated when the enable signal is active, which indicates that the input data is valid. The feedback path isXOR'ed with the input data to do a comparison. The checker flags an error when it finds any singlemismatch between polynomial data and input data.

Alternate Checkerboard Checker

The alternate checkerboard checker is implemented in the same way as in the alternate checkerboardgenerator. To do a comparison, an initial seed internally generates a set of expected data pattern result toXOR'ed with the input data. The seed is updated only when the enable signal is active, which indicatesthat the input data is valid. The checker flags an error when it finds any single mismatch between theexpected data and input data.

Ramp Wave Checker

The ramp wave checker is implemented in the same way as in the ramp wave generator. To do acomparison, an initial seed internally generates a set of expected data pattern result to XOR'ed with theinput data. The seed is updated only when the enable signal is active, which indicates that the input data isvalid. The checker flags an error when it finds any single mismatch between the expected data and inputdata.

Transport LayerThe transport layer in the JESD204B IP core consists of an assembler at the TX path and a deassembler atthe RX path.

The transport layer provides the following services to the application layer (AL) and the DLL:

• The assembler at the TX path:

• maps the conversion samples from the AL (through the Avalon-ST interface) to a specific format ofnon-scrambled octets, before streaming them to the DLL.

• reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interfaceduring TX data streaming.

• The deassembler at the RX path:

• maps the descrambled octets from the DLL to a specific conversion sample format before streamingthem to the AL (through the Avalon-ST interface).

• reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interfaceduring RX data streaming.

Supported System Configuration

The transport layer supports static configurations where before compilation, you can modify the configu‐rations using the IP core's parameter editor in the Quartus Prime software. To change to another configu‐ration, you have to recompile the design. The following list describes the supported configurations for thetransport layer:

• Data rate (maximum) = 12.5 Gbps (F1_FRAMECLK_DIV = 4 and F2_FRAMECLK_DIV = 2)• L = 1–8• F = 1, 2, 4, 8• N = 12, 13, 14, 15, 16• N' = 16

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• CS = 0–3• CF = 0• HD = 0 (for F=2, 4, 8), 1 (for F=1)

Dynamic Downscaling Of System Parameters (L, N, and F)The Dynamic Downscaling of System Parameters (DDSP) feature enables you to dynamically downscalespecific JESD204B system parameters through the CSR, without having to recompile the FPGA.

The transport layer supports dynamic downscaling of parameters L, F, and N only. The supported M andS parameters are determined by the L, F, and N' parameters. Some parameters (for example, CS and N')do not have this capability in the transport layer. If you needs to change any of these parameters, youmust recompile the system.

You are advised to connect the power down channels to higher indexes and connect used channel at lowerlanes. Otherwise, you have to reroute the physical-used channels to lower lanes externally whenconnecting the IP core to the transport layer. For example, when L = 4 and csr_l = 8'd1 (which means twolanes out of four lanes are active), with lane 1 and lane 3 being powered down, connection from the MACto the transport layer for lane 0 remains. However, lane 1 is powered down while lane 2 is not powereddown. Thus, lane 2 output from the MAC should be rerouted to lane 1 data input of the transport layer.The data port for those power-down channels will be tied off within the transport layer.

The 16-bit N' data for F = 1 is formed through the data from 2 lanes. Thus, F = 1 is not supported for oddnumber of lanes, for example, when LMF = 128. In this case, you can only reconfigure from F = 8 to F = 4and F = 2 but not F = 1.

Relationship Between Frame Clock and Link ClockThe frame clock and link clock are synchronous.

The ratio of link_clk period to frame_clk period is given by this formula:

32 x L / M x S x N'

Table 5-8: txframe_clk and rxframe_clk Frequency for Different F Parameter Settings

For a given ftxlink (txlink_clk frequency) and frxlink (rxlink_clk frequency), the ftxframe (txframe_clk frequency) andfrxframe (rxframe_clk frequency) are derived from the formula listed in this table.

F Parameter ftxframe (txframe_clk frequency) frxframe (rxframe_clk frequency)

1 ftxlink x (4 / F1_FRAMECLK_DIV ) frxlink x (4 / F1_FRAMECLK_DIV )

2 ftxlink x (2 / F2_FRAMECLK_DIV ) frxlink x (2 / F2_FRAMECLK_DIV )

4 ftxlink frxlink

8 ftxlink / 2 frxlink / 2

Data Bit and Content Mapping SchemeOne major function of the transport layer is to arrange the data bits in a specific way between the Avalon-ST interface and the DLL in the JESD204B IP core.

Figure 5-2 shows the mapping scheme in the transport layer across various TX to RX interfaces for aspecific system configuration.

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Figure 5-2: Mapping of Data Bit and Content Across Various Interfaces (LMF = 112, N = 12, N' = 16, S =1, T represents the tail bits).

01234567891011

[0]

[0]

[1][2][3][4][5][6][7][8][9][10][11]

[0][1][2][3][4][5][6][7][8][9][10][11]

[0][1][2][3][4][5][6][7][8][9][10][11][0][1][2][3][4][5][6][7][8][9][10][11] TTT TTT

1213141516171819202122232425262728293031

2nd jesd204_tx_datain[11:0](Avalon-ST interface to Transport Layer)

2nd jesd204_tx_ctrlin[0](Avalon-ST interface to Transport Layer)

[0]

[0]

[0]

[0]

[0]

1st jesd204_tx_ctrlin[0](Avalon-ST interface to Transport Layer)

[0]1st jesd204_rx_ctrlout[0](Transport Layer to Avalon-ST Interface)

[0]2nd jesd204_rx_ctrlout[0](Transport Layer to Avalon-ST Interface)

[0][1][2][3][4][5][6][7][8][9][10][11]2nd jesd204_rx_dataout[11:0](Transport Layer to Avalon-ST Interface)

1st jesd204_tx_datain[11:0](Avalon-ST interface to Transport Layer)

[0][1][2][3][4][5][6][7][8][9][10][11]1st jesd204_rx_dataout[11:0](Transport Layer to Avalon-ST Interface)

Bit Position

TX to RX Channel

jesd204_tx_link_datain[31:0](Transport Layer to Data Link Layer)

[0][1][2][3][4][5][6][7][8][9][10][11][0][1][2][3][4][5][6][7][8][9][10][11] TTT TTTjesd204_rx_link_datain[31:0](Data Link Layer to Transport Layer)

TX PathThe assembler in the TX path consists of the tail bits dropping, assembling, and multiplexing blocks.

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Figure 5-3: TX Path Assembler Block Diagram

Tail BitsPadding Assembling Multiplexing

TX Control

jesd204_tx_link_datain[(L*32)-1:0]

Configuration Register Settings

jesd204_tx_link_early_ready

jesd204_tx_link_data_valid

jesd204_tx_link_error

txframe_clktxframe_rst_ntxlink_clktxlink_rst_n

Control Unit

JESD204B IP CoreData Link LayerData

BusDataBus

DataBus

DataBus

jesd204_tx_datain[DATA_BUS_WIDTH-1:0](1)

JESD204B Transport Layer TX Block

Interface withAvalon-ST

jesd204_tx_data_validjesd204_tx_data_ready

Interfaces with JESD204 IP CoreData Link Layer and Control Unit

Parameter L, M, F, N, N’,S,F1_FRAMECLK_DIV,F2_FRAMECLK_DIV

Note:1. The DATA_BUS_WIDTH value is the data input bus width size, which depends on the F and L parameter. bus_width=M*S*N F=(M*S*N_PRIME)/(8*L) M*S=(8*F*L)/N_PRIME bus_width=(8*F*L*N)/N_PRIME

• Tail bits padding block—pads incoming data (jesd204_tx_datain) with "0" if N < 16, so that thepadded data is 16 bits per sample.

• Assembling block—arranges the resulting data bits in a specific way according to the mapping scheme(refer to Figure 5-2).

• Multiplexing block—sends the multiplexed data to the DLL interface, determined by certain controlsignals from the TX control block.

Table 5-9: Assembler Parameter Settings

Parameter Description Value

L Number of lanes per converter device. 1–8

F Number of octets per frame. 1, 2, 4, 8

CS Number of control bits or conversion sample. 0–3

N Number of conversion bits per converter. 12-16

N' Number of transmitted bits per sample in the user data format. 16

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F1_FRAMECLK_DIV

Only applies to cases where F=1.

The divider ratio on the frame_clk. The assembler always use thepost-divided frame_clk (txframe_clk). (33)

1, 4

F2_FRAMECLK_DIV

Only applies to cases where F=2.

The divider ratio on the frame_clk. The assembler always use thepost-divided frame_clk (txframe_clk). (33)

1, 2

RECONFIG_EN Enable reconfiguration support in the transport layer. Onlydownscaling reconfiguration is supported. Disable the reconfigurationto reduce the logic.

0, 1

DATA_BUS_WIDTH

The data input bus width size that depends on the F and L.

bus_width = M*S*N

F = (M*S*N_PRIME)/(8*L)

M*S = (8*F*L)/N_PRIME

Therefore the data bus width = (8*F*L*N)/N_PRIME

(8*F*L*N)/N_PRIME

CONTROL_BUS_WIDTH

The control output bus width size. The width depends on the CSparameter as well as the M and S parameters. When CS is 0, thecontrol data is one bit wide (tie the signal to 0).

If CS = 0, the bus width = 1. Otherwise, the bus width = (OUTPUT_BUS_WIDTH/N*CS) while OUTPUT_BUS_WIDTH/N = M*S

OUTPUT_BUS_WIDTH/N*CS

Table 5-10: Assembler Signals

Signal Clock Domain Direction Description

Control Unit

txlink_clk — Input TX link clock signal. This clock is equal to the TXdata rate divided by 40. This clock is synchronousto the txframe_clk signal.

txframe_clk — Input TX frame clock used by the transport layer. Thefrequency is a function of parameters F, F1_FRAMECLK_DIV, F2_FRAMECLK_DIV andtxlink_clk.

This clock is synchronous to the txlink_clksignal.

(33) Refer to the Table 5-13 to set the desired frame clock frequency with different FRAMECLK_DIV and Fvalues.

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txlink_rst_n txlink_clk Input Reset for the TX link clock domain logic in theassembler. This reset is an active low signal andthe deassertion is synchronous to the rising-edgeof txlink_clk.

txframe_rst_n txframe_clk Input Reset for the TX frame clock domain logic in theassembler. This reset is an active low signal andthe deassertion is synchronous to the rising-edgeof txframe_clk.


Between Avalon- ST and Transport Layer

jesd204_tx_

datain[(DATA_BUS_

WIDTH)-1:0]

txframe_clk Input TX data from the Avalon-ST source interface.The source shall arrange the data in a specificorder, as illustrated in the cases listed in TX PathData Remapping section

jesd204_tx_

controlin[(CONTROL_

BUS_WIDTH)-1:0]

txframe_clk Input TX control data from the Avalon-ST sourceinterface. The source shall arrange the data in aspecific order, as illustrated in the cases listed in TX Path Data Remapping section

jesd204_tx_data_

valid

txframe_clk Input Indicates whether the data from the Avalon-STsource interface to the transport layer is valid orinvalid.


jesd204_tx_data_

readytxlink_clk Output Indicates that the transport layer is ready to

accept data from the Avalon-ST source interface.

• 0—transport layer is not ready to receive data• 1—transport layer is ready to receive data


Between Transport Layer and DLL


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jesd204_tx_link_

datain[(L*32)-1:0]txlink_clk Output Indicates transmitted data from the transport

layer to the DLL at txlink_clk clock rate, wherefour octets are packed into a 32-bit data width perlane. The data format is big endian. The tablebelow illustrates the data mapping for L = 4:

jesd204_tx_link_datain [x:y] Lane

[31:0] 0

[63:32] 1

[95:64] 2

[127:96] 3

Connect this signal to the TX DLL jesd204_tx_link_data[] input pin.

jesd204_tx_link_

data_validtxlink_clk Output Indicates whether the jesd204_tx_link_

datain[] is valid or invalid.

• 0—jesd204_tx_link_datain[] is invalid• 1—jesd204_tx_link_datain[] is valid

Connect this signal to the TX DLL jesd204_tx_link_valid input pin.

jesd204_tx_link_

early_ready (34)txlink_clk Input Indicates that the DLL requires valid data at the

subsequent implementation-specific duration.

Connect this signal to the TX DLL jesd204_tx_frame_ready output pin.

jesd204_tx_link_

errortxlink_clk Output Indicates an error at the Avalon-ST source

interface. Specifically, this signal is asserted whenjesd204_tx_data_valid = "0" while jesd204_tx_data_ready = "1". The DLL subsequentlyreports this error to the CSR block.

Connect this signal to the TX DLL jesd204_tx_frame_error input pin.


CSR in DLL

(34) If a JESD device of No Multiple-Converter Device Alignment, Single-Lane (NMCDA-SL) class is deployed,Altera recommends that you tie this input signal to "1".

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csr_l[4:0] (35) mgmt_clk Input Indicates the number of active lanes for the link.This 5-bit bus represents the L value in zero-based binary format. For example, if L = 1, thecsr_l[4:0] = "00000". This design examplesupports the following values:

• 00000• 00001• 00011• 00111

Any programmed value beyond the supportedrange may result in undeterminable behavior inthe transport layer. You must ensure that thecsr_l[4:0] value always matches the systemparameter L value when it is in static configura‐tion.

Runtime reconfiguration supports L fallback. Forstatic configuration, set the maximum L andreconfigure csr_l[] to a smaller value duringruntime. This transport layer only supportshigher index channels to be powered down. Tointerleave the de-commision channels, you needto modify the interface connection from the DLLto transport layer.

Connect this signal to the TX DLL csr_l[]output pin.

csr_f[7:0] (35) mgmt_clk Input Indicates the number of octets per frame. This 8-bit bus represents the F value in zero-basedbinary format. For example, if F = 2, the csr_f[7:0] = "00000001". This design examplesupports the following values:

• 00000000• 00000001• 00000011• 00000111

Any programmed value beyond the supportedrange may result in undeterminable behavior inthe transport layer. Ensure that the csr_f[7:0]value always matches the system parameter Fvalue when it is in static configuration. Connectthis signal to the TX DLL csr_f[] output pin.

(35) This signal should be static and valid before the deassertion of the link_rst_n and frame_rst_n signals.


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csr_n[4:0] (35) mgmt_clk Input Indicates the converter resolution. This 5-bit busrepresents the N value in zero-based binaryformat. For example, if N = 16, the csr_n[4:0] ="01111". This design example supports thefollowing values:

• 01011• 01100• 01101• 01110• 01111

Any programmed value beyond the supportedrange may result in undeterminable behavior inthe transport layer. You must ensure that thecsr_n[4:0] value always match the systemparameter N value.

Connect this signal to the TX DLL csr_n[]output pin.

TX Path OperationThe data transfer protocol between the Avalon-ST interface and the TX path transport layer is datatransfer with backpressure, where ready_latency = 0.

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Figure 5-4: TX Operation Behavior

This figure shows the data transmission for a system configuration of LMF = 112, N = N' = 16, S = 1.

Operation:

• Upon the deassertion of the txframe_rst_n signal, the jesd204_tx_link_early_ready signal fromthe DLL to the transport layer is asserted some time later, which activates the transport layer to startsampling the jesd204_tx_datain[15:0] signal from the Avalon-ST interface.

• Each sampled 16-bit data is first written in a FIFO with a depth of four.• Once the FIFO accumulates 32-bit data, the data is streamed to the DLL accordingly through the

jesd204_tx_link_datain[31:0] signal.• Finally, the jesd204_tx_link_early_ready and jesd204_tx_data_ready signals deassert because

the DLL has entered code group synchronization state in this scenario.

txframe_clk

txlink_clk

txframe_rst_n/txlink_rst_n

jesd204_tx_data_valid

jesd204_tx_link_early_ready/jesd204_tx_data_ready

jesd204_tx_datain[15:0]


jesd204_tx_link_datain[31:0]

junk

All 0s

d0[15:0] d1[15:0] d2[15:0] d3[15:0] d4[15:0] d5[15:0] d6[15:0] d7[15:0] d8[15:0] d9[15:0] d10[15:0]

d0[15:0]d1[15:0]

d2[15:0]d3[15:0]

d4[15:0]d5[15:0]

d6[15:0]d7[15:0]

d8[15:0]d9[15:0] All 0s

TX Data TransmissionThis section explains the data transmission behavior when there is a valid TX data out from the TL toDLL.

Upon the deassertion of txframe_rst_n signal, the link's jesd204_tx_link_early_ready signal equalsto "1". This setting activates the TL to start sampling jesd204_tx_datain signal from the Avalon-STinterface and transmits sampled data (jesd204_tx_link_datain) to the TX link. The TX link onlycaptures valid data from the TL when the jesd204_tx_link_ready signal equals to "1" (in user dataphase). This means all the data transmitted from the TL before jesd204_tx_link_ready signal equals to"1" are ignored.

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Figure 5-5: TX Data Transmission

Junk datain Valid Data

Junk Sampled Data Valid Data

txframe_clktxlink_clk

txframe_rst_ntxlink_rst_n

jesd204_tx_datavalid

TL.jesd204_tx_link_early_ready


LINK.jesd204_tx_link_ready


Figure 5-6: TX Data Transmission (For F = 8)

Junk datain Valid Data

Junk Sampled Data Valid Data

txlink_clk

txframe_rst_ntxlink_rst_n

jesd204_tx_datavalid

jesd204_tx_link_early_ready


LINK.jesd204_tx_link_ready


txframe_clk

T0 -->T1

When F = 8, the data latency for jesd204_tx_link_datain should always be in an even latency link_clk count to ensure that the first valid data capturedby the TX link is T0 data followed by T1 data.

TX Path Data RemappingThe JESD204B IP core implements the data transfer in big endian format.

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Figure below illustrates the converter sample to transceiver lane mapping operation in the transport layer.Each converter sample has N bits, M converters per ADC/DAC device, and S samples per converter (M)per frame clock cycle. The transport layer operates at full rate or FRAMECLK_DIV=1.

1. The application layer or user logic data path interfaces directly with the transport layer through theAvalon-ST data bus if the application layer operates in frame clock domain. If the application layeroperates at a different clock domain than the frame clock domain, add a FIFO for the clock domaincrossing.

2. You have to reorder the samples so that sample 0 of converter 0 is located at LSB of the Avalon-ST databus, followed by sample 1 of converter 0 (if S>1) or sample 0 of converter 1 (if S=1). The most signifi‐cant bits (MSB) of the Avalon-ST bus has a sample of S -1 of converter M-1. For example, if S=4 andM=4, the most significant bits will be occupied by sample 3 of converter 3.

3. In this example, there is no control word because CF=0. Control bits are added if CS>1. Depending onthe value of CS and N, the number of tail bits added is N'-N-CS. For example, N'=16, N=12 and CS=2,the number of tail bits added to form a nibble group (NG) is 2.

4. The JESD204B IP core implements the data transfer in big endian format. Data is reshuffled in bigendian format before crossing to the link clock domain through an adaptor.

5. The data is arranged so that the L0 is always on the right (LSB) in the data bus interfacing with theJESD204B IP core. In big endian implementation, the oldest data (F0) is placed at the MSB in L0. 32-bits or 4 octets of data are transferred to the IP core in one link clock cycle. For example of F=8, 2 linkclock cycles are needed to transfer all 8 octets to the IP core.

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Figure 5-7: User Data Format that Feeds into the Transport Layer and Output to the Link Layer

Converter Device, MxN bits, S Samples per Single Converter per Frame Cycle

MSB LSB

Converter 0,M0

Sample 0S0

Sample 1S1

Sample S - 1S[S - 1]

Converter i,Mi

Sample 0S0


Converter M - 1,M[M - 1]

Sample 0S0


M0S0 M0S1 M0S[S - 1] MiS0 MiS[S - 1] M[M - 1]S0 M[M - 1]S[S - 1]

M[M - 1]S[S - 1]

M[M - 1]S0 MiS[S - 1] MiS0 M0S[S - 1] M0S1 M0S0

Control bits Appended to Each Sample (CF = 0)

Word1,M0S1 + C1

Word0,M0S0 + C0

NG1,Word1 + T

NG0,Word0 + T

Octet F-2,F[F - 2]

Octet F-1,F[F - 1]

Octet 2,F2

Octet 3,F3

Octet 0,F0

Octet 1,F1

F0 F1 F2 F3 F[F - 2] F[F - 1]

Frame Clock to Link Clock Adaptor

F4 F5 F6 F7

F0 F1 F2 F3

Lane 0, L0

Altera JESD IP Core

Lane L - 1, L[L - 1]

Sample from the converter is N bits wide

The user reorders the data so that M0S0 is at the LSB and M[M - 1]S[S - 1] is at the MSB. Data out from the RX has tthe same orientation, M0S0 at the LSB.

Add the control bit

Add the tail bit toN’ = 16

The transport layer reshuffles the data in big endian format

F = 8 in this example2nd link clock

1st link clock32 bits of data per lane in the link clock domain is packed to the JESD204B IP core

This Region of the Transport LayerIs in the Frame Clock Domain

This Region of the Transport LayerIs in the Link Clock Domain

1

2

3

4

5

Application layer or user logic'sAvalon-ST data bus

The following tables show examples of data mapping for L=4, F=1, 2, 4, 8 and M*S=2, 4, 8, 16. Theconfigurations that the transport layer support are not limited to these examples.

Table 5-11: Data Mapping for F=1, L=4

F = 1

Supported Mand S

M*S=2 for F=1, L=4

F=1 supports either (case1: M=1, S=2) or (case2: M=2, S=1)



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F = 1

F1_FRAMCLK_DIV=1(36)

1st frameclkjesd204_tx_datain[31:0] ={F8F12, F0F4}

Case1: M=1, S=2 M0S0=F0F4,M0S1=F8F12

Case2: M=2, S=1 M0S0=F0F4,M1S0=F8F12

2nd frameclkjesd204_tx_datain[31:0] ={F9F13, F1F5}

Case1: M=1, S=2 M0S0=F1F5,M0S1=F9F13

Case2: M=2, S=1 M0S0=F1F5,M1S0=F9F13

3rd frameclkjesd204_tx_datain[31:0] ={F10F114, F2F6}

Case1: M=1, S=2 M0S0=F2F6,M0S1=F10F14

Case2: M=2, S=1 M0S0=F2F6,M1S0=F10F14

4th frameclkjesd204_tx_datain[31:0] ={F11F15, F3F7}

Case1: M=1, S=2 M0S0=F3F7,M0S1=F11F15

Case2: M=2, S=1 M0S0=F3F7,M1S0=F11F15

F1_FRAMCLK_DIV=4 (37)

jesd204_tx_datain[127:0] = {{F11F15, F3F7},{F10F114, F2F6},{F9F13, F1F5},{F8F12,F0F4}}

Lane L3 L2 L1 L0

Data Out {F12, F13, F14,F15}

{F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3}


F = 2

SupportedM and S

M*S=4 for F=2, L=4

F=2 supports either (case1: M=1, S=4), (case2: M=2, S=2) or (case3: M=4, S=1)

(36) The effective frame clock in the Transport Layer is 4x of the link clock.(37) The effective frame clock in the Transport Layer is same as the link clock.

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F = 2

F2_FRAMCLK_DIV=1

1st frameclk

jesd204_tx_datain[63:0] ={F12F13,F8F9,F4F5, F0F1}

Case1: M=1, S=4 M0S0=F0F1, M0S1=F4F5,M0S2=F8F9, M0S3=F12F13at

Case2: M=2, S=2 M0S0=F0F1, M0S1=F4F5,M1S0=F8F9, M1S1=F12F13


2nd frameclk

jesd204_tx_datain[63:0] ={F14F15,F10F11,F6F7, F2F3}

Case1: M=1, S=4 M0S0=F2F3, M0S1=F6F7,M0S2=F10F11,M0S3=F14F15



F2_FRAMCLK_DIV=2

jesd204_tx_datain[127:0] = {{F14F15, F10F11,F6F7, F2F3}, {F12F13, F8F9,F4F5, F0F1}}

Lane L3 L2 L1 L0

Data Out {F12, F13, F14, F15} {F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3}


F = 4

Supported Mand S

M*S=8 for F=4, L=4

F=4 supports either (case1: M=1, S=8), (case2: M=2, S=4), (case3: M=4, S=2) or (case4:M=8, S=1)

F=4

jesd204_tx_datain[127:0] ={F14F15,F12F13,F10F11,F8F9,F6F7,F4F5,F2F3,F0F1}

Case1: M=1, S=8 {M0S7, M0S6, M0S5, M0S4, M0S3, M0S2,M0S1, M0S0}




Lane L3 L2 L1 L0



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F = 4

Data Out {F12, F13, F14,F15}

{F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3}


F = 8

Supported Mand S

M*S=16 for F=8, L=4

F=8 supports either (case1: M=1, S=16), (case2: M=2, S=8), (case3: M=4, S=4), (case4:M=8, S=2) or (case5: M=16, S=1)

F=8 jesd204_tx_datain[255:0] ={{F3031,F28F29,F26F27,F24F25}, {F22F23,F20F21,F18F19,F16F17}, {F14F15,F12F13,F10F11,F8F9}, {F6F7,F4F5,F2F3,F0F1}}

Case1: M=1, S=16 {M0S15, M0S14, M0S13, M0S12, M0S11,M0S10, M0S9, M0S8, M0S7, M0S6, M0S5,M0S4, M0S3, M0S2, M0S1, M0S0}

Lane L3 L2 L1 L0

Data Out atlinkclk T0

{F24, F25, F26,F27}

{F16, F17, F18,F19}

{F8, F9, F10, F11} {F0, F1, F2, F3}

Data Out atlinkclk T1

{F28, F29, F30,F31}

{F20, F21, F22,F23}

{F12, F13, F14,F15}

{F4, F5, F6, F7}

TX Error Reporting

For TX path error reporting, the transport layer expects a valid stream of TX data from the Avalon-STinterface (indicated by jesd204_tx_data_valid signal = 1) as long as the jesd204_tx_data_readyremains asserted. If the jesd204_tx_data_valid signal unexpectedly deasserts during this stage, thetransport layer reports an error to the DLL by asserting the jesd204_tx_link_error signal anddeasserting the jesd204_tx_link_data_valid signal accordingly, as shown in the timing diagram below.

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Figure 5-8: TX Error Reporting

The jesd204_tx_data_valid signal deasserts for one frame_clk and cannot be sampled by the link_clk.

txframe_clk

txlink_clk

jesd204_tx_data_valid

jesd204_tx_data_ready


jesd204_tx_link_error

TX Latency

Table 5-15: TX Latency Associated with Different F and FRAMECLK_DIV Settings.

F FRAMECLK_DIV TX Latency

1 1 3 txframe_clk period.

• Maximum 5 txframe_clk period for byte 3• Minimum 2 txframe_clk period for byte 0

1 4 1 txframe_clk period

2 1 3 txframe_clk period.

• Maximum 4 txframe_clk period for byte 2 and byte 3• Minimum 3 txframe_clk period for byte 0 and byte 1


4 — 1 txframe_clk period


RX PathThe deassembler in the RX path consists of the tail bits dropping, deassembling, and multiplexing blocks.

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Figure 5-9: RX Path Assembler Block Diagram

Deassembling Multiplexing

RX Control

jesd204_rx_link_datain[(L*32)-1:0]jesd204_rx_link_data_validjesd204_rx_linkdata_ready

jesd204_rx_linkerrorConfiguration Register Settings

rxframe_clkrxframe_rst_n

rxlink_clkrxlink_rst_n

Control Unit

JESD204B IP Core Data Link Layer DataBus

DataBus

DataBus

DataBus

jesd204_rx_dataout[OUTPUT_BUS_WIDTH-1:0]

JESD204B Transport Layer RX Block

jesd204_rx_data_valid

jesd204_rx_data_ready

Interface withAvalon-ST

Interfaces with JESD204B IP CoreData Link Layer and Control Unit

Parameter L, M, F, N, N’,S,F1_FRAMECLK_DIV, F2_FRAMECLK_DIV

Tail BitsDropping

• Tail bit dropping block—drops padded tail bits in the incoming data (jesd204_rx_link_datain).• Deassembling block—rearranges the resulting data bits in a specific way according to the mapping

scheme (refer to Figure 5-2).• Multiplexing block—sends the multiplexed data to the Avalon-ST interface, determined by certain

control signals from the RX control block.

Table 5-16: Deassembler Parameter Settings


L Number of lanes per converter device. 1–8

F Number of octets per frame. 1, 2, 4, 8

CS Number of control bits or conversion sample. 0–3

N Number of conversion bits per converter. 12-16

N' Number of transmitted bits per sample in the user data format. 16

F1_FRAMECLK_DIV Only applies to cases where F=1.

The divider ratio on the frame_clk. The deassembler always uses thepost-divided frame_clk (rxframe_clk). (38)

1, 4

(38) Refer to the Table 5-13 to set the desired frame clock frequency with different FRAMECLK_DIV and Fparameter values.

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F2_FRAMECLK_DIV Only applies to cases where F=2.

The divider ratio on the frame_clk. The deassembler always uses thepost-divided frame_clk (rxframe_clk). (38)

1, 2

RECONFIG_EN Enable reconfiguration support in the transport layer. Onlydownscaling reconfiguration is supported. Disable the reconfigura‐tion to reduce the logic.

0, 1

OUTPUT_BUS_WIDTH

The data output bus width size that depends on the F and L.

bus_width = M*S*N

F = (M*S*N_PRIME)/(8*L)

M*S = (8*F*L)/N_PRIME

Therefore the output bus width = (8*F*L*N)/N_PRIME

(8*F*L*N)/N_PRIME

CONTROL_BUS_WIDTH

The control output bus width size. The width depends on the CSparameter as well as the M and S parameters. When CS is 0, thecontrol data is one bit wide (tie the signal to 0).

If CS = 0, the bus width = 1. Otherwise, the bus width = (OUTPUT_BUS_WIDTH/N*CS) while OUTPUT_BUS_WIDTH/N = M*S

OUTPUT_BUS_WIDTH/N*CS

Table 5-17: Deassembler Signals


Control Unit

rxlink_clk — Input RX link clock signal. This clock is equal to the RXdata rate divided by 40. This clock is synchronousto the rxframe_clk signal.

rxframe_clk — Input RX frame clock used by the deassembler. Thefrequency is a function of parameters F, F1_FRAMECLK_DIV, F2_FRAMECLK_DIV andrxlink_clk.

This clock is synchronous to the rxlink_clksignal.

rxlink_rst_n rxlink_clk Input Reset for the RX link clock domain logic in thedeassembler. This reset is an active low signal andthe deassertion is synchronous to the rising-edgeof rxlink_clk.

rxframe_rst_n rxframe_clk Input Reset for the RX frame clock domain logic in thedeassembler. This reset is an active low signal andthe deassertion is synchronous to the rising-edgeof rxframe_clk.

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Between Avalon- ST and Transport Layer

jesd204_rx_

dataout[(OUTPUT_BUS_

WIDTH)-1:0]

rxframe_clk Output RX data to the Avalon-ST source interface. Thetransport layer arranges the data in a specificorder, as illustrated in the cases listed in RX PathData Remapping section.

jesd204_rx_

controlout[CONTROL_

BUS_WIDTH -1:0]

rxframe_clk Output RX control data to the Avalon-ST sourceinterface. The transport layer arranges the data ina specific order, as illustrated in the cases listed in RX Path Data Remapping section.

jesd204_rx_data_

valid

rxframe_clk Output Indicates whether the data from the transportlayer to the Avalon-ST sink interface is valid orinvalid.


jesd204_rx_data_

readyrxframe_clk Input Indicates that the Avalon-ST sink interface is

ready to accept data from the transport layer.

• 0—Avalon-ST sink interface is not ready toreceive data

• 1—Avalon-ST sink interface is ready to receivedata


Between Transport Layer and DLL

jesd204_rx_link_

datain[(L*32)-1:0]rxlink_clk Input Indicates received data from the DLL to the

transport layer, where four octets are packed intoa 32-bit data width per lane. The data format isbig endian. The table below illustrates the datamapping for L = 4:

jesd204_rx_link_datain [x:y] Lane

[31:0] 0

[63:32] 1

[95:64] 2

[127:96] 3

Connect this signal to the RX DLL jesd204_rx_link_data[] output pin.


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jesd204_rx_link_

data_validrxlink_clk Input Indicates whether the jesd204_rx_link_

datain[] is valid or invalid.

• 0—jesd204_rx_link_datain[] is invalid• 1—jesd204_rx_link_datain[] is valid

Connect this signal to the RX DLL jesd204_rx_link_valid output pin.

jesd204_rx_link_

data_readyrxframe_clk Output Indicates that the transport layer is ready to

sample jesd204_rx_link_datain[].

• 0—transport layer is not ready to samplejesd204_rx_link_datain[]

• 1—transport layer starts sampling jesd204_rx_link_datain[] at the next clock cycle.

Connect this signal to the RX DLL jesd204_rx_link_ready input pin.

jesd204_rx_link_

errorrxlink_clk Output Indicates an empty data stream due to invalid

data. This signal is asserted high to indicate anerror at the Avalon-ST sink interface (forexample, when jesd204_rx_data_valid = "1"while jesd204_rx_data_ready = "0"). The DLLsubsequently reports this error to the CSR block.

Connect this signal to the RX DLL jesd204_rx_frame_error input pin.


CSR in DLL

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csr_l[4:0] (39) mgmt_clk Input Indicates the number of active lanes for the link.This 5-bit bus represents the L value in zero-based binary format. For example, if L = 1, thecsr_l[4:0] = "00000". This design examplesupports the following values:

• 00000• 00001• 00011• 00111

Any programmed value beyond the supportedrange may result in undeterminable behavior inthe transport layer. You must ensure that thecsr_l[4:0] value always match the systemparameter L value.

Runtime reconfiguration supports L fallback. Forstatic configuration, set the maximum L andreconfigure csr_l[] to a smaller value duringruntime. This transport layer only supportshigher index channels to be powered down. Tointerleave the de-commision channels, you needto modify the interface connection from the DLLto transport layer.

Connect this signal to the RX DLLcsr_l[]output pin.

(39) This signal should be static and valid before the deassertion of the link_rst_n and frame_rst_n signals.


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csr_f[7:0] (39) mgmt_clk Input Indicates the number of octets per frame. This 8-bit bus represents the F value in zero-basedbinary format. For example, if F = 2, the csr_f[7:0] = "00000001". This design examplesupports the following values:

• 00000000• 00000001• 00000011• 00000111

Any programmed value beyond the supportedrange may result in undeterminable behavior inthe transport layer. You must ensure that thecsr_f[7:0] value always match the systemparameter F value.

Connect this signal to the RX DLL csr_f[]output pin.

csr_n[4:0] (39) mgmt_clk Input Indicates the converter resolution. This 5-bit busrepresents the N value in zero-based binaryformat. For example, if N = 16, the csr_n[4:0] ="01111". This design example supports thefollowing values:

• 01011• 01100• 01101• 01110• 01111

Any programmed value beyond the supportedrange may result in undeterminable behavior inthe transport layer. You must ensure that thecsr_n[4:0] value always match the systemparameter N value.

Connect this signal to the RX DLL csr_n[]output pin.

RX Path Operation

The data transfer protocol between the Avalon-ST interface and the RX path transport layer is datatransfer without backpressure. Therefore, the sink shall always be ready to sample the incoming datawhenever data at the source is valid.

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Figure 5-10: RX Operation Behavior

This figure shows the data transmission for a system configuration of LMF = 112, N = 12, N' = 16, S =1.

Operation:

• Upon the deassertion of the rxframe_rst_n signal, the jesd204_rx_link_data_ready signal fromthe deassembler to the DLL is asserted at the next rxframe_clk.

• Subsequently, the DLL asserts the jesd204_rx_link_data_valid signal for the deassembler toactivate the f2_div1_cnt signal logic and to start sampling the jesd204_rx_link_datain[31:0]signal. (40)

• At the following rxframe_clk, the jesd204_rx_data_valid is asserted along with the multiplexedjesd204_rx_dataout[11:0] signal to stream data to the Avalon-ST interface.

• Finally, the DLL deasserts the jesd204_rx_link_data_valid signal when there is no more valid data.• The deassembler deactivates the f2_div1_cnt signal logic accordingly, and deasserts the

jesd204_rx_data_valid at the next rxframe_clk.

rxframe_clk

rxlink_clk

rxframe_rst_n

rxlink_rst_n

jesd204_rx_link_data_ready

jesd204_rx_link_data_valid

f2_div1_cnt

jesd204_rx_link_datain[31:0]

rxdata_mux_out[15:0]

jesd204_rx_crtlout[0]



junk xddcc bbaa

junk

junk

junk

xbbaa ddcc x4433 bbaa xddcc 4433

xddc xbba xbba xddc x443 xbba xddc x443

jesd204_rx_dataout[11:0] junk junkxddc xbba xbba xddc x443 xbba xddc x443

RX Data ReceptionThis section explains when there is a valid RX data out from the DLL to the TL to with scrambler enabled.

The MAC layer process the jesd204_rx_dataout signal once the TL asserts the jesd204_rx_data_validsignal. However, there are some data that should be discarded by the upper layer when the you enable thescrambler. This is because the initial unknown seed value within the scrambler can corrupt the very firsteight octets, which is the data for the first two link clock cycles. The data can be translated to the frame

(40) The f2_div1_cnt signal is internally generated in the RX control block to correctly stream data to theAvalon-ST interface.

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clock cycle depending on the F and FRAMECLK_DIV parameters selected based on the frame clock tolink clock relationship.

Figure 5-11: RX Data Reception

Junk

Scrambler Corrupted Data

JunkValid Data

All 0s All 0sValid Data

rxframe_clk

rxlink_clk

rxframe_rst_nrxlink_rst_n

jesd204_rx_link_datain[63:0]

jesd204_rx_link_data_valid

jesd204_rx_dataout[15:0]


Related InformationRelationship Between Frame Clock and Link Clock on page 5-16

RX Path Data RemappingThe JESD204B IP core implements the data transfer in big endian format.

The RX path data remapping is the reverse of TX path data remapping. Refer to Figure 5-7for the RXtransport layer remapping operation.

The following tables show examples of data mapping for L=4, F=1, 2, 4, 8 and M*S=2, 4, 8, 16. Theconfigurations that the transport layer support are not limited to these examples.


F = 1

Lane L3 L2 L1 L0

Data In {F12, F13, F14, F15} {F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3}

SupportedM and S

M*S=2 for F=1, L=4

F=1 supports either (case1: M=1, S=2) or (case2: M=2, S=1)

Assuming N=16, M0S0=jesd204_rx_dataout[15:0], M0S1/M1S0= jesd204_rx_dataout[31:16]

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F = 1

F1_FRAMCLK_DIV=1

1st frameclk

cnt=0 :

jesd204_rx_dataout[31:0] ={F8F12, F0F4}

Case1: M=1, S=2 M0S0=F0F4, M0S1=F8F12

Case2: M=2, S=1 M0S0=F0F4, M1S0=F8F12

2nd frameclk

cnt=1:


Case1: M=1, S=2 M0S0=F1F5, M0S1=F9F13

Case2: M=2, S=1 M0S0=F1F5, M1S0=F9F13

3rd frameclk

cnt=2:


Case1: M=1, S=2 M0S0=F2F6, M0S1=F10F14

Case2: M=2, S=1 M0S0=F2F6, M1S0=F10F14

4th frameclk

cnt=3:


Case1: M=1, S=2 M0S0=F3F7, M0S1=F11F15

Case2: M=2, S=1 M0S0=F3F7, M1S0=F11F15

F1_FRAMCLK_DIV=4

jesd204_rx_dataout[127:0] = {{F11F15, F3F7},{F10F114, F2F6},{F9F13, F1F5},{F8F12, F0F4}}


F = 2

Lane L3 L2 L1 L0

Data In {F12, F13, F14, F15} {F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3}

SupportedM and S

M*S=4 for F=2, L=4

F=2 supports either (case1: M=1, S=4), (case2: M=2, S=2) or (case3: M=4, S=1)

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F = 2

F2_FRAMCLK_DIV=1

1st frameclk

cnt=0:

jesd204_rx_dataout[63:0] ={F12F13,F8F9,F4F5, F0F1}




2nd frameclk

cnt=1:

jesd204_rx_dataout[63:0] ={F14F15,F10F11,F6F7, F2F3}




F2_FRAMCLK_DIV=2

jesd204_rx_dataout[127:0] = {{F14F15, F10F11,F6F7, F2F3}, {F12F13, F8F9,F4F5, F0F1}}


F = 4

Lane L3 L2 L1 L0

Data In {F12, F13, F14,F15}

{F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3}

Supported Mand S

M*S=8 for F=4, L=4

F=4 supports either (case1: M=1, S=8), (case2: M=2, S=4), (case3: M=4, S=2) or (case4:M=8, S=1)

F=4

jesd204_rx_dataout[127:0] ={F14F15,F12F13,F10F11,F8F9,F6F7,F4F5,F2F3,F0F1}





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F = 8

Lane L3 L2 L1 L0

Data In linkclkT0

{F24, F25, F26,F27}

{F16, F17, F18,F19}

{F8, F9, F10, F11} {F0, F1, F2, F3}

Data In linkclkT1

{F28, F29, F30,F31}

{F20, F21, F22,F23}

{F12, F13, F14,F15}

{F4, F5, F6, F7}

Supported Mand S

M*S=16 for F=8, L=4

F=8 supports either (case1: M=1, S=16), (case2: M=2, S=8), (case3: M=4, S=4), (case4:M=8, S=2) or (case5: M=16, S=1)

F=8 jesd204_rx_dataout[255:0] ={{F3031,F28F29,F26F27,F24F25},{F22F23,F20F21,F18F19,F16F17},{F14F15,F12F13,F10F11,F8F9},{F6F7,F4F5,F2F3,F0F1}}

Case1: M=1, S=16 {M0S15, M0S14, M0S13, M0S12, M0S11,M0S10, M0S9, M0S8, M0S7, M0S6, M0S5,M0S4, M0S3, M0S2, M0S1, M0S0}

RX Error Reporting

For RX path error reporting, the transport layer expects the AL to always be ready to sample the RX data(as indicated by the jesd204_rx_data_ready signal equal to "1") as long as the jesd204_rx_data_validremains asserted. If the jesd204_rx_data_ready signal unexpectedly deasserts, the transport layerreports the error to the DLL by asserting the jesd204_rx_link_error signal, as shown in the timingdiagram below.

Figure 5-12: RX Error Reporting

rxframe_clk

rxlink_clk

jesd204_rx_link_error



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RX Latency

The RX latency is defined as the time needed to fully transfer a 32-bit data in a lane(jesd204_rx_link_datain*) to the Avalon-ST interface (jesd204_rx_dataout*) when thejesd204_rx_link_data_valid signal equals to "1".

Table 5-22: RX Latency Associated with Different F and FRAMECLK_DIV Settings.

F FRAMECLK_DIV RX Latency

1 1 • Maximum 5 rxframe_clk period for byte 3• Minimum 2 rxframe_clk period for byte 0

1 4 2 rxframe_clk period

2 1 • Maximum 3 rxframe_clk period for byte 2 and byte 3• Minimum 2 rxframe_clk period for byte 0 and byte 1




Serial Port Interface (SPI)

An external converter device with a SPI allows you to configure the converter for specific functions oroperations through a structured register space provided inside the converter device. The SPI givesflexibility and customization, depending on the application. Addresses are accessed via the serial port andcan be written to or read from the port. The memory is organized into bytes that can be further dividedinto fields.

The SPI communicates using two data lines, a control line, and a synchronization clock. A single SPImaster can work with multiple slaves. The SPI core logic is synchronous to the clock input provided bythe Avalon-MM interface. When configured as a master, the core divides the Avalon-MM clock togenerate the SCLK output.

Figure 5-13: Serial Port Interface (24-bit) Timing Diagram

Figure shows the timing diagram of a 24-bit SPI transaction required by a typical external converterdevice.

R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0Don’t Care

Don’t Care Don’t Care

Don’t Care

SS_n

SCLK

SDIO

The first 16 bits are instruction data. The first bit in the stream is the read or write indicator bit. This bitgoes high to indicate a read request. W1 and W0 represent the number of data bytes to transfer for eithera read or write process. For implementation simplicity, W1 and W0 are always set at 0 in this design

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example. The subsequent 13 bits represent the starting address of the data sent. The last 8 bits are registerdata.

For a 32-bit SPI transaction, each SPI programming cycle needs to be preceded with a preselection byte.The preselection byte is typically used to forward the SPI command to the right destination. figure showsthe timing diagram of a 32-bit SPI transaction.

Figure 5-14: Serial Port Interface (32-bit) Timing Diagram

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0P7 P6 P5 P4 P3 P2 P1 P0 R/W W1 W0

8 Bit Pre-Selection 8 Bit Register Data16 Bit Instruction

SS_n

SCLK

SDIO

In this design example, the SPI core is configured as a 4-wire master protocol to control threeindependent SPI slaves—ADC, DAC, and clock devices. The width of the receive and transmit registersare configured at 32 bits. Data is sent in MSB-first mode in compliance with the converter device defaultpower up mode. The SPI clock (sclk) rate is configured at a frequency of the SPI input clock rate dividedby 5. If the SPI input clock rate is 100 MHz (in the mgmt_clock domain), the sclk rate is 20 MHz. If theexternal converter device's SPI interface is a 3-wire protocol without both MOSI (master output, slaveinput) and MISO (master input, slave output) lines but with a single DATAIO pin, you can use theALTIOBUF Megafunction IP core (configured with bidirectional buffer) with the SPI master to convertthe MOSI and MISO lines to a single DATAIO pin. The DATAIO pin can be dynamically reconfigured asMOSI by asserting the output enable (oe) signal or as MISO by deasserting the oe signal. For implementa‐tion simplicity, you can directly connect the master MOSI pin to the slave DATAIO pin if read transac‐tions are not required.

Related InformationI/O Buffer (ALTIOBUF) Megafunction User GuideMore information about configuring the ALTIOBUF Megafunction IP Core.

Control UnitThe control unit has access to the CSR interface of the JESD204B IP core duplex base core, PLLreconfiguration, transceiver reconfiguration controller, and SPI master. The control unit also serves as aclock and reset unit (CRU) for the design example.

The control unit replaces the software-based Nios II processor to perform device configuration andinitialization on the JESD204B duplex base core. This configuration and initialization process includes thetransceivers, transport layer, pattern generator and checker, external converters (ADC/DAC), and clockdevices over the SPI interface.

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http://www.altera.com/literature/ug/ug_altiobuf.pdf


Figure 5-15: Control Unit Process Flow

Power-Up and Reset

Assert Transceiver(user-triggered),

Frame, and CSR Reset

SPI Configuration

Assert Link, Frame, andCSR Reset

Deassert Transceiver Reset

Deassert CSR Reset, followed by Link and

Frame Reset

INIT Done

IDLE

Start Reconfiguration

Assert Link andFrame Transceiver Reset

SPI Reconfiguration

LMF Reconfiguration

PLL Reconfiguration

Transceiver Reconfiguration

Deassert Transceiver Reset

Deassert Link and FrameReset

Cleartx_err, rx_err0, and rx_err1

status registers

Reconfiguration Done

reconfig = 1’b1

Memory Block (ROM)The control unit is a finite state machine (FSM) that works with multiple memory blocks (ROMs).

Each ROM holds the configuration data required to configure the external converter or clock devices foreach SPI slave. A memory initialization file (MIF) contains the initial values for each address in thememory. Each memory block requires a separate file. You can create the MIF using the text editor tool inthe Quartus Prime software.

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Figure 5-16: Example of MIF Format and Content

-- MIF content for ADC

WIDTH=24; -- the size of data in bits DEPTH=8; -- the size of memory in wordsADDRESS_RADIX=UNS; -- the radix for address valuesDATA_RADIX=BIN; -- the radix for data values

CONTENT BEGIN 0 : 000000000101111100010101; -- write 0x15 to link control 1 register 0x5F to disable the lane 1 : 000000000101111001000100; -- write 0x44 to quick config register 0x5E for L=4, M=4 2 : 000000000110010011000000; -- write 0xC0 to DID register 0x64 3 : 000000000110111000000011; -- write 0x03 to parameter SCR/L register 0x6E to disable scrambler 4 : 000000000111000000001111; -- write 0x0F to parameter K register 0x70 for K=16 in base IP core 5 : 000000000000110100000100; -- write 0x04 to test mode register 0x0D for checkerboard test pattern 6 : 000000000101111100010100; -- write 0x14 to link control 1 register 0x5F to enable the lane 7 : 111111111111111111111111; -- indicates end of mif or end of programming sequenceEND;

The initial values for each address and sequence is defined based on the requirement of the externalconverter and clock devices. The example above is based on 24-bit SPI write-only programming.

The last word must not be a valid data and must be set to all 1's to indicate the end of the MIF orprogramming sequence. This is because each converter device may have a different number ofprogrammable registers and hence involves a different number of MIF words. In this design example,three ROMs are used by default for each external ADC, DAC, and clock devices. If either one of the deviceis not used, a single word MIF with all 1's can be created.

Note: The MIFs in this design example is an example for a particular converter device. You must definethe MIF content based on the requirement of the external converter devices.

Finite State Machine (FSM)

The steps below describe the FSM flow:

1. Initialize the SPI:

a. Perform a read transaction from the ROM on per word basis and write to the SPI master for SPIwrite transaction to the external SPI slave.

b. Perform a read transaction from the next ROM and perform the same SPI write transaction to nextSPI slave.

2. Initialize the JESD204B IP base core, transport layer, pattern generator, and pattern checker uponsuccessful initialization of the transceiver.

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System Parameters

Table 5-23: System Parameter Settings

This table lists the parameters exposed at the system level.Parameter Value (41) Default Description

LINK 1, 2 1 Number of JESD204B link. One link represent one JESD204Binstance.

L 1, 2, 4, 8 2 Number of lanes per converter device.

M 1, 2, 4, 8 2 Number of converters per device.

F 1, 2, 4, 8 2 Number of octets per frame.

S 1, 2 1 Number of transmitted samples per converter per frame.

N 12–16 16 Number of conversion bits per converter.

N' 16 16 Number of transmitted bits per sample in the user data format.

F1_FRAMECLK_DIV

1, 4 4 The divider ratio on frame_clk when F = 1. The transportlayer uses the post-divided frame_clk.

F2_FRAMECLK_DIV

1, 2 2 The divider ratio on frame_clk when F = 2. The transportlayer uses the post-divided frame_clk.

POLYNOMIAL_LENGTH

7, 9, 15, 23,31

7 Defines the polynomial length for the PRBS pattern generatorand checker, which is also the equivalent number of stages forthe shift register.

• If PRBS-7 is required, set this parameter to 7.• If PRBS-9 is required, set this parameter to 9.• If PRBS-15 is required, set this parameter to 15.• If PRBS-23 is required, set this parameter to 23.• If PRBS-31 is required, set this parameter to 31.

This parameter value must not be larger than N, which is theoutput data width of the PRBS pattern generator or converterresolution. If an N of 12-14 is required, PRBS-7 and PRBS-9 arethe only feasible options. If an N of 15-16 is required, PRBS-7,PRBS-9, and PRBS-15 are the only feasible options.

(41) Values supported or demonstrated by this design example.

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Parameter Value (41) Default Description

FEEDBACK_TAP 6, 5, 14, 18,28

6 Defines the feedback tap for the PRBS pattern generator andchecker. This is an intermediate stage that is XOR-ed with thelast stage to generate to next PRBS bit.


Table below lists the configuration that this design example supports. However, the design examplegenerated by the Qsys system is always fixed at a data rate of 6144 Mbps and a limited set of configurationas shown in the table below. If your setting in the Qsys parameter editor does not match one of the LMFand bonded mode parameter values in Table, the design example is generated with the default values ofLMF = 124.

Table 5-24: Static and Dynamic Reconfiguration Parameter Values Supported

Mode Link L M F ReferenceClock

FrameClock

LinkClock

F1_FRAMECLK_

DIV

F2_FRAMECLK_

DIV

Static

Bonded/Non-bonded 2 1 1 2 153.6 153.6 153.6 2
















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Mode Link L M F ReferenceClock

FrameClock

LinkClock

F1_FRAMECLK_

DIV

F2_FRAMECLK_

DIV





Dynamic Reconfiguration

Non-bonded 2 2 2 2 153.6 153.6 153.6 2

The following figures show the datapath of single and multiple JESD204B links.Figure 5-17: Datapath of A Single JESD204B Link

Pattern Generator

M = 1, S = 1, N = 16, FRAMECLK_DIV = 1

Pattern Checker

AssemblerLMF = 211, S = 1,

N = 16

DeassemblerLMF = 211, S = 1,

N = 16

TX Base CoreLMF = 211, S = 1,

N = 16

RX Base CoreLMF = 211, S = 1,

N = 16

DuplexSERDES

PHY

32

32

16

16

Avalon-ST

Avalon-ST

Avalon-ST

Avalon-ST

Transport Layer 0 JESD204B IP Duplex Core 0 (LMF = 211)

LINK 0

M = 1, S = 1, N = 16, FRAMECLK_DIV = 1

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Figure 5-18: Datapath of Multiple JESD204B Links

32

32

16

16

Avalon-ST

Avalon-ST

Avalon-ST

Avalon-ST

Transport Layer 0 JESD204B IP Duplex Core 0 (LMF = 112)

Pattern Generator 0

Pattern Checker 0


N = 16


N = 16


N = 16


N = 16

DuplexSERDES

PHY

32

32

16

16

Avalon-ST

Avalon-ST

Avalon-ST

Avalon-ST

Transport Layer 1

Pattern Generator 1

Pattern Checker 1


N = 16


N = 16


N = 16


N = 16

DuplexSERDES

PHY

LINK 0

LINK 1

M = 1, S = 1, N = 16, FRAMECLK_DIV = 1

M = 1, S = 1, N = 16, FRAMECLK_DIV = 1

M = 1, S = 1, N = 16, FRAMECLK_DIV = 1

M = 1, S = 1, N = 16, FRAMECLK_DIV = 1

JESD204B IP Duplex Core 1 (LMF = 112)

Run-Time ReconfigurationThe JESD204B IP core supports run-time reconfiguration for the LMF and data rate settings. The designexample only demonstrates the following set of configuration.

To generate the design example with run-time reconfiguration enabled, the LMF and bonding modeparameters must match the default value listed in the table below.

Table 5-25: Run-time Reconfiguration Demonstrated By The Design Example

Parameter Default Run-time Reconfiguration

LMF 222 112FRAMECLK_DIV 2 2Data Rate 6144 Mbps 3072 MbpsLink Clock 153.6 MHz 76.8 MHzFrame Clock 153.6 MHz 76.8 MHzBonding Mode Non-bonded Non-bonded

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System Interface Signals

Table 5-26: Interface Signals

Signal ClockDomain

Direction Description

Clocks and Resets

device_clk — Input Device clock signal from the external converter orclock device.

mgmt_clk — Input Management clock signal from the on-board 100MHz oscillator.

frame_clk — Output Internally generated clock. The Avalon-ST user datainput must be synchronized to this clock domain fornormal operation mode.

global_rst_n mgmt_clk Input Global reset signal from the push button. This reset isan active low signal and the deassertion of this signalis synchronous to the rising-edge of mgmt_clk.

Signal ClockDomain


JESD204B

tx_sysref[LINK-1:0] link_clk Input TX SYSREF signal for JESD204B Subclass 1implementation.

sync_n[LINK-1:0] link_clk Input Indicates a TX SYNC_N from the receiver. This is anactive low signal and is asserted 0 to indicate asynchronization request or error reporting.

mdev_sync_n[LINK-1:0] link_clk Input Indicates a multidevice synchronization request atthe TX path. Synchronize signal combination shouldbe done externally and then input to the JESD204BIP core through this signal. In a single link instancewhere multidevice synchronization is not needed,you need to tie this signal to the dev_sync_n signal.

alldev_lane_aligned link_clk Input Aligns all lanes for this device at the RX path.

For multidevice synchronization, multiplex all thedev_lane_aligned signals before connecting to thissignal pin.

For single device support, connect the dev_lane_aligned signal back to this signal.

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Signal ClockDomain


rx_sysref[LINK-1:0] link_clk Input RX SYSREF signal for JESD204B Subclass 1implementation.

tx_dev_sync_n[LINK-

1:0]

link_clk Output Indicates a clean synchronization request at the TXpath. This is an active low signal and is asserted 0 toindicate a synchronization request. The SYNC_Nsignal error reporting is masked out of this signal.This signal is also asserted during software-initiatedsynchronization.

dev_lane_

aligned[LINK-1:0]

link_clk Output Indicates that all lanes for this device are aligned atthe RX path.

rx_dev_sync_n[LINK-

1:0]

link_clk Output Indicates a SYNC_N to the transmitter. This is anactive low signal and is asserted 0 to indicate asynchronization request. Instead of reporting the linkerror through this signal, the JESD204B IP core usesthe jesd204_rx_int signal to indicate an interrupt.

Signal ClockDomain


SPI

miso sclk Input Output data from a slave to the input of the master.

mosi sclk Output Output data from the master to the inputs of theslaves.

sclk mgmt_clk Output Clock driven by the master to slaves, to synchronizethe data bits.

ss_n[2:0] sclk Output Active low select signal driven by the master toindividual slaves, to select the target slave. Defaults to3 bits.

Signal ClockDomain


Serial Data and Control

rx_serial_

data[LINK*L-1:0]— Input Differential high speed serial input data. The clock is

recovered from the serial data stream.

tx_serial_

data[LINK*L-1:0]

device_

clkOutput Differential high speed serial output data. The clock

is embedded in the serial data stream.

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Signal ClockDomain


rx_

seriallpbken[LINK*L-

1:0]

— Input Assert this signal to enable internal serial loopback inthe duplex transceiver.

Signal ClockDomain


User Request Control

reconfig mgmt_clk Input Active high reconfiguration request. Set this signal tostatic 0 during compile time if run time reconfigura‐tion is not required.

runtime_lmf mgmt_clk Input Reconfigure the LMF value at run-time. This valuemust be stable prior to assertion of the reconfigsignal.

• 0—Downscale to the LMF value stored in MIFfile.

• 1— Upscale back to maximum LMF value.

Assuming at compile time, the LMF configuration is222, set this signal to 0 to scale down the LMFconfiguration to 112. Set this signal to 1 to scale upthe LMF configuration back to 222.

runtime_datarate mgmt_clk Input Reconfigure the data rate at run-time. This valuemust be stable prior to assertion of reconfig signal.

• 0— Downscale to data rate setting stored in PLL,PHY, and clock MIF.

• 1— Upscale back to maximum data rate settingstored in PLL, PHY, and clock MIF.

Assuming the compile time data rate is 3.072 Gbps,set this signal to 0 to scale down the data rate to 1.536Gbps. Set this signal to 1 to scale up the data rateback to 3.072 Gbps.

cu_busy mgmt_clk Output Assert high to indicate that the control unit is busy.All reconfiguration input will be ignored when thissignal is high.

Signal ClockDomain


Avalon- ST User Data



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Signal ClockDomain


avst_usr_

din[(FRAMECLK_

DIV*LINK*M*S*N)-1:0]

frame_

clkInput TX data from the Avalon-ST source interface. The

source arranges the data in a specific order, asillustrated in the cases below:

Case 1: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M= 1, S =1, N = 16:

• avst_usr_din[15:0]

Case 2: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M= 2 (denoted by m0 and m1), S =1, N = 16:

• avst_usr_din[15:0] = m0[15:0]• avst_usr_din[31:16] = m1[15:0]

Case 3: If F1/F2_FRAMECLK_DIV =1, LINK = 2(denoted by link0 and link1), M = 1, S =1, N = 16:

• avst_usr_din[15:0] = link0• avst_usr_din[31:16] = link1

Case 4: If F1/F2_FRAMECLK_DIV =1, LINK = 2(denoted by link0 and link1), M = 2 (denoted by m0and m1), S =1, N = 16:

• avst_usr_din[15:0] = link0, m0[15:0]• avst_usr_din[31:16] = link0, m1[15:0]• avst_usr_din[47:32] = link1, m0[15:0]• avst_usr_din[63:48] = link1, m1[15:0]

avst_usr_din_valid frame_

clkInput Indicates whether the data from the Avalon-ST

source interface to the transport layer is valid orinvalid.


avst_usr_din_ready frame_

clkOutput Indicates that the transport layer is ready to accept

data from the Avalon-ST source interface.


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Signal ClockDomain


avst_usr_

dout[(FRAMECLK_

DIV*LINK*M*S*N)-1:0]

frame_

clkOutput RX data to the Avalon-ST sink interface. The

transport layer arranges the data in a specific order,as illustrated in the cases below:

Case 1: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M= 1, S =1, N = 16:

• avst_usr_dout[15:0]

Case 2: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M= 2 (denoted by m0 and m1), S =1, N = 16:

• avst_usr_dout[15:0] = m0[15:0]• avst_usr_dout[31:16] = m1[15:0]

Case 3: If F1/F2_FRAMECLK_DIV =1, LINK = 2(denoted by link0 and link1), M = 1, S =1, N = 16:

• avst_usr_dout[15:0] = link0• avst_usr_dout[31:16] = link1

Case 4: If F1/F2_FRAMECLK_DIV =1, LINK = 2(denoted by link0 and link1), M = 2 (denoted by m0and m1), S =1, N = 16:

• avst_usr_dout[15:0] = link0, m0[15:0]• avst_usr_dout[31:16] = link0, m1[15:0]• avst_usr_dout[47:32] = link1, m0[15:0]• avst_usr_dout[63:48] = link1, m1[15:0]

avst_usr_dout_valid frame_

clkOutput Indicates whether the data from the transport layer

to the Avalon-ST sink interface is valid or invalid.


avst_usr_dout_ready frame_

clk

Input Indicates that the Avalon-ST sink interface is readyto accept data from the transport layer.





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Signal ClockDomain


test_mode[3:0] frame_

clkInput Specifies the operation mode.

• 0000—Normal mode. The design example takesdata from the Avalon-ST source.

• 1000—Test mode. The design example generatesalternate checkerboard data pattern.

• 1001—Test mode. The design example generatesramp wave data pattern.

• 1010—Test mode. The design example generatesthe PRBS data pattern.

• Others—Reserved

Signal ClockDomain


Status

rx_is_lockedtodata

[LINK*L-1:0]

device_

clkOutput Asserted to indicate that the RX CDR PLL is locked

to the RX data and the RX CDR has changed fromLTR to LTD mode.

data_error [LINK-1:0] frame_

clkOutput Asserted to indicate that the pattern checker has

found a mismatch in the received data and theexpected data. One error signal per pattern checker.

jesd204_tx_int[LINK-

1:0]

link_clk Output Interrupt pin for the JESD204B IP core (TX). Theinterrupt signal is asserted when an error conditionor synchronization request is detected.

jesd204_rx_int[LINK-

1:0]

link_clk Output Interrupt pin for the JESD204B IP core (RX). Theinterrupt signal is asserted when an error conditionor synchronization request is detected.

Example Feature: Dynamic ReconfigurationThe JESD204B IP core design example demonstrates dynamic (run-time) reconfiguration of either theLMF or data rate, at any one time.

Dynamic Reconfiguration Operation

The dynamic reconfiguration feature implements various reconfiguration controller modules such as PLLreconfiguration, Transceiver Reconfiguration Controller, SPI master, and JESD204B IP core Avalon-MMslave. These modules connect to the control unit through the Avalon-MM interface. You can control thereconfiguration using the reconfig, runtime_lmf, and runtime_datarate input ports exposed at controlunit interface.

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Figure 5-19: Dynamic Reconfiguration Block Diagram (For 28 nm Device Families—Stratix V and ArriaV)

JESD204B IP Core (Duplex)

CSR PHY

PHY MIFROM

SPI Master

Clock MIFROM

DAC MIFROM

ADC MIFROM

JESD MIFROM

Control Unit

PLL MIFROM

PLLReconfiguration Avalon-MM Avalon-MM

TransceiverReconfiguration

Controller

Avalon-MM

Avalon-MMre

conf

ig

runt

ime_

lmf

runt

ime_

data

rate

cu_b

usy

Avalon-MM

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Figure 5-20: Dynamic Reconfiguration Block Diagram (For 20 nm Device Families—Arria 10)

JESD204B IP Core (Duplex)

CSR PHY

SPI Master

Clock MIFROM

DAC MIFROM

ADC MIFROM

JESD MIFROM

Control Unit

PLL MIFROM

PLLReconfiguration Avalon-MM Avalon-MM

Avalon-MM

reco

nfig

runt

ime_

lmf

runt

ime_

data

rate

cu_b

usy

Avalon-MM

PHY MIFROM

The MIF ROM content for maximum and downscale configuration:

• PLL MIF ROM—contains the PLL counter, charge pump, and bandwidth setting.• JESD MIF ROM—contains the LMF information.• PHY MIF ROM—contains the transceiver channel and PLL setting.• ADC MIF ROM—contains the ADC converter setting.• DAC MIF ROM—contains the DAC converter setting.• CLK MIF ROM—contains the device clock setting.

MIF ROM

You need to generate two MIF files for each reconfigurable IP core as shown in Figure 5-20 or Figure5-21, and merge them into a single MIF file for each IP core. The following section shows the MIF fileformat.

Core PLL

The MIF format is fixed by the PLL. You need to generate two PLLs with maximum and downscalesetting to get these two MIF files. Then, merge the files into one (core_pll.mif). Only the PLL withmaximum configuration is used in final compilation.

Maximum Configuration MIFWIDTH=32;DEPTH=92;

ADDRESS_RADIX=UNS;

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DATA_RADIX=BIN;

CONTENT BEGIN 0 : 00000000000000000000000000111110; -- START OF MIF 1 : 00000000000000000000000000000100; 2 : 00000000000000000000000100000001; 3 : 00000000000000000000000000000011;... 42 : 00000000000000000000000000000010; 43 : 00000000000000000000000000001000; 44 : 00000000000000000000000001000000; 45 : 00000000000000000000000000111111; -- END OF MIF

Downscale Configuration MIF

46 : 00000000000000000000000000111110; -- START OF MIF 47 : 00000000000000000000000000000100; 48 : 00000000000000000000000100000001; 49 : 00000000000000000000000000000011;... 88 : 00000000000000000000000000000010; 89 : 00000000000000000000000000001000; 90 : 00000000000000000000000001000000; 91 : 00000000000000000000000000111111; -- END OF MIFEND;

PHY (Stratix V and Arria V)

The MIF format is fixed by the PHY. You need to generate two JESD204B IP cores with maximum anddownscale setting. Then, compile each of the setting to get a total of four MIF files (two for TX PLL andtwo for channel MIF). Then, merge the files into one (phy.mif). Only the JESD204B IP cores withmaximum configuration is used in final compilation.

Maximum TX PLL Configuration MIFWIDTH=16;DEPTH=186;

ADDRESS_RADIX=UNS;DATA_RADIX=BIN;

CONTENT BEGIN 0 : 0000000000100001; -- Start of MIF opcode (TX_PLL, 6144Mbps) 1 : 0000000000100010;... 10 : 0011000000000000; 11 : 0000000000011111; -- End of MIF opcode

Maximum Channel Configuration MIF

12 : 0000000000100001; -- Start of MIF opcode (Channel, 6144Mbps) 13 : 0000000000000010;...

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[88..91] : 0000000000000000; 92 : 0000000000011111; -- End of MIF opcode

Downscale TX PLL Configuration MIF

93 : 0000000000100001; -- Start of MIF opcode (TX_PLL, 3072Mbps) 94 : 0000000000100010;... 103 : 0011000000000000; 104 : 0000000000011111; -- End of MIF opcode

Downscale Channel Configuration MIF

105 : 0000000000100001; -- Start of MIF opcode (Channel, 3072Mbps) 106 : 0000000000000010;... [181..184] : 0000000000000000; 185 : 0000000000011111; -- End of MIF opcodeEND;

PHY (Arria 10)

The MIF format is fixed by the PHY. You need to generate two JESD204B IP cores with maximum anddownscale setting. Then, compile each of the setting to get a total of four MIF files (two for TX PLL andtwo for channel MIF). Then, merge the files into two (xcvr_atx_pll_combined.mif andxcvr_cdr_combined.mif). Only the JESD204B IP cores with maximum configuration is used in finalcompilation.

xcvr_atx_pll_combined.mif

Maximum Configuration MIF

CONTENT BEGIN 00 : 102FF71; -- Start of MIF 01 : 103BF01; 02 : 1047F04; 03 : 1054700;... 10 : 11AFF00; 11 : 11CE020; 12 : 11DE020; 13 : 3FFFFFF; -- End of MIF


14 : 102FF71; -- Start of MIF 15 : 103BF01; 16 : 1047F04; 17 : 1054700;... 24 : 11AFF00; 25 : 11CE020; 26 : 11DE020;

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27 : 3FFFFFF; -- End of MIFEND;

xcvr_cdr_combined.mif

Maximum Configuration MIF

CONTENT BEGIN 00 : 006DF02; -- Start of MIF 01 : 007FF09; 02 : 008FF04; 03 : 00AFF01;... 76 : 173FF31; 77 : 1741F0C; 78 : 1753F13; 79 : 3FFFFFF; -- End of MIF


7A : 006DF02; -- Start of MIF 7B : 007FF09; 7C : 008FF04; 7D : 00AFF01;... F0 : 173FF31; F1 : 1741F0C; F2 : 1753F13; F3 : 3FFFFFF; -- End of MIFEND;

JESD

The current JESD MIF contains only the LMF information. You need to manually code the MIF contentin the following format.



CONTENT BEGIN 0 : 0000000000000001; -- L (maximum config) 1 : 0000000000000001; -- M 2 : 0000000000000001; -- F... 3 : 1111111111111111; -- End of MIF [4..7] : 0000000000000000;


8 : 0000000000000000; -- L (downscale config) 9 : 0000000000000000; -- M 10 : 0000000000000001; -- F.

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.

. 11 : 1111111111111111; -- End of MIF [12..15] : 0000000000000000; END;

ADC/DAC/CLK

The content for ADC/DAC/CLK MIF is vendor-specific. The general format for the MIF is as shownbelow, with each section terminated by all 1's.



CONTENT BEGIN 0 : 10000100000000000001000001111100; -- (Maximum Config) 1 : 10000100000000000001010000000101; 2 : 10000100000000000001011000000101; 3 : 10000100000000000001110000000010; ... 28 : 10000001000000001111111100000001; 29 : 10000001000000000101111100010100; 30 : 11111111111111111111111111111111; -- End of MIF [31..63] : 00000000000000000000000000000000;


64 : 10000100000000000001000001111100; -- (downscale config) 65 : 10000100000000000001010000000101; 66 : 10000100000000000001011000000101; 67 : 10000100000000000001110000000010;... 92 : 10000001000000001111111100000001; 93 : 10000001000000000101111100010100; 94 : 11111111111111111111111111111111; -- End of MIF 95..127] : 00000000000000000000000000000000;END;

Generating and Simulating the Design ExampleTo use the JESD204B IP core design example testbench, follow these steps:

1. Generate the design example simulation testbench. Refer to Generating the Design ExampleSimulation Model on page 5-63

2. Simulate the design example using simulator-specific scripts. Refer to Simulating the JESD204B IPCore Design Example on page 5-63


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Generating the Design Example Simulation Model

After generating the IP core, generate the design example simulation testbench using the script(gen_ed_sim_verilog.tcl or gen_ed_sim_vhdl) located in the <example_design_directory>/ed_sim directory.

Note: For more information about the JESD204B design example testbench, refer to the README_DESIGN_EXAMPLE.txt file located in the <example_design_directory>/ed_sim folder.


1. Launch the Quartus Prime software.2. On the View menu, click Utility Windows and select Tcl Console.3. In the Tcl Console, type cd <example_design_directory>/ed_sim to go to the specified

directory.4. Type source gen_ed_sim_verilog.tcl (Verilog) or source gen_ed_sim_vhdl.tcl

(VHDL) to generate the simulation files.


1. Obtain the Quartus Prime software resource.2. Type cd <example_design_directory>/ed_sim to go to the specified directory.3. Type quartus_sh -t gen_ed_sim_verilog.tcl (Verilog) or quartus_sh -t

gen_ed_sim_vhdl.tcl (VHDL) to generate the simulation files.

Simulating the JESD204B IP Core Design Example

By default, the Quartus Prime software generates simulator-specific scripts containing commands tocompile, elaborate, and simulate Altera IP models and simulation model library files. You can copy thecommands into your simulation testbench script, or edit these files to add commands for compiling,elaborating, and simulating your design and testbench.

To simulate the design using the ModelSim-Altera SE/AE simulator, follow these steps:

1. Start the ModelSim-Altera simulator.2. On the File menu, click Change Directory > Select <example_design_directory>/ed_sim/testbench/

mentor.3. On the File menu, click Load > Macro file. Select run_tb_top.tcl. This file compiles the design and

runs the simulation automatically, providing a pass/fail indication on completion.

To simulate the design using the VCS MX simulator (in Linux), follow these steps:

1. Start the VCS MX simulator.2. On the File menu, click Change Directory > Select <example_design_directory>/ed_sim/testbench/

synopsys/vcsmx.3. Run run_tb_top.sh. This file compiles the design and runs the simulation automatically, providing a

pass/fail indication on completion.

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To simulate the design using the Aldec Riviera-PRO simulator, follow these steps:

1. Start the Aldec Riviera-PRO simulator.2. On the File menu, click Change Directory > Select <example_design_directory>/ed_sim/testbench/

aldec.3. On the Tools menu, click Execute Macro. Select run_tb_top.tcl. This file compiles the design and

runs the simulation automatically, providing a pass/fail indication on completion.

Generating the Design Example For CompilationUse the gen_quartus_synth.tcl script to generate the JESD204B design example for compilation.

Note: If you use the Tcl console in the Quartus Prime software to generate the gen_quartus_synth.tclscript, close all Quartus Prime project before you start generating the script.


1. Launch the Quartus Prime software.2. On the View menu, click Utility Windows and select Tcl Console.3. In the Tcl Console, type cd <example_design_directory>/ed_synth to go to the

specified directory.4. Type source gen_quartus_synth.tcl to generate the JESD204B design example for compila‐

tion.


1. Obtain the Quartus Prime software resource.2. Type cd <example_design_directory>/ed_synth to go to the specified directory.3. Type quartus_sh -t gen_ed_quartus_synth.tcl to generate the JESD204B design

example for compilation.


Compiling the JESD204B IP Core Design Example

You can use the generated .qip file to include relevant files into your project. Generate the Quartus Primesynthesis compilation files by running the script (gen_quartus_synth.tcl) located in the<example_design_directory>/ed_synth/ directory.

Note: If you use the Tcl console in the Quartus Prime software to generate the gen_quartus_synth.tclscript, close all Quartus Prime project before you start generating.

To compile your design using the Quartus Prime software , follow these steps:

1. Launch the Quartus Prime software.2. On the File menu, click Open Project > Select <example_design_directory>/ed_synth/example_design/.3. Select jesd204b_ed.qpf. (42)

4. On the Processing menu, click Start Compilation.

At the end of the compilation, the Quartus Prime software provides a pass/fail indication.

(42) This is the default quartus project file that the Quartus Prime software automatically generates. You can editthis file and the .qsf file according to your design preference.

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Design Example with Nios II Processor Control UnitThis design example with Nios II processor control unit provides an option if you need a software controlflow for your JESD204B system.

Generate this design by selecting the Nios II Control option in the Example Designs tab of the parametereditor. You can also generate a generic design by selecting the Generic Nios II Control option in theGenerate generic example design selection. This design example has the following key features:

• Supports Arria 10 devices only.• C-based software control flow implemented on a Nios II soft core processor.• Available as synthesizable design entity only.

Note: No simulation model is provided for this design. If you need a design example that has asimulation model, use the RTL State Machine Control design example.

Figure 5-21: Nios II Control Unit Design Example Block Diagram

PatternGenerator

Avalon-STUser Data

Avalon-ST User Data

Test PatternGenerator

Test PatternChecker

Top-Level Qsys Systemjesd204b_ed_qsys.qsys

Assembler(Transport

Layer)

Nios IISubsystem

Deassembler(Transport

Layer)

JESD204Subsystem

SPI

Core PLLframe_clk

frame_clk

device_clk

sysrefsync_n

SPI signals

tx_serial_data

rx_serial_data

link_clk

Top-Level RTL (jesd204b_ed.sv)

Core PLLReference Clock

TX/RXTransceiver PLLReference Clock

Avalon-ST

Avalon-ST

Avalon-ST 32 Bitper transceiver

lane


lane

mgmt_clk

global_rst_n

Design Example ComponentsThe Nios II processor control unit design example for the JESD204B IP core consists of the followingcomponents:

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• Qsys system

• JESD204B subsystem• Nios II subsystem• Core PLL• PLL reconfiguration controller• Serial Port Interface (SPI) – master module

• Test pattern generator• Test pattern checker• Assembler and deassembler (in the transport layer)

The following sections describe in detail the function of each component.

Qsys System Component

The Qsys system instantiates both the JESD204B IP core data path and the Nios II subsystem control path.

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Figure 5-22: Qsys System

Base Core PHY (HSSI)

TXCSR

RXCSRIRQ

ReconfigurationInterface

jesd204b_subsystem.qsys

JESD204B IP Core (Duplex)Serial Data To/FromExternal Converter

Avalon-MM BridgeReset

Sequencer

TransceivrReset Controller

ATX PLL

ReconfigurationInterface

Transceiver Reset

System Resets (1)

Transceiver Analog/Digital ResetsTX Serial Clock

PLL ReconfigurationController

Core PLL (2)C0

C1

Link Clock

Frame Clock

SPI Master

IRQ

IRQ

4-Wire SPI Signalto External ConverterSPI Interface

4

Core PLL ResetTo Nios II IRQ In

Avalon-MM Bridge

Avalon-MMBridgeNios II

IRQ In

On-ChipMemory

IRQPIO

JTAGUART

Timer

To/From Terminal Console

To Control RegistersFrom Status Registers

nios_subsystem.qsys

jesd204b_ed_qsys.qsys

Avalon Memory Mapped(Avalon-MM) Interconnect

Avalon Streaming(Avalon-ST) Interconnect

Interrupt Request SIgnals(IRQ)

Legend:

Notes:1. System resets comprise the following resets: Core PLL reset, JESD204B IP core SerDes PHY reset, TX/RX JESD204B IP core CSR resets, TX/RX link resets, TX/RX frame resets.2. The PLL takes the device clock from an external clock chip as the input reference. The PLL generates two output clocks (using two output counters from a single VCO). The clock from output counter C0 is the link clock for the transport and link layer. The clock from output counter C1 is the frame clock for the transport layer, pattern generator, and pattern checker.

Avalon-ST 32 Bit DataPer Transceiver LaneTo/From Transport layer

The top level Qsys system, jesd204b_ed_qsys.qsys, instantiates the following modules:

• JESD204B subsystem• Nios II subsystem• Core PLL• PLL reconfiguration controller• SPI master

The main data path flows through the JESD204B subsystem. In the example design, the JESD204B IP coreis configured in duplex mode with both TX and RX data paths. On the TX data path, user data flows from

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the transport layer through the JESD204B IP core base module via a 32-bit per transceiver lane AvalonStreaming (Avalon-ST) interface and out as serial data to the external converters via the JESD204B IP corePHY module. On the RX data path, serial data flows from the external converters (or from the TX datapath, in internal serial loopback mode) to the JESD204B IP core PHY module and out from the JESD204BIP core base module to the transport layer via a 32-bit per transceiver lane Avalon-ST interface.

The control path is centered on the Nios II processor in the Nios II subsystem and connects to variousperipherals via the Avalon Memory-Mapped (Avalon-MM) interface. A secondary control path from theSPI master module links out to the SPI configuration interface of external converters via a 4-wire SPIinterconnect. The configuration of the external converters is done by writing configuration data from theNios II processor to the SPI master module. The SPI master module handles the serial transfer of data tothe SPI interface on the converter end via the 4-wire SPI interconnect.

The core PLL generates the link clock and frame clock for the system. During a data rate dynamic reconfi‐guration process, the core PLL is dynamically reconfigurable at run time via the PLL reconfigurationcontroller.

To view the top level Qsys system in Qsys, follow these steps:

1. Launch the Quartus Prime software.2. On the File menu, click Open.3. Browse and select the jesd204b_ed_qsys.qsys file located in the project directory.4. Click Open to view the Qsys system.

You can access the address mapping of the submodules in the top level Qsys project by clicking on theAddress Map tab in the Qsys window.

Figure 5-23: Address Map View in Qsys

The Qsys system supports multi-link scenarios (up to 16 links) using the existing address map. To addmore links to the system, add more jesd204b_subsystem.qsys modules to the project, connect them to thejesd204b_subsystem Avalon-MM bridge, and adjust the address map accordingly. Bits 16-19 of thenios_subsystem-to-jesd204b_subsystem Avalon-MM bridge are reserved to support multi-links.

JESD204B Subsystem in Qsys

The JESD204B subsystem Qsys project, jesd204b_subsystem.qsys, instantiates the following modules:

• JESD204B IP core (altera_jesd204) configured in duplex, non-bonded mode (with TX and RXdatapaths)

• Reset sequencer (altera_reset_sequencer)• Transceiver PHY reset controller (altera_xcvr_reset_control)• ATX PLL (altera_xcvr_atx_pll_a10)• Avalon-MM bridge (altera_avalon_mm_bridge)

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The grouping of modules into a single Qsys subsystem project facilitates easy implementation of multi-link capabilities. For every link that you implement, a jesd204b_subsystem.qsys project is instantiated inthe top level Qsys project and assigned an address as described in the Address Map section of the QsysSystem section. Each link can be reset and dynamically reconfigured independently.

JESD204B IP Core

The generated example design is a self-contained system with its own JESD204B IP core. This IP core isseparate from the IP core that is generated from the IP tab. The example design JESD204B IP core isconfigured in duplex mode (with TX and RX data paths) and has the IP parameter settings as set whenyou generate the example design. The JESD204B IP base core and PHY layer connect to the Nios IIprocessor via the Avalon-MM interconnect. There are three separate Avalon-MM ports for the JESD204BIP core:

• Base core TX data path – For dynamic reconfiguration of the TX CSR parameters• Base core RX data path – For dynamic reconfiguration of the RX CSR parameters• PHY layer – For dynamic reconfiguration of transceiver PHY CSR (including data rate reconfigura‐

tion)

The Nios II processor writes to the JESD204B IP core CSR during a dynamic reconfiguration operation.By default, the software does not contain any dynamic reconfiguration features but you can use the Qsyssystem to implement such feature in the software.

Reset Sequencer

The reset sequencer is a standard Qsys component in the IP Catalog standard library. The reset sequencergenerates the following system resets to reset various modules in the system:

• Core PLL reset—resets the core PLL• Transceiver reset—resets the JESD204B IP core PHY module• TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP core CSRs• TX/RX link reset—resets the TX/RX JESD204B IP core base module and transport layer• TX/RX frame reset—resets the TX/RX transport layer, upstream and downstream modules

The reset sequencer has hard and soft reset options. The hard reset port connects to the global_rst_ninput pin in the top level design. The Nios II processor executes a soft reset by issuing the reset commandto the Avalon-MM interface of the reset sequencer. When you assert a hard reset or issue the relevantreset command via the Nios II processor, the reset sequencer cycles through all the various module resetsbased on a pre-set sequence. The figure below illustrates the sequence and also shows how the resetsequencer output ports correspond to the modules that are being reset.

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Figure 5-24: Reset Sequence

reset_in0

reset_out0

reset1_dsrt_qual

reset_out1

Qualifying Condition

reset2_dsrt_qual

reset_out2

reset_out5

reset_out3

reset_out4

reset5_dsrt_qual

reset_out7

reset_out6

Global Reset

Core PLL

Core PLL Locked

Transceiver PHY

TX Transceiver Ready

JESD204B TX CSR

JESD204B RX CSR

TX Link Layer

TX Frame Layer

RX Transceiver Ready

RX Frame Layer

RX Link Layer

Reset Type Reset SequencerOutput



Transceiver PHY Reset Controller

The transceiver PHY reset controller is a standard Qsys component in the IP Catalog standard library.This module takes the transceiver PHY reset output from the reset sequencer and generates the properanalog and digital reset sequencing for the transceiver PHY module.

ATX PLL

The ATX PLL is a standard Qsys component in the IP Catalog standard library. This module supplies alow-jitter serial clock to the Arria 10 transceiver PHY module. The reference clock input to the ATX PLLis the device_clk. The ATX PLL has an Avalon-MM interface that connects to the Nios II processor via theAvalon-MM interconnect and can receive configuration instructions from the Nios II processor. Bydefault, the software does not contain any dynamic reconfiguration features but you can use the Qsyssystem to implement such feature in the software.

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Avalon-MM Bridge

All the Avalon-MM submodules in the JESD204B subsystem are connected via Avalon-MM interconnectto a single Avalon-MM bridge. This bridge is the single interface for Avalon-MM communications intoand out of the subsystem.

JESD204B Subsystem Address Map

You can access the address map of the submodules in the JESD204B subsystem by clicking on theAddress Map tab in the Qsys window.

Table 5-27: JESD204B Subsystem Address Map

This table lists the memory allocation address map.Avalon-MM Peripheral Address Map

JESD204B IP core transceiver reconfigurationinterface

0x0000 – 0x3FFF

ATX PLL (up to 4 modules per link) 0x8000 – 0x8FFF (Module 0)

0x9000 – 0x9FFF (Module 1)

0xA000 – 0xAFFF (Module 2)

0xB000 – 0xBFFF (Module 3)

JESD204B IP core CSR – TX 0xC000 – 0xC3FF

JESD204B IP core CSR – RX 0xD000 – 0xD3FF

Reset sequencer 0xE000 – 0xE0FF

Related Information

• Quartus Prime Handbook Volume 1: Design and SynthesisFor detailed description of the reset sequencer module.

• Arria 10 Transceiver PHY User GuideFor detailed description of the transceiver PHY reset controller and ATX PLL.

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http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf

http://www.altera.com/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf


Nios II Subsystem in Qsys

The Nios II subsystem Qsys project, nios_subsystem.qsys, instantiates the following peripherals:

• Nios II processor (altera_nios2_gen2)• On-chip memory (altera_avalon_onchip_memory2)—provides both instruction and data memory

space• Timer (altera_avalon_timer)—provides a general timer function for the software• JTAG UART (altera_avalon_jtag_uart)—serves as the main communications portal between the user

and the Nios II processor via the terminal console in Nios II SBT for Eclipse tool• Avalon-MM bridges (altera_avalon_mm_bridge)—two Avalon-MM bridge modules; one to interface

to the JESD204B subsystem and the other to interface to the Qsys components (core PLL reconfigura‐tion controller and SPI master modules) in the top level Qsys project.

• PIO (altera_avalon_pio)—provides general input/output (I/O) access from the Nios II processor to theHDL components in the FPGA via two sets of 32-bit registers:

• io_status—status registers input from the HDL components to the Nios II processor• io_control—control registers output from the Nios II processor to the HDL components

The tables below describe the signal connectivity for the io_status and io_control registers.

Table 5-28: Signal Connectivity for io_status Registers

Bit Signal

0 Core PLL locked

1 TX transceiver ready (Link 0)

2 RX transceiver ready (Link 0)

3 Test pattern checker data error (Link 0)

4–31 TX transceiver ready, RX transceiver ready, and test pattern checker data error signalsfor subsequent links, if present.

Table 5-29: Signal Connectivity for io_control Registers

Bit Signal

0 RX serial loopback enable for lane 0 (Link 0)




4–30 RX serial loopback enable for subsequent links, if present.

31 Sysref (Not implemented in software)

You can access the address map of the submodules in the Nios II subsystem by clicking on the AddressMap tab in the Qsys window.

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Core PLLThe core PLL is an Arria 10 I/O PLL (altera_iopll) module that generates the clocks for the FPGA corefabric.

The core PLL uses the device_clk as its reference clock to generate two derivative clocks from a singleVCO:

• Link clock – from output C0• Frame clock – from output C1

Table 5-30: Clocks

Clock Formula Description

Link Clock Serial data rate/40 The link clock clocks the JESD204B IP corelink layer and the link interface of thetransport layer.

Frame Clock Serial data rate/(10 × F) The frame clock clocks the transport layer,test pattern generators and checkers, andany downstream modules in the FPGA corefabric.

For the frame clock, when F=1 and F=2, the resulting frame clock value can easily exceed the capability ofthe core PLL to generate and close timing. The top level RTL file (jesd204b_ed.sv) defines the frame clockdivision factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (forcases with F = 2). This factor enables the transport layer and test pattern generator to operate at a dividedfactor of the required frame clock rate by widening the data width accordingly. For this example design,the F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2. For example, the actual frameclock for a serial data rate of 6.144 Gbps and F = 1 is:

(6144/(10 × 1)) / F1_FRAMECLK_DIV = 614.4 / 4 = 153.6 MHz

PLL Reconfiguration ControllerThe PLL reconfiguration controller (altera_pll_reconfig) facilitates dynamic real-time reconfiguration ofthe core PLL.

You can use this IP core to update the output clock frequency, PLL bandwidth, and phase shifts in realtime, without reconfiguring the entire FPGA. The PLL reconfiguration controller connects to the Nios IIprocessor via the Avalon-MM interconnect. The Nios II processor sends dynamic reconfigurationinstructions to the controller during a dynamic data rate reconfiguration operation. By default, thesoftware does not contain any dynamic reconfiguration features but you can use the Qsys system toimplement such feature in the software.

Related Information

• AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Arria 10 DevicesMore details on implementing dynamic reconfiguration of the core PLL

• AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor AsControl UnitAn example of implementing a full-featured software control flow with various user commands in aJESD204B system that incorporates a Nios II processor

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https://documentation.altera.com/#/link/mcn1418200027274/mcn1418200318502/en-us

https://documentation.altera.com/#/link/bhc1423797291882/bhc1423797201068/en-us



• JESD204B Reference DesignAvailable design examples in Altera Design Store.

SPI MasterThe SPI master module (altera_avalon_spi) is a 4-wire, 24-bit width interface.

This module uses the SPI protocol to facilitate the configuration of external converters (for example,ADC, DAC, external clock modules) via a structured register space inside the converter device. The SPImaster module is connects to the Nios II processor via the Avalon-MM interconnect. By default, thesoftware does not contain any external converter configuration features but you can use the Qsys systemto implement the feature in the software.

For more details on the SPI master module, refer to chapter 5.

Transport LayerThe transport layer in the JESD204B IP core consists of an assembler at the TX path and a deassembler atthe RX path. The transport layer for both the TX and RX path is implemented in the top level RTL file,not in the Qsys project.

The transport layer provides the following services to the application layer (AL) and the DLL:

• The assembler at the TX path:

• maps the conversion samples from the AL (through the Avalon-ST interface) to a specific format ofnon-scrambled octets, before streaming them to the DLL.

• reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interfaceduring TX data streaming.

• The deassembler at the RX path:

• maps the descrambled octets from the DLL to a specific conversion sample format before streamingthem to the AL (through the Avalon-ST interface).

• reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interfaceduring RX data streaming.

The transport layer has many customization options and you may modify the transport layer RTL tocustomize it to your specifications. Furthermore, for certain parameters like L, F, and N, the transportlayer shares the CSR values with the JESD204B IP core. This means that any dynamic reconfigurationoperation that affects those values for the JESD204B IP core will affect the transport layer in the same way.By default, the software does not contain any dynamic reconfiguration features but you can use the Qsyssystem to implement such feature in the software.

For more details on the implementation of the transport layer in RTL and customization options, refer tochapter 5.

Test Pattern GeneratorThe test pattern generator generates one of three patterns; parallel PRBS, alternate checkerboard, or rampwave, and sends it along to the transport layer during test mode.

The test pattern generator has many customization options and you can modify the test pattern generatorRTL to customize it to your specifications. Furthermore, for certain parameters like M, S, N, and testmode, the test pattern generator shares the CSR values with the JESD204B IP core. This means that anydynamic reconfiguration operation that affects those values for the JESD204B IP core will affect the testpattern generator in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp)

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which is controlled by the test mode CSR. By default, the software does not contain any dynamic reconfi‐guration features but you can use the Qsys system to implement such feature in the software.

Note: The test pattern generator is implemented in the top level RTL file, not in the Qsys project.

Test Pattern Checker

The test pattern checker is implemented in the top level RTL file, not in the Qsys project. The test patternchecker checks one of three patterns; parallel PRBS, alternate checkerboard, or ramp wave from thetransport layer during test mode. The test pattern checker has many customization options and you maymodify the test pattern checker RTL to customize it to your specifications. Furthermore, for certainparameters like M, S, N, and test mode, the test pattern checker shares the CSR values with the JESD204BIP core. This means that any dynamic reconfiguration operation that affects those values for theJESD204B IP core will affect the test pattern generator in the same way. This includes the pattern type(PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR. By default, the softwaredoes not contain any dynamic reconfiguration features but you can use the Qsys system to implementsuch feature in the software.

System ClockingThe main reference clock for the design data path is the device_clk, which is supplied from an externalsource. The device_clk is the reference clock for the core PLL and the TX/RX transceiver referenceclocks. The core PLL generates the link_clk and frame_clk from the device_clk. The link_clk clocksthe JESD204B IP core link layer and link interface of the transport layer. The frame_clk clocks thetransport layer, test pattern generator and checker modules, and any downstream modules. The externalsource supplies a clock called the mgmt_clk to clock the control path of the design (the Nios II subsystemand any modules connected to the Nios II via the Avalon-MM bus interconnect).

Table 5-31: System Clocking for the Design Example

Clocks Description Source Modules Clocked

device_clk Reference clock for thedata path

— Core PLL, ATX PLL, RX transceiverPLL

link_clk Link layer clock device_clk JESD204B IP core link layer,transport layer link interface

frame_clk Frame layer clock device_clk Transport layer, test patterngenerator and checker, downstreammodules

mgmt_clk Control plane clock — Nios II subsystem and any modulesconnected to Nios II via Avalon-MMbus interconnect

Nios II Processor Design Example FilesThe design example is stored in the <your project>/ed_nios file directory. For the design example withNios II processor control unit, only the synthesis flow is available; simulation flow is not available.

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Table 5-32: Design Example Files

This table lists the important folders and files in the ed_nios file directory.File Type File/Folder Description

Quartus projectfiles

jesd204b_ed.qpf Quartus project file.

jesd204b_ed.qsf Quartus settings file.

output_files Folder containing output files from Quartus compilation (forexample, reports or sof)

Verilog HDLdesign files

jesd204b_ed.sv Top level HDL.

jesd204b_ed.sdc Synopsys Design Constraints (SDC) file containing all timing/placement constraints.

transport_layer Folder containing assembler and de-assembler HDL.pattern Folder containing the test pattern generator and checker HDL.spi_mosi_oe.v Output buffer RTL.switch_debouncer.v Switch debouncer RTL.

Qsys Projects

jesd204b_ed_qsys.qsys

Top level Qsys system project.

jesd204b_subsystem.qsys

JESD204B subsystem (refer to related information)

se_outbuf_1bit.qsys Output buffer module.se_outbuf_1bit Folder containing the output buffer module.

nios_subsystem.qsys Nios II subsystem (refer to related information)

jesd204b_ed_qsys Folder containing generated HDL files from jesd204b_ed_qsys.qsys.

*.sopcinfo Files containing system information for software projectbuilding (refer to related information) .

Software files software Folder containing all software-related files (detailed descriptionin the Software File Directory table).

There are two folders for the software files:

• jesd204_nios_ed—contains all user source and header files.• jesd204_nios_ed_bsp—board support package (BSP) that contains system files.

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Table 5-33: Software File Directory

File Type File Description

Header files(in jesd204_nios_ed folder)

altera_jesd204_qsys_regs.h

Offsets, masks, and bit position definitions for peripherals inQsys system that do not have standard access libraries. Thisincludes the following peripherals:

• JESD204B TX and RX CSR• Reset sequencer• PIO control• PIO status• Core PLL reconfiguration

main.h General user parameter definitions.

functions.h Contains function prototype definitions of sub-functions inmain.c.

macros.h Contains function prototype definitions of macro functions inmacros.c.

Source files (injesd204_nios_ed folder)

main.c Main C program. Also contain sub functions.

macros.c JESD204B Qsys system device access macros.

System files (injesd204_nios_ed_bsp folder)

system.h BSP-generated header file containing Qsys system-specificparameters such as:

• Peripheral base addresses• Interrupt controller IDs• IRQ priorities

Attention: Do not edit this auto-generated header file.

Related Information

• JESD204B Subsystem in Qsys on page 5-68• Nios II Subsystem in Qsys on page 5-72• Running the Software Control Flow on page 5-86

Nios II Processor Design Example System ParametersThe top level HDL file (jesd204b_ed.sv) includes system parameters that define the configuration of theexample design as a whole. You can change the values in the HDL file after generation to customize toyour desired configuration but the values must fall within the supported value ranges.

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Table 5-34: System Parameter

Parameter Value (43) Description

LINK 1, 2 Number of JESD204B link. One link represent one JESD204Binstance.

L 1, 2, 4, 8 Number of lanes per converter device.

M 1, 2, 4, 8 Number of converters per device.

F 1, 2, 4, 8 Number of octets per frame.

S 1, 2 Number of transmitted samples per converter per frame.

N 12–16 Number of conversion bits per converter.

N' 16 Number of transmitted bits per sample.

CS 0–3 Number of JESD204B control bits per conversion sample.

F1_FRAMECLK_DIV

1, 4 The divider ratio for frame_clk when F = 1 (refer to Core PLL onpage 5-73 section.

F2_FRAMECLK_DIV

1, 2 The divider ratio for frame_clk when F = 2 (refer to Core PLL onpage 5-73 section..

POLYNOMIAL_LENGTH

7, 9, 15, 23,31

Defines the polynomial length for the PRBS pattern generator andchecker, which is also the equivalent number of stages for the shiftregister.


This parameter value must not be larger than N, which is the outputdata width of the PRBS pattern generator or converter resolution. Ifan N of 12-14 is required, PRBS-7 and PRBS-9 are the only feasibleoptions. If an N of 15-16 is required, PRBS-7, PRBS-9, and PRBS-15are the only feasible options.

FEEDBACK_TAP 6, 5, 14, 18,28

Defines the feedback tap for the PRBS pattern generator and checker.This is an intermediate stage that is XOR-ed with the last stage togenerate to next PRBS bit.



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Nios II Processor Design Example System Interface Signals

Table 5-35: System Interface Signals

Signal ClockDomain


Clocks and Resets

device_clk — Input Reference clock for JESD204B data path.

mgmt_clk — Input Reference clock for Nios II processor control pathand all peripherals connected via Avalon-MMinterconnect.

sma_clkout — Output Clock output to SMA connector on board (for testonly).

global_rst_n mgmt_clk Input Global reset signal from the push button. This reset isan active low signal and the deassertion of this signalis synchronous to the rising-edge of mgmt_clk.

Signal ClockDomain


Serial Data

rx_serial_

data[LINK*L-1:0]

device_

clk

Input Differential high speed serial input data. The clock isrecovered from the serial data stream.

tx_serial_

data[LINK*L-1:0]

device_

clk

Output Differential high speed serial output data. The clockis embedded in the serial data stream.

Signal ClockDomain


JESD204B

sysref_out mgmt_clk Output SYSREF signal for JESD204B Subclass 1 implementa‐tion.

sync_n_out link_clk Output Indicates a SYNC_N from the receiver. This is an activelow signal and is asserted 0 to indicate a synchroniza‐tion request or error reporting.

Signal ClockDomain


Avalon- ST User Data

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Signal ClockDomain


avst_usr_din[LINK*

TL_DATA_BUS_WIDTH-

1:0]

frame_

clk

Input TX data from the Avalon-ST source interface. TheTL_DATA_BUS_WIDTH is determined by thefollowing formulas:

• If F = 1, TL_DATA_BUS_WIDTH = F1_FRAMECLK_DIV*8*1*L*N/N_PRIME


• If F = 4, TL_DATA_BUS_WIDTH = 8*4*L*N/N_PRIME


avst_usr_din_

valid[LINK-1:0]

frame_

clk

Input Indicates whether the data from the Avalon-STsource interface to the transport layer is valid orinvalid.


avst_usr_din_

ready[LINK-1:0]

frame_

clk

Output Indicates that the transport layer is ready to acceptdata from the Avalon-ST source interface.


avst_usr_dout[LINK*

TL_DATA_BUS_WIDTH-

1:0]

frame_

clk

Output RX data to the Avalon-ST sink interface. The TL_DATA_BUS_WIDTH is determined by the followingformulas:





avst_usr_dout_

valid[LINK-1:0]

frame_

clk

Output Indicates whether the data from the transport layerto the Avalon-ST sink interface is valid or invalid.


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Signal ClockDomain


avst_usr_dout_

ready[LINK-1:0]

frame_

clk

Input Indicates that the Avalon-ST sink interface is readyto accept data from the transport layer.



avst_patchk_data_

error [LINK-1:0]

frame_

clk

Output Output signal from pattern checker indicating apattern check error.

Signal ClockDomain


SPI

spi_MISO spi_SCLK Input Output data from a slave to the input of the master.

spi_MOSI spi_SCLK Output Output data from the master to the inputs of theslaves.

spi_SCLK mgmt_clk Output Clock driven by the master to slaves, to synchronizethe data bits.

spi_SS_n[2:0] spi_SCLK Output Active low select signal driven by the master toindividual slaves, to select the target slave. Defaults to3 bits.

Compiling the Design Example for SynthesisAfter generating the design example, all the necessary files for synthesis are stored in the <your project>/ed_nios directory.

To compile the design using the Quartus Prime software, follow these steps:

1. Launch the Quartus Prime software.2. On the File menu, click Open Project.3. Navigate to your project directory and select the Quartus project file (jesd204b_ed.qpf). Click Open.

The Quartus project is now open in the Project Navigator window. If required, you can modify theHDL files and Qsys projects to customize the design configurations to your specifications.

4. On the Processing menu, select Start Compilation to compile the HDL.The Quartus Prime software compiles the design and indicates the compilation status in the Taskswindow.


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Implementing the Design on the Development KitThe Target Development Kit option in the parameter editor window gives you the option to target theexample design to a development kit. For the Nios II processor design example, you can target the designto the Arria 10 GX FPGA Development Kit.

Note: The hardware example design targets an Arria 10 ES3 device (10AX115S3F45E2SGE3). It cannotfunction correctly on an Arria 10 production device.

When you select this target, the Quartus Settings File (jesd204b_ed.qsf) is updated with the followingchanges:

1. The target device is set to match the Arria 10 device on the Arria 10 GX FPGA development kit. Thedevice part number is 10AX115S3F45E2SGE3.

2. Pin assignments are added for selected signals listed in the Pin Assignments section.

Pin Assignments

The serial data (tx_serial_data [n] and rx_serial_data[n]) pin assignments are shown for the maximumnumber of transceiver lanes supported by the design example, which is L = 8. For other configurationswhere L < 8, a subset of the serial data pin assignments are selected.

Table 5-36: Top Level Interface Ports and its Corresponding Pin Assignments

The interface ports of the top level HDL file (jesd204b_ed.sv) with its corresponding FPGA pin assignments on theArria 10 FPGA development board are listed in the table below.

Interface Port Name FPGA PinNumber

I/O Standard Direction Board Source/Destination

global_rst_n T12 1.8 V Input User PB0 push-buttondevice_clk AN8 LVDS Input On-board Si5338

programmable oscillator(Output: CLK1B)

device_clk (n) AN7 LVDS Input On-board Si5338programmable oscillator

(Output: CLK1A)

mgmt_clk AR36 LVDS Input On-board Si570programmable oscillator(Output: 100 Mhz)

mgmt_clk(n) AR37 LVDS Input On-board Si570programmable oscillator(Output: 100 Mhz)

sma_clkout E24 1.8 V Output SMA clock outspi_MISO AR22 1.8 V Input FMC Port A connectorspi_MOSI AR11 1.8 V Output FMC Port A connectorspi_SCLK AT10 1.8 V Output FMC Port A connectorspi_SS_n[0] AV14 1.8 V Output FMC Port A connectortx_serial_data[7] AW3 High Speed Differential I/O Output FMC Port A connector

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tx_serial_data[7] (n) AW4 High Speed Differential I/O Output FMC Port A connectortx_serial_data[6] AY1 High Speed Differential I/O Output FMC Port A connectortx_serial_data[6] (n) AY2 High Speed Differential I/O Output FMC Port A connectortx_serial_data[5] BA3 High Speed Differential I/O Output FMC Port A connectortx_serial_data[5] (n) BA4 High Speed Differential I/O Output FMC Port A connectortx_serial_data[4] BB1 High Speed Differential I/O Output FMC Port A connectortx_serial_data[4] (n) BB2 High Speed Differential I/O Output FMC Port A connectortx_serial_data[3] BC3 High Speed Differential I/O Output FMC Port A connectortx_serial_data[3] (n) BC4 High Speed Differential I/O Output FMC Port A connectortx_serial_data[2] BB5 High Speed Differential I/O Output FMC Port A connectortx_serial_data[2] (n) BB6 High Speed Differential I/O Output FMC Port A connectortx_serial_data[1] BD5 High Speed Differential I/O Output FMC Port A connectortx_serial_data[1] (n) BD6 High Speed Differential I/O Output FMC Port A connectortx_serial_data[0] BC7 High Speed Differential I/O Output FMC Port A connectortx_serial_data[0] (n) BC8 High Speed Differential I/O Output FMC Port A connectorrx_serial_data[7] AM5 High Speed Differential I/O Input FMC Port A connectorrx_serial_data[7](n)

AM6 High Speed Differential I/O Input FMC Port A connector

rx_serial_data[6] AN3 High Speed Differential I/O Input FMC Port A connectorrx_serial_data[6](n)

AN4 High Speed Differential I/O Input FMC Port A connector

rx_serial_data[5] AP5 High Speed Differential I/O Input FMC Port A connectorrx_serial_data[5](n)

AP6 High Speed Differential I/O Input FMC Port A connector

rx_serial_data[4] AT5 High Speed Differential I/O Input FMC Port A connectorrx_serial_data[4](n)

AT6 High Speed Differential I/O Input FMC Port A connector

rx_serial_data[3] AV5 High Speed Differential I/O Input FMC Port A connectorrx_serial_data[3](n)

AV6 High Speed Differential I/O Input FMC Port A connector

rx_serial_data[2] AY5 High Speed Differential I/O Input FMC Port A connectorrx_serial_data[2](n)

AY6 High Speed Differential I/O Input FMC Port A connector

rx_serial_data[1] BA7 High Speed Differential I/O Input FMC Port A connector

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rx_serial_data[1](n)

BA8 High Speed Differential I/O Input FMC Port A connector

rx_serial_data[0] AW7 High Speed Differential I/O Input FMC Port A connectorrx_serial_data[0](n)

AW8 High Speed Differential I/O Input FMC Port A connector

sysref_out AV11 LVDS Output FMC Port A connectorsysref_out (n) AW11 LVDS Output FMC Port A connectorsync_n_out AN20 LVDS Output FMC Port A connectorsync_n_out (n) AP19 LVDS Output FMC Port A connector

Hardware SetupThe Arria 10 GX FPGA development board with a 10AX115 device features two FPGA mezzanine card(FMC) connectors for you to interoperate with external converters.

Figure 5-25: Block Diagram of the JESD204B Reference Design with Nios II Processor

This figure illustrates the example design block diagram implemented on the Arria 10 GX FPGA develop‐ment board.

global_rst_nPattern

Generator

Avalon-STUser Data

Avalon-ST User Data


Test PatternChecker


Assembler(Transport

Layer)

Nios IISubsystem


Layer)

JESD204Subsystem

SPI

Core PLLframe_clk

frame_clk

sync_n_outsysref_out

SPI signals (spi_MISO, spi_MOSI, spi_SCLK, spi_SS_n)

link_clk

Arria 10 Device (10AX115)


Si570 Oscillator100 MHz

Si5338 Oscillator

mgmt_clk

device_clk

Arria 10 FPGA Development Board

FMCPort A

Core PLLReference Clock

TX/RXTransceiver PLLReference Clock

Avalon-ST

Avalon-ST


lane


lane

tx_serial_data [n]

rx_serial_data [n]

The JESD204B serial data, control, and configuration signal pins are assigned to FMC port A connector.To interoperate with your converter device, ensure that the pin assignments for the JESD204B serial data,control, and configuration ports are set correctly according your converter specifications. The global reset

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pin (global_rst_n) connects to the user PB0 push-button on the board. The control plane clock(mgmt_clk) is sourced from the on-board Si570 programmable oscillator. The Si570 clock output routesthrough a Si53301 clock buffer that allows you to select between the Si570 clock output and SMA input.Follow the instructions in the Programming the Device section to set the board settings correctly.

The example design is configured in internal serial loopback mode. Therefore, the JESD204B data pathreference clock (device_clk) is sourced from an on-board clock source, the Si5338 programmableoscillator. In general, when interoperating with an external converter, the device_clk is sourced from theconverter through the FMC connector. If this suits your configuration, modify the device_clk pinassignments accordingly to assign the pin to the FMC connector.

Programming the Device

Follow the steps below to setup and program the device on the development board.

1. Connect the mini-USB programming cable from your workstation to the mini-USB connector (J3) onthe development board.

2. Connect the power adapter shipped with the development board to the power supply jack (J13).3. Turn on the power for the development board.4. To configure the clock frequency for the mgmt_clk that is sourced from the on-board Si570 program‐

mable oscillator (X3), use the Altera Clock Control GUI that is included with the development kit.Select the Si570 (X3) tab, enter the required target frequency in the Target frequency (MHz) box andclick Set New Frequency. The correct target frequency value is 100 MHz.You must set the CLK_SEL port of the Si53301 clock buffer module (U42) on the board to LOW toselect the Si570 clock output. To set the CLK_SEL signal to LOW, set switch 1 of DIPSWITCH5 (SW6)to the ON position. Refer to the Arria 10 GX FPGA development kit schematic and related documen‐tation for more details.

5. To configure the clock frequency for the device_clk that is sourced from the on-board Si5338programmable oscillator, use the Altera Clock Control GUI that is included with the development kit.Select the Si5338 (U14) tab, enter the required target frequency in the CLK1 box and click Set NewFreq. The correct target frequency value depends on the L parameter selected for the example design.Table below lists the required values for the device_clk, with the serial data rate set as 6.144 Gbps.

L Parameter Target Frequency (MHz)

8 307.2

Others 153.6

6. Compile the design as described in the Compiling Example Design For Synthesis section.7. In the Tools menu, click Programmer.8. In the Programmer window, click Add File.9. In the Select Programming File window, navigate to <your project>/ed_nios/output_files and select the

SOF programming file (jesd204b_ed.sof). Click Open.10.Verify that all the hardware setup options are set correctly to your system configurations.11.Click Start to program the file into the board device.

After programming the Arria 10 FPGA device on the development board, the system needs to be initial‐ized via software before the link is fully active. Follow the steps in the Executing the Software C Codesection to complete the link initialization process.

Attention: Do not skip this step. The JESD204B link will not function correctly without software linkinitialization.

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Related InformationExecuting the Software C Code on page 5-88

Running the Software Control FlowThe key feature of the design example with Nios II processor control unit is the ability to control certainaspects of JESD204B system using a C-based, software control flow.

The software control flow allows you to perform the following tasks:

• System reset – ability to reset individual modules (core PLL, transceiver PHY, JESD204B base Avalon-MM interface, link clock domain, and frame clock domain) independently or in sequence.

• Initial and dynamic, real-time configuration of external converter devices via SPI interface.• Dynamic reconfiguration of key modules in the design example subsystem (for example, JESD204B IP

core base layer, transceiver PHY, core PLL).• Error handling via interrupt service routines (ISR).• Status register readback.• Dynamic switching between real-time operation and test mode.

The software C code included as part of the design example only performs basic JESD204B link initializa‐tion. You can modify the code to perform some or all of the tasks above as per your system specifications.

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Figure 5-26: Software C Code Execution Flow

Figure illustrates the main C code execution flow

START

END

Complete Reset Sequence

Reset Link

Initialize ISR

Clear JESD204BError Status Register

Initialize JESD204B Link

Set Pattern Generator/Checker Pattern Type or

User Mode

Set Loopback Mode

Pulse Sysref

Wait 10 Seconds

Report Link Status

The JESD204B link initialization performs the following tasks:

• Set the pattern type or user mode for the pattern generator or checker. The default pattern type is set toPRBS.

• Set the loopback mode. The default is internal serial loopback mode.• Pulse SYSREF (required to meet Subclass 1 requirements)• Wait 10 seconds to allow for changes to take effect.• Report the link status.


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Executing the Software C Code

To execute the software code and initialize the JESD204B link:

1. Program the device on the board with the FPGA programming file as described in the Programmingthe Device on page 5-85 section.

2. In the Quartus Prime software, navigate to the Tools menu and select Nios II Software Build Toolsfor Eclipse.

3. In the Select a workspace dialog box, navigate to the software workspace, <your project>/ed_nios/software and click OK.

4. Create a new Nios II application and board support package (BSP) from the template. On the Filemenu, navigate to New and click Nios II Application and BSP From Template.

5. In the Nios II Application and BSP From Template window, enter the following information:

• SOPC Information File Name: <your project>/ed_nios/jesd204b_ed_qsys.sopcinfo

• Project name: jesd204_nios_ed (44)

• User default location: Checked• Templates: Blank Project

6. Click Next. Verify that the default BSP name is jesd204_nios_ed_bsp, then click Finish. The Nios IIapplication project (jesd204_nios_ed) and BSP (jesd204_nios_ed_bsp) appears in the Project Explorerwindow.

Note: Whenever you modify and recompile the Quartus project, you must regenerate the BSP files. Inthe Project Explorer window, right-click the jesd204_nios_ed_bsp project, navigate to Nios II andclick Generate. This regenerates the BSP files based on your most current compiled Quartusproject settings.

7. Import the design example source (*.c) and header (*.h) files into the application directory. In theProject Explorer window, right click on the jesd204_nios_ed project and click Import.

8. In the Import window, select General > File System as the import source. Click Next>.9. Browse to the <your project>/ed_nios/software/source directory. Check the source box on the left panel.

This selects all the source and header files in the source directory. Verify that the list of source andheader files are as follows:

• altera_jesd204_regs.h• functions.h• macros.h• main.h• macros.c• main.c

Verify that the destination folder is jesd204_nios_ed. Click Finish. All the source and header filesshould be imported into the jesd204_nios_ed project directory.

10.Right-click the jesd204_nios_ed_bsp project, navigate to Nios II and click BSP Editor. Under theDrivers tab, check the enable_small_driver box of the altera_avalon_jtag_uart_driver group and clickGenerate. This setting allows the compilation to proceed without connecting the interrupt ports of theJTAG UART module. After the BSP files have been generated, click Exit.

(44) You can choose any name for the project. This project name is given for reference purposes only.

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11.Expand the jesd204_nios_ed application project in the Project Explorer window and verify that thefolder contains all the source and header files.

12.To compile the C code, navigate to the Project menu and select Build All. The compiler now compilesthe C code into executable code.

13.To download the executable code to the development board, navigate to the Run menu and select RunConfigurations. In the Run Configurations window, double-click Nios II Hardware on the left panel.Check that all run configurations are correct, then click Run on the bottom right corner of thewindow.

The Quartus Prime software downloads the executable code onto the board and the Nios II processorexecutes the code. The code performs the JESD204B link initialization sequence and exits. You can viewthe code execution results on the Nios II Console tab.

All printf statements in the C code print to this console window. Similarly, all user input functions likegetc, gets, and scanf get user input from this console window. At the end of the initialization sequence,the code prints the JESD204B link status to the console. The following tables list the expected values of thelink status register report.

Table 5-37: TX Status 0 Register Bits

Bit Name Description Expected BinaryValue

[0] SYNC_N value 0: Receiver is not in sync

1: Link is in sync

1

[2:1] Data Link Layer (DLL)state

00: Code Group Synchronization (CGS)

01: Initial Lane Alignment Sequence (ILAS)

10: User Data Mode

11: D21.5 test mode

10

Table 5-38: RX Status 0 Register Bits

Bit Name Description Expected BinaryValue

[0] SYNC_N value 0 – Receiver is not in sync

1 – Link is in sync

1

Others — — Don’t care

The code also reports the status of the pattern checker. Any pattern checker errors that occur during theinitialization period is flagged in the console window.

Software ParametersThe software parameters defined in the main header file, main.h, controls various behaviors of the C code.

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Table 5-39: Software Parameters

Parameter DefaultValue

Description

DEBUG_MODE 0 Set to 1 to print debug messages, else set to 0.PRINT_INTERRUPT_MESSAGES

1 Set to 1 to print JESD204B error interrupt messages, else set to 0.

PATCHK_EN 1 Set to 1 when test pattern checker is included in the initial design datapath configuration, else set to 0.

DATAPATH 3 Set to indicate the JESD204B IP configuration:

1 – TX data path only.

2 – RX data path only.

3 – Duplex data path (TX and RX data path).

MAX_LINKS 1 Set to indicate the number of links in the design (for example, for duallink, set MAX_LINKS=2). See Implementing a Multi-Link Designsection for more detailed instructions on implementing multi-link usecase.

Note: When using the design as-is, the maximum value of MAX_LINKS is 16. To increase the limit, redesign the address mapin Qsys.

LOOPBACK_INIT 1 Initial value of the loopback. Set to 1 for internal serial loopback mode,else set to 0.

SOURCEDEST_INIT

PRBS Initial value of source/destination. Set to indicate test pattern generatoror checker type or user mode:

USER – User mode (no test pattern generator or checker in data path).

ALT – Test pattern generator or checker set in alternate checkerboardmode.

RAMP – Test pattern generator or checker set in ramp wave mode.

PRBS – Test pattern generator or checker set in parallel PRBS mode.

Software Interrupt Service Routines (ISR)One key feature of the Nios II processor control unit is the ability to handle interrupt requests (IRQ) fromperipherals through the software interrupt service routines (ISR).

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In this design example, the following peripherals have their IRQ output ports connected to the IRQ inputport of the Nios II processor:

• JESD204B IP core TX base layer• JESD204B IP core RX base layer• SPI master• Timer• Reset sequencer

The software C code included as part of the design example defines the ISRs for the following peripherals:

• JESD204B IP core TX base layer• JESD204B IP core RX base layer• SPI master

The ISRs in the C code is a basic routine that performs two tasks:

• Clear IRQ error flag• Print error type and message (for JESD204B IP core TX and RX base layer ISR only)

Error types and messages printed by the JESD204B IP core TX base layer ISR:

• SYNC_N error• SYSREF LMFC error• DLL data invalid error• Transport layer data invalid error• SYNC_N link reinitialization request• Transceiver PLL locked error• Phase compensation FIFO full error• Phase compensation FIFO empty error

Error types and messages printed by the JESD204B IP core RX base layer ISR:

• SYSREF LMFC error• DLL data ready error• Transport layer data ready error• Lane deskew error• RX locked to data error• Phase compensation FIFO full error• Phase compensation FIFO empty error• Code group synchronization error• Frame alignment error• Lane alignment error• Unexpected K character• Not in table error• Running disparity error• Initial Lane Alignment Sequence (ILAS) error• DLL error reserve status• ECC error corrected• ECC error fatal

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The error types correspond to the tx_err, rx_err0, and rx_err1 status registers in the JESD204B IP coreTX and RX register maps respectively. The PRINT_INTERRUPT_MESSAGES parameter in the main.hheader file controls the printing of interrupt error messages in the Nios II console window. Set theparameter to 1 (default) to print error messages, else set to 0. Refer to the Software Parameters section formore details. You can modify the ISRs in the C code to customize the interrupt handling response basedon your system specifications.

Related InformationSoftware Parameters on page 5-89

Software Functions DescriptionThe software C code provided with the design example performs basic JESD204B link initialization andexits.

This section describes the functions used in the main.c code and also the macros library that facilitatesaccess to the configuration and status registers (CSR) of the JESD204B design example system. Thesefunctions and macros provide the building blocks for you to customize the software code to your systemspecifications.

Functions in main.c Source File

The function prototypes of the sub functions listed in the table below can be found in the functions.hheader file located in the software folder.

Table 5-40: Functions in main.c

Function Prototype Description

int StringIsNumeric (

char *string)

Tests whether the string is numeric. Returns 1 if true, 0 if false.

void DelayCounter(

alt_u32 count)

Delay counter. Counts up to count ticks, each tick is roughly 1 second.

int Status (

char *options[][])

Executes report link status command according to the options. Returns0 if success, 1 if fail, 2 if sync errors found, 4 if pattern checker errorsfound, 6 if both sync errors and pattern checker errors found

int Loopback (

char *options[][],

int *held_resets,

int dnr)

Executes loopback command according to the options. Returns 0 ifsuccess, 1 if fail

int SourceDest (

char *options[][],

int *held_resets,

int dnr)

Executes source or destination datapath selection command accordingto the options. Returns 0 if success, 1 if fail

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int Test (

char *options[][],

int *held_resets)

Executes test mode command according to the options. Test mode:

• Set source/destination datapath selection to PRBS test patterngenerator or checker.

• Set transceiver to serial loopback mode.

Returns 0 if success, 1 if fail.

void Sysref (void) Pulse SYSREF signal one time (one-shot)void ResetHard (void) Triggers full hardware reset sequence through the PIO control

registers.

int ResetSeq (

int link,

int *held)

Performs full hardware reset sequence through the software interfaceon the indicated link. Returns 0 if success, 1 if fail.

int ResetForce (

int link,

int reset_val,

int hold_release,

int *held_resets)

Forces reset assertion or deassertion on submodule resets indicated byreset_val for the indicated link. The function also decides whether toassert and hold (hold_release=2), deassert (hold_release=1), or pulse(hold_release=0) the indicated resets. The function has mechanismsusing the global held_resets flag to ensure that held resets that arenot the target of the reset force function are not affected by it. Returns0 if success, 1 if fail.

int Reset_X_L_F_Release (

int link,

int *held_resets)

Deassert the transceiver, link, and frame resets. The function deassertsthe TX transceiver reset first, waits until the TX transceiver readysignal asserts, then deasserts the TX link and TX frame resets. Thefunction then repeats the above actions for the RX side. Returns 0 ifsuccess, 1 if fail.

void InitISR (void) Initializes the interrupt controllers for the following peripherals:

• JESD204B IP core TX CSR• JESD204B IP core RX CSR• SPI Master

The timer and JTAG UART interrupt controllers are disabled. Modifythe function to enable it. Refer to the Nios II Software Developer’sHandbook for more details on writing ISRs.

static void ISR_JESD_RX (

void * context)

JESD204B IP core RX ISR. Upon an interrupt event (IRQ asserted), thefunction reads the RX JESD204B CSR rx_err0 and rx_err1 registersand reports the error code. After that, the ISR clears all valid and activestatus registers in the rx_err0 and rx_err1 registers. Refer to the NiosII Software Developer’s Handbook for more details on writing ISRs.

static void ISR_JESD_TX (

void * context)

JESD204B IP core TX ISR. Upon an interrupt event (IRQ asserted), thefunction reads the TX JESD204B CSR tx_err registers and reports theerror code. After that, the ISR clears all the valid and active statusregisters in the tx_err registers. Refer to the Nios II SoftwareDeveloper’s Handbook for more details on writing ISRs.

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static void ISR_SPI (

void * context)

SPI Master interrupt service routine (ISR). Upon interrupt event (IRQassert), clears IRQ flag and return. Refer to the Nios II SoftwareDeveloper’s Handbook for more details on writing ISRs.

Custom Peripheral Access Macros in macros.c Source File

A set of peripheral access macros are provided for you to access specific information in the CSR of thefollowing peripherals:

• Reset sequencer• JESD204B TX• JESD204B RX• PIO control• PIO status• Transceiver Native PHY IP core• ATX PLL• Core PLL Reconfiguration

The function prototypes of the macros listed in the table below can be found in the macros.h header filelocated in the software folder.

Table 5-41: Custom Peripheral Access Macros in macros.c


int CALC_BASE_ADDRESS_LINK (intbase , int link)

Calculates and returns the base address based on the linkprovided. In the QSYS system (jesd204b_ed_qsys.qsys)address map, bits 16-19 are reserved for multi-linkaddressing. The address map allocation allows for up to amaximum of 16 links to be supported using the existingaddress map. The number of multi-links in the design isdefined by the MAX_LINKS parameter in the main.h headerfile. You are responsible to set the parameter correctly toreflect the system configuration.

int CALC_BASE_ADDRESS_XCVR_PLL(int base , int instance)

Calculates and returns the base address of the TXtransceiver PLL (ATX PLL) based on the instance number.In the JESD204B subsystem (jesd204b_subsystem.qsys)address map, bits 12-13 are reserved for multi ATX PLLaddressing. The address map allocation allows for up to amaximum of four ATX PLLs per link to be supported usingthe existing address map. The number of ATX PLLs per linkin the design is defined by the XCVR_PLL_PER_LINKparameter in the main.h header file. You are responsible toset the parameter correctly to reflect the system configura‐tion.

int IORD_RESET_SEQUENCER_STATUS_REG (int link)

Read reset sequencer status register at link and return thevalue.

int IORD_RESET_SEQUENCER_RESET_ACTIVE (int link)

Read reset sequencer status register at link and return 1 ifthe reset active signal is asserted, else return 0.

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void IOWR_RESET_SEQUENCER_INIT_RESET_SEQ (int link)

Write reset sequencer at link to trigger full hardware resetsequence.

void IOWR_RESET_SEQUENCER_FORCE_RESET (int link , int val)

Write reset sequencer at link to force assert or deassertresets based on the val value.

int IORD_JESD204_TX_STATUS0_REG(int link)

Read the JESD204B TX CSR tx_status0 register at link andreturn the value.

int IORD_JESD204_TX_SYNCN_SYSREF_CTRL_REG (int link)

Read the JESD204B TX CSR syncn_sysref_ctrl register atlink and return the value.

void IOWR_JESD204_TX_SYNCN_SYSREF_CTRL_REG (int link , int val)

Write val value into the JESD204B TX CSR syncn_sysref_ctrl register at link link.

int IORD_JESD204_TX_DLL_CTRL_REG(int link)

Read JESD204B TX CSR dll_ctrl register at link andreturn value.

void IOWR_JESD204_TX_DLL_CTRL_REG (int link , int val)

Write val value into the JESD204B TX CSR dll_ctrlregister at link.

int IORD_JESD204_RX_STATUS0_REG(int link)

Read JESD204B RX CSR rx_status0 register at link andreturn value.

int IORD_JESD204_RX_SYNCN_SYSREF_CTRL_REG (int link)

Read JESD204B RX CSR syncn_sysref_ctrl register atlink and return value.

void IOWR_JESD204_RX_SYNCN_SYSREF_CTRL_REG (int link, int val)

Write val value into the JESD204B RX CSR syncn_sysref_ctrl register at link.

int IORD_JESD204_TX_ILAS_DATA1_REG (int link)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the value.

int IORD_JESD204_RX_ILAS_DATA1_REG (int link)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the value.

void IOWR_JESD204_TX_ILAS_DATA1_REG (int link, int val)

Write val value into the JESD204B TX CSR ilas_data1register at link.

void IOWR_JESD204_RX_ILAS_DATA1_REG (int link, int val)

Write val value into the JESD204B RX CSR ilas_data1register at link.


Read the JESD204B TX CSR ilas_data2 register at link andreturn the value.


Read the JESD204B RX CSR ilas_data2 register at link andreturn the value.






Read the JESD204B TX CSR ilas_data12 register at linkand return the value.


Read the JESD204B RX CSR ilas_data12 register at linkand return the value.

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int IORD_JESD204_TX_GET_L_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the L value.

int IORD_JESD204_RX_GET_L_VAL (intlink)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the L value.

int IORD_JESD204_TX_GET_F_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the F value.

int IORD_JESD204_RX_GET_F_VAL (intlink)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the F value.

int IORD_JESD204_TX_GET_K_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the K value.

int IORD_JESD204_RX_GET_K_VAL (intlink)

Read JESD204B RX CSR ilas_data1 register at link linkand return K value.

int IORD_JESD204_TX_GET_M_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the M value.

int IORD_JESD204_RX_GET_M_VAL (intlink)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the M value.

int IORD_JESD204_TX_GET_N_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the N value.

int IORD_JESD204_RX_GET_N_VAL (intlink)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the N value.

int IORD_JESD204_TX_GET_NP_VAL(int link)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the NP value.

int IORD_JESD204_RX_GET_NP_VAL(int link)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the NP value.

int IORD_JESD204_TX_GET_S_VAL (intlink)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the S value.

int IORD_JESD204_RX_GET_S_VAL (intlink)

Read theJESD204B RX CSR ilas_data1 register at link andreturn the S value.

int IORD_JESD204_TX_GET_HD_VAL(int link)

Read the JESD204B TX CSR ilas_data1 register at link andreturn the HD value.

int IORD_JESD204_RX_GET_HD_VAL(int link)

Read the JESD204B RX CSR ilas_data1 register at link andreturn the HD value.

int IORD_JESD204_TX_LANE_CTRL_REG (int link, int offset)

Read the JESD204B TX CSR lane_ctrl_* register at linkand return the value.

int IORD_JESD204_RX_LANE_CTRL_REG (int link, int offset)

Read the JESD204B RX CSR lane_ctrl_* register at linkand return the value.

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void IOWR_JESD204_TX_LANE_CTRL_REG (int link, int offset, int val)

Write val value into the JESD204B TX CSR lane_ctrl_*register at link.

void IOWR_JESD204_RX_LANE_CTRL_REG (int link, int offset, int val)

Write val value into the JESD204B RX CSR lane_ctrl_*register at link.

int IORD_PIO_CONTROL_REG (void) Read the PIO control register and return the value.void IOWR_PIO_CONTROL_REG (intval)

Write val value into the PIO control register.

int IORD_PIO_STATUS_REG (void) Read the PIO status register and return thevalue.int IORD_JESD204_TX_TEST_MODE_REG (int link)

Read the JESD204B TX CSR tx_test register at link andreturn the value.

int IORD_JESD204_RX_TEST_MODE_REG (int link)

Read the JESD204B RX CSR rx_test register at link andreturn the value.

void IOWR_JESD204_TX_TEST_MODE_REG (int link, int val)

Write val value into the JESD204B TX CSR tx_test registerat link.

void IOWR_JESD204_RX_TEST_MODE_REG (int link, int val)

Write val value into the JESD204B RX CSR rx_test registerat link.

int IORD_JESD204_RX_ERR0_REG (intlink)

Read the JESD204B RX CSR rx_err0 register at link andreturn the value.

void IOWR_JESD204_RX_ERR0_REG (intlink, int val)

Write val value into the JESD204B RX CSR rx_err0 registerat link.

int IORD_JESD204_RX_ERR1_REG (intlink)

Read the JESD204B RX CSR rx_err1 register at link andreturn the value.

void IOWR_JESD204_RX_ERR1_REG (intlink, int val)

Write val value into the JESD204B RX CSR rx_err1 registerat link.

int IORD_JESD204_TX_ERR_REG (intlink)

Read the JESD204B TX CSR tx_err register at link andreturn the value.

void IOWR_JESD204_TX_ERR_REG (intlink, int val)

Write val value into the JESD204B TX CSR tx_err registerat link.

int IORD_JESD204_TX_ERR_EN_REG(int link)

Read the JESD204B TX CSR tx_err_enable register at linkand return the value.

void IOWR_JESD204_TX_ERR_EN_REG(int link, int val)

Write val value into the JESD204B TX CSR tx_err_enableregister at link.

int IORD_JESD204_RX_ERR_EN_REG(int link)

Read the JESD204B RX CSR rx_err_enable register at linkand return the value.

void IOWR_JESD204_RX_ERR_EN_REG(int link, int val)

Write val value into the JESD204B RX CSR rx_err_enableregister at link.

int IORD_XCVR_NATIVE_A10_REG (intlink, int offset)

Read the transceiver reconfiguration register at link andaddress offset at offset and return the value.

void IOWR_XCVR_NATIVE_A10_REG(int link, int offset, int val)

Write val value into the transceiver reconfiguration registerat link and address offset at offset.

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int IORD_XCVR_ATX_PLL_A10_REG(int link, int instance, int offset)

Read the ATX PLL reconfiguration register indicated by theinstance number instance at link and address offset at offsetand return the value.

void IOWR_XCVR_ATX_PLL_A10_REG(int link, int instance, int offset, int val)

Write val value into the ATX PLL reconfiguration registerindicated by instance number instance at link and addressoffset at offset.

int IORD_CORE_PLL_RECONFIG_C0_COUNTER_REG (void)

Read the core PLL reconfiguration C0 counter register andreturn the value.

int IORD_CORE_PLL_RECONFIG_C1_COUNTER_REG (void)

Read the core PLL reconfiguration C1 counter register andreturn the value.

void IOWR_CORE_PLL_RECONFIG_C0_COUNTER_REG (int val)

Write val value into the core PLL reconfiguration C0counter register.

void IOWR_CORE_PLL_RECONFIG_C1_COUNTER_REG (int val)

Write val value into the core PLL reconfiguration C1counter register.

void IOWR_CORE_PLL_RECONFIG_START_REG (int link)

Write to core PLL reconfiguration CSR to start the reconfi‐guration operation.

Related InformationAN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor AsControl UnitFor an example of a full-featured software C code that includes user command interface to executevarious features such as dynamic reconfiguration or external SPI configuration.

Customizing the Design ExampleUse the following guidelines if you want to customize the design example that you generate from the IPcore's parameter editor.

Modifying the JESD204B IP Core Parameters Post-GenerationIn the event that the design examples available does not suit your desired JESD204B IP parameterconfiguration, you can generate a generic example design and then manually modify the parameters tomeet your specifications.

1. Generate a generic design example with Nios II control unit.2. Open the top level Qsys system (jesd204b_ed_qsys.qsys) in Qsys.3. In the Qsys window, navigate to the File menu and click Open. Select jesd204b_subsystem.qsys and

click Open.4. In the System Contents tab, double-click the jesd204b module. This brings up the parameter editor

that shows the current parameter settings of the JESD204B IP core. This is the duplicate JESD204B IPcore that is generated in the design example folder, not the JESD204B IP core that is generated fromthe IP tab of the parameter editor, which is stored in a different folder.

5. Modify the IP core parameters of the jesd204b module as per your system specifications. When you aredone, navigate to the File menu and click Save.

6. In the File menu, click Open. Select the top level Qsys project, jesd204b_ed_qsys.qsys and click Open.

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https://documentation.altera.com/#/link/bhc1423797291882/bhc1423797201068

https://documentation.altera.com/#/link/bhc1423797291882/bhc1423797201068


7. Verify that the jesd204b_subsystem.qsys project has been updated with the new IP parameters for thejesd204b module. Right-click the jesd204b_subsystem_0 module and select Drill into subsystem. Thejesd204b_subsystem.qsys project opens in the Qsys window. In the System Contents tab, double-clickon the jesd204b module and verify that the parameters in the parameters tab match the ones that youhave updated earlier. When you are done verifying, click Move to the top of hierarchy to move backto the jesd204b_ed_qsys.qsys view.

8. Click Generate HDL to generate the HDL files needed for Quartus compilation.9. After the HDL generation is completed, click Finish to save your Qsys settings and exit the Qsys

window.10.You have to manually change the system parameters in the top level RTL file to match the parameters

that you set in the Qsys project, if applicable. Open the top level RTL file (jesd204b_ed.sv) in any texteditor of your choice.

11.Modify the system parameters at the top of the file to match the new JESD204B IP core settings in theQsys project, if applicable. Refer to the Nios II Processor Design Example System Parameters onpage 5-77 for more details on the system parameters.

12.Save the file and compile the design in Quartus Prime software as per the instructions in the Compiling the Design Example for Synthesis on page 5-81.

Changing the Data Rate or Reference Clock FrequencyWhen changing the data rate or reference clock frequency, be aware of the relationships between the serialdata rate, link clock, and frame clock as described in the Core PLL section and change the PLL outputclock settings accordingly to meet the clock frequency requirements.

Also be aware of the F1_FRAMECLK_DIV and F2_FRAMECLK_DIV frame clock division factorparameters for cases when F=1 or F=2. These parameters further divide down the frame clock frequencyrequirement so the resulting clock frequency is within bounds of the timing closure for the FPGA corefabric.

To change the serial data rate or reference clock frequency:

1. Open the jesd204b_subsystem.qsys project in the Qsys window.2. Double-click the jesd204b module to bring up the parameters editor for the JESD204B IP core.3. Change the Data rate and PLL/CDR Reference Clock Frequency values to meet your system require‐

ments.4. Double-click the xcvr_atx_pll_a10_0 module to bring up the parameters editor for the ATX PLL

module. This is the module that generates the serial clock for the TX transceiver PHY.5. Under the PLL subtab, locate the Output Frequency group and change the PLL output frequency and

PLL integer reference clock frequency values to meet your system requirements. Note that the PLLoutput frequency is half of the PLL output data rate as the clocking of the TX data is in DDR mode.Ensure that the data rate and PLL reference clock values match the parameters that were entered intothe jesd204b module.

6. Navigate back to the top level jesd204b_ed_qsys.qsys hierarchy.7. Double-click the core_pll module to bring up the parameters editor for the core PLL module.8. Under the PLL subtab, change the Reference Clock Frequency value in the General group to meet

your system requirements. Ensure that the reference clock frequency value matches the ones set for thejesd204b and xcvr_atx_pll_a10_0 modules. Also change the outclk0 group settings (which correspondto the link clock) and outclk1 group settings (which correspond to the frame clock) where necessary.Ensure that the link_clk and frame_clk values satisfy the frequency requirements as described in theCore PLL section.

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9. Click Generate HDL to generate the design files needed for Quartus Prime compilation.10.After the HDL generation is completed, click Finish to save your Qsys settings and exit the Qsys

window.11.If the frame clock settings (outclk1 of the core_pll module) are such that F1_FRAMECLK_DIV or

F2_FRAMECLK_DIV values are 1, change the relevant system parameters in the top level design file,jesd204b_ed.sv.

12.Save the file and compile the design.

Implementing a Multi-Link DesignThe design example Qsys projects, top level HDL file, and software C code are designed for easyimplementation of a JESD204B multi-link use case. In the Qsys projects, each link in a JESD204B multi-link use case corresponds to a single instantiation of the jesd204b_subsystem module, which includes theJESD204B IP core and other supporting modules. This section assumes that each jesd204b_subsystemmodule in the multi-link design has identical parameter configurations.

In the top level HDL file, each link in a JESD204B multi-link use case corresponds to an instantiation of atransport layer TX and RX pair and a pattern generator and checker pair (assuming duplex data pathconfiguration). The HDL file uses the Verilog generate statement using the system parameter LINK as anindex variable to generate the requisite number of instances for the multi-link use case. This sectionassumes that each transport layer TX and RX pair and pattern generator and checker pair in the multi-link design has identical parameter configurations. In the software C code, all software tasks are codedwith multi-link capabilities. The MAX_LINKS software parameter in the main.h header file defines thenumber of links in the design. In a multi-link scenario, each software action performs an identical task oneach link starting with link 0 and proceeding sequentially until the link indicated by the MAX_LINKSparameter.

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Figure 5-27: Multi-Link Use Case (Data Path Only) Block Diagram

PatternGenerator

Avalon-ST User Data(Link 0)





Test Pattern


Assembler(Transport

Layer)


Layer)

JESD204BSubsystem tx_serial_data (Link 0)

rx_serial_data (Link 0)

tx_serial_data (Link 1)

rx_serial_data (Link 1)


Avalon-ST

Avalon-ST


lane


lane

PatternGeneratorTest Pattern

Generator

Test Pattern

Assembler(Transport

Layer)


Layer)

JESD204BSubsystem

Avalon-ST

Avalon-ST


lane


lane

(Link 0)

(Link 1)

Checker

Checker

To implement a multi-link design, you need to perform these procedures:

1. Edit the Qsys project.2. Edit the top level HDL file.3. Edit the software C code.

The following sections describe these procedures in detail.

Editing the Qsys Project

1. Open the top level system, jesd204b_ed_qsys.qsys, in Qsys.2. Each JESD204B link is represented by a single jesd204b_subsystem instantiation. To implement multi-

links in Qsys, duplicate the jesd204b_subsystem instantiations. Right-click the jesd204b_subsystem_0module and select Duplicate. This duplicates the jesd204b_subsystem_0 module to a new modulecalled jesd204b_subsystem_1.

3. Connect the jesd204b_subsystem_1 ports as shown in the table below. Any ports not described in thetable below should be exported. To export a port, click the Double-click to export label in the Exportcolumn of the System Contents tab.

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Ports for jesd204b_subsystem_1 Module Connection

device_clk device_clk.clk

do_not_connect_reset_0 mgmt_clk.clk_reset



frame_clk frame_clk.clk

jesd204b_jesd204_rx_int nios_subsystem.nios2_d_irq

jesd204b_jesd204_tx_int nios_subsystem.nios2_d_irq

link_clk link_clk.clk

mgmt_clk mgmt_clk.clk

mgmt_reset reset_controller_0.reset_out

mm_bridge_s0 nios_subsystem.jesd204b_subsystem_mm_bridge_0_m0

reset_seq_irq nios_subsystem.nios2_d_irq

reset_seq_pll_reset (Do not connect)

reset_seq_reset_in0 reset_controller_0.reset_out

4. Adjust the interrupt priorities of the interrupt ports (jesd204b_jesd204_rx_int,jesd204b_jesd204_tx_int, and reset_seq_irq) in the new jesd204b_subsystem_1 module to meetyour system specifications. Click and edit the priority number of the relevant ports in the IRQ columnof the System Contents tab. The lower the priority number, the higher the priority.

5. Assign the address map of the jesd204b_subsystem_1 module in the Address Map tab. Bits 16-19 ofthe nios_subsystem-to-jesd204b_subsystem Avalon-MM bridge are reserved to support multi-links.Assign the address map according to the figure shown below. Bits 16-19 in the address map denotesthe link indicator. For subsequent links, increment the link indicator accordingly. The system cansupport up to 16 links.

Figure 5-28: Multi-Link Address Map

6. Repeat steps 2 – 5 for subsequent links in your design.7. Click Generate HDL to generate the design files needed for Quartus compilation.8. After the HDL generation is completed, click Finish to save your Qsys settings and exit the Qsys

window.

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Editing the Top Level HDL File

1. Open the top level HDL file (jesd204b_ed.sv) in any text editor.2. Modify the LINK system parameter to reflect the number of links in your design.3. Replace the single-link jesd204b_ed_qsys instance with the multi-link instance generated earlier as

shown in Editing the Qsys Project on page 5-101.4. Reconnect all the ports that are similar between the single-link jesd204b_ed_qsys instance and the

multi-link instance.5. The ports that are new in the multi-link jesd204b_ed_qsys instance are associated with the

jesd204b_subsystem_1 module. Connect the ports that have the jesd204b_subsystem_1_* prefix in thesame manner as shown below:

.jesd204b_subsystem_1_jesd204b_txlink_rst_n_reset_n(tx_link_rst_n[1])

6. Save the file and compile the design in the Quartus Prime software.

Ensure that any additional pins that are created from the addition of multi-links (for example,tx_serial_data and rx_serial_data pins) have proper pin assignments in the Quartus settings file (jesd204b_ed.qsf).

Editing the Software C Code

1. Open the main.h header file in the <your project>/ed_nios/software directory in any text editor.2. Change the MAX_LINKS parameter to match the number of links implemented in your design and

save the file.3. Compile and execute the C code as described in Executing the Software C Code on page 5-88.

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JESD204B IP Core Deterministic LatencyImplementation Guidelines 6

2015.11.02


Subclass 1 and Subclass 2 modes support deterministic latency. This section describes the featuresavailable in the JESD204B IP core that you can use to achieve Subclass 1 deterministic latency in yourdesign. This section also covers some best practices for Subclass 1 implementation like constraining theincoming SYSREF signal and maintaining deterministic latency during link reinitialization.

Features available:

• Programmable RBD offset.• Programmable LMFC offset.

Constraining Incoming SYSREF SignalThe SYSREF signal resets the LMFC counter in the IP core for subclass 1 implementation. Constrainingthe SYSREF signal ensures that the setup relationship between SYSREF and device clock is established.

The setup time is analyzed when you set the timing constraint for the SYSREF signal in the user .sdc file.When the setup time is met, the SYSREF signal detection by the IP core is deterministic; the number oflink clock cycles of SYSREF signal that arrives at the FPGA pin to the LMFC counter resets, is determin‐istic.

Apply the set_input_delay constraint on the SYSREF signal with respect to device clock in the user .sdcfile:

set_input_delay -clock <device clock name at FPGA pin> <sysref IO delay in ns> [get_ports <sysref name at FPGA pin >]

The SYSREF IO delay is the board trace length mismatch between device clock and SYSREF. For example:

set_input_delay -clock device_clk 0.5 [get_ports sysref]

The above statement constrains the FPGA SYSREF signal (sysref), with respect to the FPGA device clock(device_clk) pin. The trace length mismatch resulted in 500 ps or 0.5 ns difference in time arrival at theFPGA pins between SYSREF and device clock.

In most cases, the register in the IP core, which detects the SYSREF signal, is far away from the SYSREFI/O pin. The long interconnect routing delay results in timing violation. You are recommeded to usemulti-stages pipeline registers to close timing. Use the same clock domain as the JESD204B IP core'srxlink_clk and txlink_clk to clock the multi-stages pipeline registers.





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Figure 6-1: Multi-Stage Pipeline Register for SYSREF Signal

Figure shows a two stages pipeline registers for the SYSREF signal.

SYSREF at FPGA pin D Q D Q D Q

User logic:1st stage pipeline register

User logic:2nd stage pipeline register

To IP core internal logic

IP core register

rxlink_clk or txlink_clk

Programmable RBD OffsetIn the RX IP core, the programmable RBD offset provides flexibility for an early RBD release to optimizethe latency through the IP core. You can configure the RBD offset using the csr_rbd_offset field in thesyncn_sysref_ctrl register.

You should set a safe RBD offset value to ensure deterministic latency from one power cycle to anotherpower cycle. Follow these steps to set a safe RBD offset value:

1. Read the RBD count from the csr_rbd_count field in rx_status0 register. Record the value.2. Power cycle the JESD204B subsystem, which consists of the FPGA and converter devices.3. Read the RBD count again and record the value.4. Repeat steps 1 to 3 at least 5 times and record the RBD count values.5. Set the csr_rbd_offset accordingly with one LMFC count tolerance.6. Perform multiple power cycles and make sure lane de-skew error does not occur using this RBD offset

value.

The RBD count should be fairly consistent, within 2 counts variation from one power cycle to anotherpower cycle. In the following examples, the parameter values are L > 1, F=1 and K=32. The legal values ofthe LMFC counter is 0 to ((FxK/4)-1), which is 0 to 7. In Figure 6-2 , the latest arrival lane variation fallswithin 1 local multi-frame period. In this scenario, if latency is not a concern, you can leave the defaultvalue of csr_rbd_offset=0, which means the RBD elastic buffer is released at the LMFC boundary. In Figure 6-3 , the latest arrival lane variation spans across 2 local multi-frames; the latest arrival lanevariation happens before and after the LMFC boundary. In this scenario, you need to configure the RBDoffset correctly to avoid lane de-skew error as indicated in bit 4 of rx_err0 register.

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Altera Corporation JESD204B IP Core Deterministic Latency Implementation Guidelines

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Figure 6-2: Early RBD Release Opportunity for Latest Arrival Lane Within One Local Multi-FrameScenario

In this example, the SYSREF pulse at rx_sysref port of the IP core is sampled by the internal register. After2 link clock cycles, the LMFC counter resets. The delay from SYSREF sampled high to LMFC counterresets is deterministic. The transition of /K/ character to /R/ character marks the beginning of ILAS phase.The number of LMFC count of the /R/ character relative to the next LMFC boundary in the latest arrivallane is reported as the RBD count. In the first power cycle, the /R/ character is received at 4 LMFC countsbefore the next LMFC boundary, hence the RBD count = 4. In the second power cycle, the /R/ character isreceived at 3 LMFC counts before next LMFC boundary, hence the RBD count = 3. In five power cycles,the RBD count varies from 3 to 5. Since there are limited number of power cycles and boards forcharacterization, 1 LMFC count tolerance is allocated as a guide to set early RBD release opportunity.Hence, setting csr_rbd_offset = 1 can safely release the elastic buffer 1 LMFC count earlier at LMFC count7 before the next LMFC boundary. If the RBD elastic buffer is released before the latest arrival lane, thiswill cause a lane de-skew error.

1st LMFC boundary

SYSREF pulse is sampled by IP core

internal register

2 link clock cycle deterministic delay from SYSREF sampled high to 1stLMFC boundary

Link clock

Free running LMFC counterInternalLMFC Counter 0 1 2 7 0 1 2 3 4 5 6 7

K

SYNC_N deasserted at LMFC boundary

K K RK K K K KLatest arrival lane in first power cycle

D D D DK K

0 1

RBD count = 4

K K K KK K K K KLatest arrival

lane in second power cycle

R D D DK K

RBD count = 3

K K K DK K K K KLatest arrival lane in fifth power cycle

D D D DK R

4th LMFC boundary

RBD count = 5

K K K KK K K K KAligned

outputs on all lanes K K R DK K

1 link clock or LMFC count to cater for

power cycle variation

RBD Elastic Buffers Released

Set csr_rbd_offset = 1

1 link clock period = LMFC count

4 LMFC counts from LMFC boundaryInternal LMFC counter resets

SYNC_N

rx_sysref

2ndLMFC boundary

K K

K K

K K

K K

K

K

K

K

0

3rd LMFC boundary

UG-011422015.11.02 Programmable RBD Offset 6-3

JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation

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Figure 6-3: Early RBD Release Opportunity for Latest Arrival Lane Across Two Local Multi-FramesScenario

In this example, the RBD count varies from 7 to 1; the /R/ character is received at the previous local multi-frame when the RBD count = 1; the /R/ character is received at the current local multi-frame when theRBD count = 0 and 7. In this scenario, deterministic latency is not guaranteed because the RBD elasticbuffer is released either at the current LMFC boundary when the RBD count = 0 and 1, or one local multi-frame period later at the next LMFC boundary when the RBD count = 7. You can fix this issue by settingthe RBD offset so that the RBD elastic buffer is always released at the next local multi-frame. Settingcsr_rbd_offset = 5 forces the release of RBD elastic buffer 5 LMFC counts before the next LMFC boundary.This corresponds to LMFC count of 3 at the current local multi-frame. In this scenario, settingcsr_rbd_offset not only optimizes user data latency through the IP core, it also resolves the deterministiclatency issue.

1st LMFC boundary

SYSREF pulse is sampled by IP core ‘s

internal register

2 link clock cycle deterministic delay from SYSREF sampled high to LMFC zero-crossing

Link clock

Free running LMFC counterInternalLMFC Counter

0

K

SYNC_N deasserted directly after LMFC boundary

K K K K RK K K K KLatest arrival lane in first power cycle

D D D DK K

RBD count = 7

K K K K K KK K K K KLatest arrival

lane in second power cycle

R D D D

RBD count = 0

K K K K K DK K K K KLatest arrival lane in fifthpower cycle

D D D DR

Next LMFC boundary

RBD count = 1 with reference to the current LMFC boundary

K K K K K KK K K K KAligned

outputs on all lanes

K R D DK K1 link clock or LMFC

count to cater for power cycle variation RBD Elastic

Buffers Released



7 LMFC counts withreference to the nextLMFC boundary

Internal LMFC counter resets

Current LMFC boundary

D D

RBD elastic buffer is released at the currentLMFC boundary during the second and fifth power cycle when csr_rbd_offset = 0

RBD elastic buffer is released at the next LMFC boundary during the first power cycle when csr _rbd_offset = 0

Latency variation = 1 local multi-frame period

D D

DD

DDD

DD

rx_sysref

SYNC_N

2nd LMFC boundary

1 2 0 0 1 2 3 4 5 6 7 0 171 2

In the example above, lane de-skew error could happen if the sum of the difference of /R/ character’sLMFC count in the earliest arrival lane to the latest arrival lane, and the number of LMFC count up to therelease of RBD elastic buffer exceeds the RBD elastic buffer size. If this is the root cause of lane de-skewerror, setting RBD offset is one of the techniques to overcome this issue. Not every RBD offset value islegal. Figure below illustrates the technique to decide the legal RBD offset value.

6-4 Programmable RBD OffsetUG-01142

2015.11.02


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Figure 6-4: Selecting Legal RBD Offset Value

First LMFC boundary

Free running LMFC counter 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7

K K KK K K K KEarliest arrival lane

D D D D

0 1

RBD count = 7

K K KK K K K KLatest arrival lane R D D

Next LMFC boundary

K K K KK K K K KAligned outputs on all

lanesK R D D

RBD Elastic Buffers Released


7 LMFC counts with reference to the

next LMFC boundary


7

Current LMFC boundary

D D

D D

DD

DD

2

D D D D

KK K K K K K

RBD elastic buffer size = 8

RK K K

RBD Elastic buffers released at LMFC boundary when csr _rbd_offset=0

KK K K K K K

Legal csr_rbd_offset=4within RBD elastic buffer size

Illegal csr_rbd_offset=1, 2, 3exceeding RBD elastic buffer size

InternalLMFC Counter

RBD elastic buffer size exceeded and causes lane deskew error

Because the IP core does not report the position of the earliest lane arrival with respect to the LMFCboundary, you should perform multiple power cycles to observe the RBD count and tune the RBD offsetaccordingly until no lane de-skew error occurs. From the example in the figure above, the recommendedRBD offset value is 4 or 5. Setting RBD offset to 1, 2 or 3 is illegal because this exceeds the RBD elasticbuffer size for the F and K configurations.

Related InformationSYNC_N Signal on page 4-14

Programmable LMFC OffsetIf your JESD204B subsystem design has deterministic latency issue, the programmable LMFC offset in theTX and RX IP cores provides flexibility to ensure that deterministic latency can be achieved.

The TX LMFC offset can align the TX LMFC counter to the LMFC counter in DAC; the RX LMFC offsetcan align the RX LMFC counter to the LMFC counter in ADC. Phase offset between the TX and RXLMFC counters in the both ends of the JESD204B link contributes to deterministic latency uncertainty.The phase offset is caused by:

• SYSREF trace length mismatch in the PCB between the TX and RX devices (FPGA and converters).• delay differences in resetting the LMFC counter when SYSREF pulses are detected by the FPGA and

converter devices.

The RX device in the JESD204B link is responsible for deterministic latency adjustments. The followingfigure illustrates the adjustments that you can make to the RX LMFC offset using the csr_lmfc_offset fieldin the syncn_sysref_ctrl register. This is an alternative to using csr_rbd_offset to achieve deterministiclatency.

UG-011422015.11.02 Programmable LMFC Offset 6-5


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Figure 6-5: Selecting Legal LMFC Offset Value for RX

Sequence of events in the diagram:

1. Due to trace length mismatch, SYSREF pulse arrives at the ADC first.2. Some deterministic delay occurs in between the time when the SYSREF pulse is sampled high to the

reset of the ADC internal LMFC counter.3. The SYSREF pulse arrives at the FPGA IP core port, rx_sysref, after the pulse's arrival at the ADC.4. The FPGA IP core's internal LMFC counter resets two link clock cycles after SYSREF is sampled.5. The LMFC phase offset between the LMFC counter at ADC and FPGA is ~3.5 link clock cycles.6. The FPGA deasserts SYNC_N at the LMFC boundary.7. The ADC JESD204B core detects the SYNC_N deassertion.8. Because SYNC_N deassertion is detected after the second LMFC boundary at ADC, ILAS transmission

begins at the third LMFC boundary.9. In this example, the ILAS arrives at the IP core's RBD elastic buffer within one local multi-frame. In

other system, the arrival at the RBD elastic buffer could span more than one local multi-frame.Assuming csr_rbd_offset = 0, RBD elastic buffer may be released at the third or fourth LMFC boundarydue to power cycle variation.

10.Setting csr_lmfc_offset = 5 resets the LMFC counter to the value of 5.11.The first LMFC boundary is delayed by three link clock cycles.12.The third LMFC boundary has been delayed past the latest arrival lane power cycle variation. The RBD

elastic buffer is always released at the third LMFC boundary.

First LMFC boundary

SYSREF pulse is sampled by IP core

internal register

2 link clock cycle deterministic delay from SYSREF sampled

high to the first LMFC boundary

Free running LMFC counterInternal

LMFC Counter 0 1 2 0 1 0 1 2 3 4 5 6 7

K

SYNC_N deasserted directly after LMFC boundary

K K K K RK K K K KLatest arrival

lane in multiple power cycles

D D D D

0

Power cycle variation

Fourth LMFC boundary


Internal LMFC counter resetscsr_lmfc_offset=0

7

Third LMFC boundary

D D

Free running LMFC counter

ADCInternal

LMFC Counter0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 17

SYSREF pulse is sampled by ADC

SYNC_N transmitted by RX

0

SYNC_N deassertion is detected by ADCSYNC_N

arrival at TX

K K K K K RK K K K KL Transmit lanes D D D DK D D

ILAS transmission by ADC


First LMFC boundary

Second LMFC boundary

Third LMFC boundary

LMFC phase offset

R R


LMFC Counter 5 6 7 0 5 6 7 0 1 2 3 4 5

RBD elastic buffer releasedwhen csr_rbd_offset=0

4

K K K K KK K K K K


LMFC boundary is delayed by 3 link clock

First LMFC boundary at new location

R D D D D D DR R

1 link clock or LMFC countto cater for power cycle variation

6

3

K


KLatest arrival


rx_sysref

1

2

3

4

5

6

7

8

9

1011

12

Third LMFC boundary at new location

6-6 Programmable LMFC OffsetUG-01142

2015.11.02


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You should set a safe LMFC offset value to ensure deterministic latency from one power cycle to anotherpower cycle. In Figure 6-6, the illegal csr_lmfc_offset values of 1, 2, and 3 will cause lane de-skew errorbecause the RBD buffer size has exceeded.

Figure 6-6: Selecting Illegal LMFC Offset Value for RX, Causing Lane Deskew Error

First LMFC boundary

SYSREF pulse is sampled by IP core ‘s

internal register

2 link clock cycle deterministic delay from SYSREF sampled

high to the first LMFC boundary


LMFC Counter 0 1 2 0 1 4 0 1 2 3 4 5 6 7

K

SYNC_N deasserted at LMFC boundary

K K K K RK K K K KLatest arrival


D D D D

0

Power cycle variation



Internal LMFC counter resetscsr _lmfc_offset=0

7

Third LMFC boundary

D D

SYNC_N transmitted by RX

R R


LMFC Counter 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 3

RBD elastic buffer released

when csr _rbd_offset=0

2

K K K K KK K K K K




R D D D D D DR R

6

1

K

KLatest arrival


K K K K K RK K K K KEarliest arrival lane D D DD D DK

5

RBD elastic buffer size = 8

D D D

RBD elastic buffer size is exceeded

rx_sysref


You can use the TX LMFC offset to align the LMFC counter in IP core to the LMFC counter in DAC.



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Figure 6-7: Example of Reducing LMFC Phase Offset between TX and RX LMFC Counter


1. SYSREF pulse arrives at the FPGA IP core port, tx_sysref.2. The IP core's internal LMFC counter resets after two link clock cycles.3. SYSREF pulse is sampled by the DAC.4. The DAC's internal LMFC counter resets after a deterministic delay.5. The LMFC phase offset is ~3.5 link clock cycles.6. The DAC deasserts SYNC_N at the LMFC boundary.7. SYNC_N deassertion is detected by the JESD204B IP core.8. Because SYNC_N deassertion is detected after the second LMFC boundary at the FPGA, ILAS

transmission begins at the third LMFC boundary.9. The csr_lmfc_offset is set to 4. This delays the TX LMFC boundary by 4 link clock cycles. If

csr_lmfc_offset is set to 5, the TX LMFC boundary is delayed by 3 link clock cycles.10.The LMFC phase offset between the TX and RX LMFC reduces to 0.5 link clock cycle.

First LMFC boundary

SYSREF pulse is sampled by DAC

2 link clock cycle deterministic delay from SYSREF sampled high to the first LMFC boundary


LMFC Counter 0 1 0 1 2 0 1 2 3 4 5

SYNC_N deasserted atthe LMFC boundary


7

Third LMFC boundary


0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 07

SYSREF pulse is sampled by FPGA

IP core

SYNC_N transmitted by DAC

0

SYNC_N deassertion is detected by the IP coreSYNC_N

arrival at TX

K K K K K RK K K K KL Transmit lanes D D D DK D D

ILAS transmission by the FPGA


First LMFC boundary


Third LMFC boundary

6


Link clock


Deterministic delay from SYSREF sampled high to the first LMFC boundary

LMFC phase offset


4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 434InternalLMFC Counter



K K K K K RK K K K KL Transmit lanes DK D DK K K

Reduced LMFC phase offset

K


tx_sysref1

2

3

4

5

6

78

9

10

9


ILAS transmission by the FPGA

Alternative to tuning RBD offset at the DAC, adjusting TX LMFC offset in the FPGA helps you to achievedeterministic latency. You should perform multiple power cycles and read the RBD counts at the DAC todetermine whether deterministic latency is achieved and RBD elastic buffer size has not exceeded.

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The SYSREF pipeline registers in the FPGA introduce additional latency to SYSREF when detected by theIP core. Therefore, you can use TX LMFC offset to reduce or eliminate this additional latency. The nextfigure illustrates the technique of optimizing latency using TX LMFC offset.

Figure 6-8: Optimizing IP Core Latency Using TX LMFC Offset


1. The DAC samples the SYSREF pulse.2. The DAC's internal LMFC counter resets after a deterministic delay.3. The SYSREF pipeline registers introduces an additional 2 link clock latency.4. The csr_lmfc_offset field is set to 4. The IP core internal LMFC counter resets after 2 link clock cycles.5. The LMFC boundary is delayed by 4 link clock.6. The DAC deasserts SYNC_N at the LMFC boundary.7. SYNC_N deassertion is detected by the JESD204B IP core.8. Because LMFC boundary is delayed by 4 link clock, the IP core detects the SYNC_N deassertion before

the second LMFC boundary. ILAS transmission begins at the second LMFC boundary instead of thethird LMFC boundary (in Figure 6-7). The latency is shortened by 4 LMFC counts or link clock cycles.

1

2

3

4

5

6

7

8

First LMFC boundary

SYSREF pulse is sampled by DAC

2 link clock cycle deterministic delay from SYSREF sampled high to LMFC counter resets


LMFC Counter 0 1 7 0 1 0 1 2 3 4 5

SYNC_N deasserted at the LMFC boundary

7

Third LMFC boundary

Free running LMFC counter 0 1 2 3 7 0 1 2 3

SYSREF pulse is sampled by FPGA

IP core

SYNC_N transmitted by DAC

0

SYNC_N deassertion is detected by IP coreSYNC_N

arrival at TX

K K K K RK K K K KL Transmit lanes D

ILAS transmission by FPGA


First LMFC boundary

Second LMFC boundary at new location

Third LMFC boundary

6

Link clock


Deterministic delay from SYSREF sampled high to the first LMFC

boundary

Free running LMFC counter 4 5 6 7 4 5 6 7InternalLMFC Counter



K K K K RK K K K KL Transmit lanes K K

LMFC boundary is delayed by 4 link clocks

Additional 2 link clock latency caused by SYSREF pipeline registers

K K

6543

Second LMFC boundarytx_sysref

LMFC boundary is delayed by 4 link clocks


2 3

1

ILAS transmission by FPGA

72

7

3

D

3

4

0

K

4

0 0


K

K

K

K

The csr_lmfc_offset field provides a convenient way to achieve deterministic latency and potentiallyoptimizing the IP core latency. There are other ways that you can achieve deterministic latency by usingthe features available at the converters. Consult the converter manufacturer for details of these features.



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Maintaining Deterministic Latency during Link ReinitializationLink reinitialization occurs when the RX device deasserts the SYNC_N signal after link is established.

The converters resample the SYSREF signal and reset the internal LMFC counter. When the link isinitially established, the IP core automatically clears the csr_sysref_singledet bit in thesyncn_sysref_ctrl register (address 0x54) when it detects the SYSREF pulse. The IP core does notautomatically resample the SYSREF pulse unless the jesd204_tx_avs_rst_n or jesd204_rx_avs_rst_nsignal is asserted.

If you are performing a link reset by asserting txlink_rst_n or rxlink_rst_n to reinitialize the link, setthe csr_sysref_singledet bit to "1" to force the IP core to resample the SYSREF pulse without assertingthe jesd204_tx_avs_rst_n or jesd204_rx_avs_rst_n signal.

6-10 Maintaining Deterministic Latency during Link ReinitializationUG-01142

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JESD204B IP Core Debug Guidelines 72015.11.02


This section lists some guidelines to assist you in debugging JESD204B link issues. Apart from applyinggeneral board level hardware troubleshooting technique like checking the power supply, external clocksource, physical damage on components, a fundamental understanding of the JESD204B subsystemoperation is important.

Related Information

• Clocking Scheme on page 7-1• JESD204B Parameters on page 7-1• SPI Programming on page 7-2• Converter and FPGA Operating Conditions on page 7-2• Signal Polarity and FPGA Pin Assignment on page 7-2• Debugging JESD204B Link Using SignalTap II and System Console on page 7-3

Clocking SchemeTo verifying the clocking scheme, follow these steps:

1. Check that the frame and link clock frequency settings are correct in the Altera PLL IP core. For thedesign example, the frame clock is assigned to outclk0 and link clock is assigned to outclk1.

2. Check the device clock frequency at the FPGA and converter.3. For Subclass 1, check the SYSREF pulse frequency.4. Check the clock frequency management. For the design example, using Stratix V and Arria V devices,

this frequency is 100 MHz.

JESD204B ParametersThe parameters in both the FPGA and ADC should be set to the same values. For example, when you setK = 32 on the FPGA, set the converter's K value to 32 as well. Scrambling does not affect the link initiali‐zation in the CGS and ILAS phases but in the user data phase. When scrambling is enabled on the ADC,the FPGA descrambling option has to be turned on using the "Enable scramble (SCR)" option in theJESD204B IP core Qsys parameter editor. When scrambling is enabled on the FPGA, the DAC descram‐bling has to be turned on too.





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Check these items:

• Turn off the scrambler and descrambler options as needed.• Use single lane configuration and K = 32 value to isolate multiple lane alignment issue.• Use Subclass 0 mode to isolate SYSREF related issues like setup or hold time and frequency of SYSREF

pulse.

SPI ProgrammingThe SPI interface configures the converter. Hence, it is important to check the SPI programming sequenceand register bit settings for the converter. If you use the MIF to store the SPI register settings of theconverter, mistakes may occur when modifying the MIF, for example, setting a certain bit to "1" instead of"0", missing or extra bits in a MIF content row.

Check these items:

• For example, in the ADI AD9250 converter, Altera recommends that you first perform register bitsetting for the scramble (SCR) or lane (L) register at address 0x6E before setting the quick configura‐tion register at address 0x5E.

• Determine that each row of the MIF has the same number of bits as the data width of the ROM thatstores the MIF.

Converter and FPGA Operating ConditionsThe transceiver channels at the converter and FPGA are bounded by minimum and maximum data raterequirements. Always check the most updated device data sheet for this info. For example, the Arria V GTdevice has a minimum data rate of 611 Mbps.

Ensure that the sampling rate of the converter is within the minimum and maximum requirements. Forexample, the ADC AD9250 has a minimum sampling rate of 40 Msps. For L = 2, M = 1 configuration, theminimum data rate of this ADC is calculated this way:

The minimum data rate for the JESD204B link is effectively 611 Mbps.

Check these items:

• Reduce the data rate or sampling clock frequency if your targeted operating requirement does notwork.

• Verify the minimum and maximum data rate requirements in the device manufacturer's data sheet.

Signal Polarity and FPGA Pin Assignment

Verify that the transceiver channel pin assignments—SYNC_N and SYSREF (for Subclass 1 only)—deviceclock, and SPI interface are correct. Also verify the signal polarity of the differential pairs like SYNC_N andtransceiver channels are correct.

7-2 SPI ProgrammingUG-01142

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Altera Corporation JESD204B IP Core Debug Guidelines

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Check these items:

• Review the schematic and board layout file to determine the polarity of the physical pin connection.• Use assignment editor and pin planner to check the pin assignment and I/O standard for each pin.• Use RTL viewer in the Quartus Prime software to verify that the top level port are connected to the

lower level module that you instantiate.

Debugging JESD204B Link Using SignalTap II and System ConsoleThe SignalTap II provides dynamic view of signals while the system console provides access to theJESD204B IP core register sets through the Avalon-MM interfaces.

The SignalTap II and system console are very useful tools in debugging the JESD204B link related issues.To use the system console, your design must contain a Qsys subsystem with the JTAG-to-Avalon-MMMaster bridge component and the Merlin slave translator ports that connect to the JESD204B IP coreAvalon-MM interface.

PHY Layer

Verify the RX PHY status through these signals in the <ip_variant_name>.v:

• rx_is_lockedtodata• rx_analogreset• rx_digitalreset• rx_cal_busy

Verify the TX PHY status through these signals in the <ip_variant_name>.v:

• pll_locked• pll_powerdown• tx_analogreset• tx_digitalreset• tx_cal_busy

Verify the RX_TX PHY status through these signals in the <ip_variant_name>.v:

• rx_is_lockedtodata• rx_analogreset• rx_digitalreset• rx_cal_busy• rx_seriallpbken• pll_locked• pll_powerdown• tx_analogreset• tx_digitalreset• tx_cal_busy

Use the rxphy_clk[0] or txphy_clk[0] signal as sampling clock for the SignalTap II.

For a normal operation of the JESD204B RX path, the rx_is_lockedtodata bit for each lane should be"1" while the rx_cal_busy, rx_analogreset, and rx_digitalreset bit for each lane should be "0".

For a normal operation of the JESD204B TX path, the pll_locked bit for each lane should be "1" whilethe tx_cal_busy, pll_powerdown, tx_analogreset, and tx_digitalreset bit for each lane should be"0".

UG-011422015.11.02 Debugging JESD204B Link Using SignalTap II and System Console 7-3

JESD204B IP Core Debug Guidelines Altera Corporation

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Measure the rxphy_clk or txphy_clk frequency by connecting the clock to the CLKOUT pin on theFPGA. The frequency should be the same as link clock frequency for PCS option in Hard PCS or Soft PCSmode. The frequency is half of the link clock frequency for PCS option in PMA Direct mode.

Link Layer

Verify the RX PHY-link layer interface operation through these signals in the<ip_variant_name>_inst_phy.v:

• jesd204_rx_pcs_data• jesd204_rx_pcs_data_valid• jesd204_rx_pcs_kchar_data• jesd204_rx_pcs_errdetect• jesd204_rx_pcs_disperr

Verify the RX link layer operation through these signals in the <ip_variant_name>.v:

• jesd204_rx_avs_rst_n• rxlink_rst_n_reset_n• rx_sysref (for Subclass 1 only)• rx_dev_sync_n• jesd204_rx_int• alldev_lane_aligned• dev_lane_aligned• rx_somf

Use the rxlink_clk signal as the sampling clock.

Verify the TX PHY-link layer interface operation through these signals in the<ip_variant_name>_inst_phy.v:

• jesd204_tx_pcs_data• jesd204_rx_pcs_kchar_data

Verify the TX link layer operation through these signals in the <ip_variant_name>.v:

• jesd204_tx_avs_rst_n• txlink_rst_n_reset_n• tx_sysref (for Subclass 1 only)• sync_n• tx_dev_sync_n• mdev_sync_n• jesd204_tx_int

Altera recommends that you verify the JESD204B functionality by accessing the DAC SPI registers or anydebug feature provided by the DAC manufacturer.

7-4 Debugging JESD204B Link Using SignalTap II and System ConsoleUG-01142

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Figure 7-1: JESD204B Link Initialization

This is a SignalTap II image during the JESD204B link initialization. The JESD204B link has twotransceiver channels (L = 2).

f

b

a

j

k

e

c

d

d

g h i

c

f

start of 1st ILAS multi-frame

Description of the timing diagram:

a. The JESD204B link is out of reset.b. The RX CDR is locked and PCS outputs valid characters to link layer.c. No running disparity error and 8b/10b block within PCS successfully decodes the incomingcharacters.d. The ADC transmits /K/ character or BC hexadecimal number to the FPGA, which starts the CGSphase.e. Upon receiving 4 consecutive /K/ characters, the link layer deasserts the rx_dev_sync_n signal.f. The JESD204B link transition from CGS to ILAS phase when ADC transmit /R/ or 1C hexadecimalafter /K/ character.g. Start of 2nd multi-frame in ILAS phase. 2nd multi-frame contains the JESD204B link configurationdata.h. Start of 3rd multi-frame.i. Start of 4th multi-frame.j. Device lanes alignment is achieved. In this example, there is only one device, the dev_lane_alignedconnects to alldev_lane_aligned and both signals are asserted together.k. Start of user data phase where user data is streamed through the JESD204B link



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Transport Layer

Verify the RX transport layer operation using these signals in the altera_jesd204_transport_rx_top.sv:

• jesd204_rx_dataout• jesd204_rx_data_valid• jesd204_rx_data_ready• jesd204_rx_link_data_ready• jesd204_rx_link_error• rxframe_rst_n

Use the rxframe_clk signal as the sampling clock.

For normal operation, the jesd204_rx_data_valid, jesd204_rx_data_ready, andjesd204_rx_link_data_ready signals should be asserted while the jesd204_rx_link_error should bedeasserted. You can view the ramp or sine wave test pattern on the jesd204_rx_dataout bus.

Figure 7-2: Ramp Pattern on the jesd204_rx_dataout Bus

This is a SignalTap II image during the JESD204B user data phase with ramp pattern transmitted from theADC.

Verify the TX transport layer operation using these signals in the altera_jesd204_transport_tx_top.sv:

• txframe_rst_n• jesd204_tx_datain• jesd204_tx_data_valid• jesd204_tx_data_ready• jesd204_tx_link_early_ready• jesd204_tx_link_data_valid• jesd204_tx_link_error

Use the txframe_clk signal as the sampling clock.

For normal operation, the jesd204_tx_data_valid, jesd204_tx_data_ready,jesd204_tx_link_early_ready, and jesd204_tx_link_data_valid signals should be asserted whilethe jesd204_tx_link_error should be deasserted. You can verify the user data arrangement (shown inthe data mapping tables in the TX Path Data Remapping on page 5-25) by referring to thejesd204_tx_datain bus.

7-6 Debugging JESD204B Link Using SignalTap II and System ConsoleUG-01142

2015.11.02


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Related Information

• AN 696: Using the JESD204B MegaCore Function in Arria V DevicesMore information about the performance and interoperability of the JESD204B IP core.

• AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor AsControl UnitAn example of implementing a full-featured software control flow with various user commands in aJESD204B system that incorporates a Nios II processor

• JESD204B Reference DesignAvailable design examples in Altera Design Store.

• Altera Transceiver PHY IP Core User GuideMore information about the transceiver PHY signals.



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https://cloud.altera.com/devstore/platform/?acds_version=any&ip_core=JESD204



Additional Information 82015.11.02


Additional information about the document and Altera.

JESD204B IP Core Document Revision HistoryDate Version Changes

November2015

2015.11.02 • Added data rate support of up to 13.5 Gbps for Arria 10 and 7.5 Gbpsfor Arria V GT/ST devices.

• Updated the IP core FPGA performance and resource utilizationvalues.

• Added a new table to define the clock network selection for bondedmode in channel bonding.

• Added a new selection for PCS Option parameter—Enabled PMADirect.

• Updated the preset value for link clock in JESD204B IP CoreTestbench on page 3-21.

• Updated the formula and description for TX/RX PHY clock.• Updated the device clock section to recommend user to supply the

device clock with the same frequency as the link clock.• Updated the description of txlink_clk, txphy_clk[], and rxphy_

clk[] signals.• Changed the default value for RX Phase Compensation FIFO empty

error enable (csr_pcfifo_empty_err_en) CSR to 0. Refer to the RXregister map for details.

• Added a new section to describe the Design Example with Nios IIProcessor Control Unit on page 5-65.

• Added a new topic – Maintaining Deterministic Latency duringLink Reinitialization on page 6-10.

• Changed instances of Quartus II to Quartus Prime.





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Date Version Changes

May 2015 2015.05.04 • Added support for Cyclone V FPGA device family.• Updated the JESD204B IP Core Configuration values:

• M value from 1-32 to 1-256• N' value from 4-32 to 1-32

• Updated the JESD204B IP Core FPGA Performance table.• Updated the JESD204B IP Core FPGA Resource Utilization table.• Added new parameters to the JESD204B IP Core Parameters table:

• Enable Capability Registers• Set user-defined IP identifier• Enable Control and Status Registers• Enable Prbs Soft Accumulators• Enable manual F configuration

• Added new topics:

• Timing Constraints For Input Clocks on page 3-13• JESD204B IP Core Deterministic Latency Implementation

Guidelines on page 6-1• Revised the note in "Simulating the IP Core Testbench" to state that

VHDL is not supported in Aldec Riviera (for Arria 10 devices only).• Updated Figure 8-16.

8-2 JESD204B IP Core Document Revision HistoryUG-01142

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December2014

2014.12.15 • Updated the JESD204B IP Core FPGA Performance table with thedata rate range.

• Updated the JESD204B IP Core FPGA Resource Utilization table.• Updated the JESD204B IP Core Parameters table with the following

changes:

• Revised the parameter name of Enable PLL/CDR DynamicReconfiguration to Enable Transceiver Dynamic Reconfigura‐tion.

• Added information for a new parameter—Enable Altera DebugMaster Endpoint.

• Added details about the rule check for parameter N' value.• Added a new topic—Integrating the JESD204B IP core in Qsys on

page 3-11.• Updated Figure 8-1, Figure 8-3, and Figure 8-4.• Added a new table—Register Access Type Convention—to describe

the access type for the IP core registers.• Added new signals description for jesd204_tx_controlout and

jesd204_rx_controlout.• Added CONTROL_BUS_WIDTH parameter and description for the

assembler and deassembler.• Added information on how to run the Tcl script using the Quartus II

sofware before compiling the design example.• Updated the section on Debugging JESD204B Link Using SignalTap

II and System Console on page 7-3 with verification information forTX PHY-link layer interface, TX link layer, and TX transport layeroperations.

UG-011422015.11.02 JESD204B IP Core Document Revision History 8-3

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June 2014 2014.06.30 • Updated Figure 2-1 to show a typical system application.• Updated the list of core key features.• Updated the Performance and Resource utilization values.• Updated the Getting Started chapter to reflect the new IP Catalog and

parameter editor.• Added the following new sections to further describe the JESD204B

IP core features:

• Channel Bonding• Datapath Modes• IP Core Variation• JESD204B IP Core Testbench• JESD204B IP Core Design Considerations• TX Data Link Layer• TX PHY Layer• RX Data Link Layer• RX PHY Layer• Operation• Example Feature: Dynamic Reconfiguration• JESD204B IP Core Debug Guidelines

• Updated the Clocking scheme section.• Added new transceiver signals that is supported in Arria 10 devices.• Updated the Transport Layer section.• Added run-time reconfiguration parameter values in the System

Parameters section.• Updated the file directory names.

November2013

2013.11.04 Initial release.

How to Contact Altera

Table 8-1: Altera Contact Information

Contact(45) Contact Method Address

Technical support Website www.altera.com/support

Technical trainingWebsite www.altera.com/training

Email [email protected]

Product literature Website www.altera.com/literature

(45) You can also contact your local Altera sales office or sales representative.

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Contact(45) Contact Method Address

Nontechnicalsupport

General Email [email protected]

Software licensing Email [email protected]

Related Information

• www.altera.com/support• www.altera.com/training• www.altera.com/literature

(45) You can also contact your local Altera sales office or sales representative.

UG-011422015.11.02 How to Contact Altera 8-5

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