JEP HW status and FW integration plans

Uli Schaefer and Pawel PlucinskiUli Schaefer and Pawel PlucinskiJohannes-Gutenberg Universitaet Mainz Johannes-Gutenberg Universitaet Mainz

Stockholm UniversityStockholm University

General remarks (Jet-FPGA)

Jet-FPGA firmware upgrade to add RoIs to the real time output.Algorithm will report up to four RoIs.No side effects. The latency will not be affected.16 registers (thresholds) in use (in total 117 including spare).Updated components:

- Algorithm (including backplane data).

- VME interface.

- Glink stream (RoI-to-L2).

- SPY Memory (output).

- Clock manager (DCM: 160MHz and 80MHz).Diagnostic module (tests pattern, Jet and Sum-FPGA)

implemented.

JEM: Jet-Energy and sum-FPGA

Jet/FPGA

sum/FPGA

Architecture of the jet-FPGA

Architecture is modular, its easier to add, replace or modify...

Component 1

Component 2

Component 3

Component 4

Component 5

Jet-FPGA – Backplane (JEM to CMX energy data)

Eight 'presence' bits, indicating in which subregions jet RoIs were indentified.

Four 2-bit 'fine-position' fields, one for each identified RoI

Four 10-bit transverse energy sums for jet size 1

Four 9-bit transverse energy sums for jet size 2

GLINK Format – JEM ROI (L2)

Jet-FPGA register map (16 thresholds)

Threshold and sizes

Register contents:

2b cluster size

10b Et threshold

VME interface and register space is updated, in total 117 registers.

Location: offset + 200

Threshold default value is set to 0x3FF

Jet processing – New idea

Thresholds and sizes register mapping (FCAL and CENTRAL):8 sets of threshold/size registers, each specifying 8 sets of threshold/size registers, each specifying two jet sizestwo jet sizes (JET Energies for larger and (JET Energies for larger and smaller window size) to be used and the smaller window size) to be used and the minimum threshold for each.minimum threshold for each.

RoIO:Threshold1/Size1

Threshold2/Size2

RoI1:Threshold1/Size1

Threshold2/Size2

RoI2:Threshold1/Size1

Threshold2/Size2

RoI3:Threshold1/Size1

Threshold2/Size2

RoI4:Threshold1/Size1

Threshold2/Size2

RoI5:Threshold1/Size1

Threshold2/Size2

RoI6:Threshold1/Size1

Threshold2/Size2

RoI7:Threshold1/Size1

Threshold2/Size2

Diagnostic module (Jet and Sum-FPGA)

JEM FW generating tests patterns at 160Mbps.JEM FW features:

- Support for CMX timing procedure.- Stress patterns (ISI, Xtalk).- Built in as part of main firmware (persistent)- Pattern selectable from a ‘pre-defined’ menu:

- No need to reserve-engineer inputs/menu to generate desired output.

- Pattern consists of one special event and 255 repeating events.

- Common components for Jet and Sum-FPGA.

JET-FPGA ready, Sum-FPGA soon!

DCM structure (modified)

Two extra clocks needed: 160MHz and 80MHz:

Conclusions / Plans Jet-FPGA FW is ready (tests ongoing), software version 1.0 is

also ready. Algorithm supports 16 thresholds but other solutions is easy to

implement. Diagnostic module (tests pattern) is ready, Jet-FPGA ready

Sum-FPGA soon. JEM + BLT backplane tests (160Mbps) conducted at CERN. Integration (+ extra tests) with CMX scheduled on April.

Some further work on Sum FPGA firmware required Uli / MZ

160Mb/s infrastructure exists due to implementation of “diagnostic module” Add “algorithmic” part

Routing energy sums out to the output multiplexers Reorganize DAQ output stream

Do further tests !