JBTech INDIA-Summer Training Details-2010

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Contents: ‐ P.No.

1. Designing the power of tomorrow ……………………………….3

2. Training Details …………………………………………………………….3

3. Summer Training in VLSI design …………………………………….4

4. Training contents…………………………………………………….…….4

5. Week by week Training details………………………………………5

6. Module wise contents………………………………………………..…5

7. Project Development flow………………………………………….…8

8. Benefits of training……………………………………………………….9

9. Diversity of students…………………………………………..………..9

10. How to register , fee and accommodation facility…..…....9

11. How to reach………………………………………………………………11

12. Application form……………………………………….…….………….12

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VLSI Training Details.

In today’s knowledge based world, the power of technology can only

be harnessed through empowered education. As convergence increase so

does the complexity of technology and digital electronics technology is

rapidly changing. At every level of IC designing we need in depth and

technically strong education to ensure growth in dynamic field of VLSI

design. The training offered by JBTech INDIA have created a strong

knowledge base in VLSI industry.

Training Modules Includes:-

1. VLSI ILP-1. This Module is of long term duration (16 – 24 Week). Eligibility: - B.Tech (EC/EE/EI/ET, 4th year or passed out), M.Sc

(Electronics), MTech.

2. VLSI ILP. (Summer Training) This is a short term duration module (4 – 12 Weeks). Eligibility: - B.Tech (EC/EE/EI/ET, 2nd, 3rd, 4th year or passed

out), M.Sc (Electronics), MTech (VLSI/Microelectronics/EC).

1. Designing The Power of Tomorrow

2. Training Details

VLSI Design Solutions and Industrial Project Training

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3. Certificate courses (Front end, Back end). Verilog HDL, VHDL , SPICE , Layout Design , C/C++, Tcl/Tk ,

Shell/Perl ,CMOS Digital Design ,Semiconductor Physics , DFT (Design for testability) , STA (Static Timing Analysis) , MATLAB. FPGA (Spartan, Virtex).

Training aims at providing a basic understanding of the flow of

integrated circuit design, by working on an industry standard project

either in front end or back end according to technical depth and in

previous subject knowledge. Module 1: Verilog HDL or VHDL.

Module 2: ASIC Design Flow.

Module 3: Digital Design Techniques.

Module 4: Simulation and Synthesis (What How and Why).

Project. (Major Focus will be on project).

Specification.

Design Entry (RTL).

RTL Simulation.

Synthesis.

Netlist Simulation.

FPGA Prototyping.

4. Summer Training Contents Duration: 4, 6, 8 Week

3. Summer Training in VLSI

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Module 1:- Verilog HDL (Book: Smair Palnitkar).

Introduction to Verilog HDL.

Syntax and Semantics.

Modeling Techniques.

Gate level Description.

Dataflow Description.

Behavioral Modeling.

Advanced Modeling Techniques.

State machine Design and RTL coding.

Transistor Level Description.

User Defined Primitives.

6. Module Wise Contents:-

5. Week by Week Training Flow for 6 – 8 week:-

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VHDL (Book: Douglas Perry). Introduction to VHDL. Modeling Techniques.

Syntax and Semantics.

Modeling Techniques.

- Behavioral Modeling, Sequential Processing.

Subprograms and Packages.

Attributes.

Configuration.

Module 2:

ASIC Design Flow: (JBTech INDIA Notes).

This Involves the discussion over complete ASIC flow step by step ,

this will give over all view to trainees about how an integrated circuit

in built starting from Ram Material Silicon to Prepared Integrated

Circuit.

Module 3:-

Digital Design Techniques.(Books: J F Wakerly, Morris Mano).

Binary Algebra.

Digital Implementations using universal elements.

Combinational Circuits design techniques and Implementation.

Sequential circuit design techniques and implementations.

State Machines.

Memory Designing.

Timing analysis.

PLAs, PALs.

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Module 4:- Simulation and Synthesis (JBTech INDIA Notes)

HDL Simulation and Synthesis Concepts.

What is Simulation?

Types of Simulation.

Simulation levels.

Synthesis issues.

Goals of synthesis.

Why synthesis.

Synthesis design Flow.

RTL descriptions.

Synthesis with, without constraints.

Synthesis characterization.

Levels of synthesis.

HDL coding styles for improved synthesis results.

Synthesis Advantages.

Timing Driven Synthesis.

Technology Library.

Redundant Logic.

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7. Project Development Flow:-

Literature

Specifications

Design

Design Entry

RTL Simulation

Fix Errors

Synthesis

Post Synthesis Simulation

Fix Errors

FPGA

Check Working Model

Final Report, Preparation

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How to Use FPGA.

Will be able to understand what and Why, ASIC, FPGA and CPLDs.

Will be able to grasp the IC Design Complexity.

Will become familiar with the flow of IC Design.

Interaction with R&D Professionals in VLSI.

From BASICs to ASICs.

From Gates to Microprocessor.

80% of the students are from outside of Greater Noida including

different institutes of national and international reputation. Following

are some of the institutes of reputations from which students

participated in summer training as well as customized modules training.

IIT, Roorkee (PhD Students).

MNNIT, Allahabad (B.Tech, MTech Students).

NIT, Kurukshetra. (B.Tech Students).

NIT, Jalandhar. (B.Tech Students).

Delhi Technological University, DCE Formerly, Delhi (B.Tech Students).

Thapar University, Patiala (B.Tech students).

IIIT, Allahabad (B.Tech students).

Bharati Vidyapeeth, Pune (MTech Students).

MITS, Rajasthan (B.Tech Students).

9. Diversity of Students:-

8. Benefits of Training:-

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SIET, Meerut (B.Tech, MTech Students).

SRM University, Modinagar (MTech, B.Tech Students).

BMAS (Agra) , MIT (B.Shahar) , BBDIT (B.Shahar) , GNIT (Greater

Noida) , Skyline (Greater Noida) , IILM (Greater Noida) , GCET

(Greater Noida) , BRCM (Haryana) , DIT (D.Doon) , NIET(Greater

Noida), Kochi University (Kerala),IETE(Delhi),JIITU(Noida).

and many more . . .

Fill the application form given in last section and send it to the address

mentioned below with a DD of 500/- . Draft should me make in the name

of JBTech INDIA and Payable at Greater Noida only.

Documents to be attached with application form:-

1. A PP size snap pasted on application form.

2. DD of Rs 500/- in favor of JBTech INDIA Payable at Greater

Noida.

Address for sending application form:-

Director.

JBTech INDIA.

Royal Krishna Apra Plaza, D-2, FF09.

Aplha-1 Commercial Belt, above ICICI Bank.

Greater Noida – 201308.

10. How to Register, fee and accommodation facility:-

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Training fee: -Rs 6500/- for 4 week

Rs 9000/- for 6 week

Rs 13,000/- for 8 week

Accommodation facility is available and those who need to have

accommodation should mention in application form.

The accommodation facility will be Paying Guest and will be

charged by respective owners, according to the present charges.

Delhi (Railway station (old, new), ISBT (Kashmiri Gate, Anand Vihar))

Sec 37 Noida Greater Noida Pari Chowk Alpha-1

commercial belt.

Metro Facility is available from Old Delhi Railway Station, ISBT

Kashmiri Gate, ISBT Anand Vihar, New Delhi Railway station to Noida

Sec 37 (Botanical Garden Railway station).

From Sec 37 there is good facility of public transport to greater

Noida. (UPSRTC Buses are available).

11. How to Reach:-

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JBTech INDIA VLSI Design Solutions & Project Training

JBTech INDIA Royal Krishna Apra Plaza, D-2, F-09, Alpha-I, Commercial Belt, Greater Noida (U.P), INDIA Tel: +91-0120-4213142, 09911676774 Email: [email protected]

Website: www.jbtechindia.com

JBTech INDIA-Summer Training Details-2010

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