JAZiO Incorporated 1 JAZiO JAZiO Incorporated Incorporated Digital Signal Switching Technology.
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Transcript of JAZiO Incorporated 1 JAZiO JAZiO Incorporated Incorporated Digital Signal Switching Technology.
JAZiO™ Incorporated1
JAZiOJAZiO™™
IncorporatedIncorporatedwww.JAZiO.comwww.JAZiO.com
Digital Signal Switching Technology
JAZiO™ Incorporated2
What is JAZiO Technology?• A new method of interchip I/O switching
– At high data rate with low latency– With low power– At low cost
• Effectiveness is due to using – Differential sensing with a single pin per bit– Built in timing
• Based on looking for change-of-data first
JAZiO™ Incorporated3
Traditional Signal Driving
All information is transmitted during tRF
(1/3 of bit time)
The rest of the bit time is just wasted!
One bittime
Next bittime
tRF tSU tHD
Sharp Edges Cause:
Ground Bounce!Cross Talk!
Ringing!EMI!
High Power!
JAZiO™ Incorporated4
Pseudo Differential Signal Sensing
Sensing level about1/3 of switching levelThe rest of the switching
level is just wasted!
Large switching levels cause:
Ground Bounce!Cross Talk!
Ringing!High Power!
One bittime
Next bittime
Sensing Level
VREF
SwitchingLevel
0.8V
JAZiO™ Incorporated5
JAZiO Solution• JAZiO has invented a system which
– Achieves very high performance – Has edges which can take the whole bit time– Uses differential sensing with very low signal
levels– Yet has only 1 pin per data signal
JAZiO™ Incorporated6
What’s the Secret? A Re-think• For each data signal, there is either a change
or no-change from the previous bit time• Traditional systems are good on no-change
but bad on change• JAZiO looks for change first and then
adjusts if no-change occurs• For JAZiO the decision binary is change or
no-change rather than high or low voltage
JAZiO™ Incorporated7
JAZiO Solution
SteeringLogic
DataOutput
VTR
DataInput
VTRB
A Dual Comparators are used
In cases 1 and 6 Comparator A makes a differential comparisonIn cases 2 and 5 Comparator B makes a differential comparisonIn the other four cases Data Input does not change
Data is driven coincidentally with Voltage/Timing References
DataInput
VTR
VTR
One Bit Time
Provide alternating Voltage/Timing References switching at the data rate
Next Bit Time
8 different combinations of VTR and Data Input
712
3
4 8
56
JAZiO™ Incorporated8
Steering Logic
The trick is to know how to select between Comparators A and B and what to do when Data Input does not change
JAZiO™ Incorporated9
Steering Logic
• Generate Steering Logic signals (SL and SL)• Use them with Data Output from previous Bit Time to
select between Comparators A and B
• Also use them for data latching
SL
SL
ReceiverOutput
XORin
inout
XORin
in
out
Data Input
VTR
VTR A
B
VTR
VTR
VTRLatchingSystem
LatchedOutput
JAZiO™ Incorporated10
DataOutput
SL
Initializationor
Receiver Enable
SL
VTR
VTRDataInput
DataInput
XOR
XOR
55 Small Transistors Per BitNo PLL/DLL Required
No die size penalty!!!
JAZiO™ Incorporated11
The receiver cell is: 22um x 55um
(Including routing channels)
The pad cell is: 70um x 80um
JAZiO™ Incorporated12
Time Domain
Decision is made in the Time Domain rather voltage domain
VTR
DataInput
First Look forchange
Determine no-change and
switch toComparator B
0.5V
SL
SL
DataOutput
XORin
inout
XORin
in
out
Data Input
VTR
VTR A
B
VTR
VTR
VTR
JAZiO™ Incorporated13
AYes
JAZiO™ Receiver OperationA
Rail to Rail
Rail to Rail
0 1 1 0 0 1
SL
SL
XOR-B
DataOutput
in
in
in
inout
out
Data Input
VTR
VTR
B
VTR
VTR
VTR
XOR-A
Rail to Rail
DataInput
DataOutput
Initialize
VTRVTR
Comparator Selected
Change?
SL
SL
CompBCompA
XOR-A
XOR-B
YesB A
YesYes No No
TheNo-change
Cases
JAZiO™ Incorporated14
The No-Change Case
But!The handoff from ComparatorA to B is smooth since both of them want to drive Data Outputhigh
After the handoff, Comparator Bis ready to make the nextdifferential comparison
Since Comparator A is selected itshigh value causes Data Output to remain high
DataOutput
XOR-B
in
in
in
inout
outXOR-A SL
SL
Comparator A is selected and as the differential on its inputs disappears the outputremains high temporarily
However, Comparator B is gaining a differential and itsOutput becomes a solid high
VTR
DataInput
VTR
B
A
(High)
Bit Time
But eventually the XORs will switchAnd Comparator B will be selected
JAZiO™ Incorporated15
18 JAZiO™ ReceiversD
ata
Inp
ut
0
Bit
s 1-
7
VT
RS
L
SL
VT
R
Dat
a O
utp
ut
0
SIG
NA
LS
FR
OM
P
AD
S
XO
R
XO
R
XO
R
XO
R XO
R
XO
R XO
R
XO
R
Dat
a In
pu
t 8
Dat
a In
pu
t 9
Dat
a In
pu
t 17
Dat
a O
utp
ut
8
Dat
a O
utp
ut
9
Dat
a O
utp
ut
17
Bit
s 10
-16
JAZiO™ Incorporated16
Data Rate vs Slew Rate Comparison
• Slower edges
• Lower switching levels
• Reduced slew rate
0.5 1.0 1.5 2.0 2.5 3.0 3.5
Slew Rate (V/nS)
Dat
a R
ate
per
Pin
(b
/S)
10M
100M
1G
10G
EDO-33
SDRAM-66
SDRAM-100 DDR
RDRAM
JAZiO™
JAZiO™
JAZiO™
Better
Higher Performance at Lower Power with Higher Robustness
JAZiO™ Incorporated17
Applying JAZiO Technology• JAZiO is the physical I/O layer only
– JAZiO provides no protocol– Works with any protocol– Like steel belted radial tires that work for Honda Civic,
Ferrari Sports Car, or Ford Explorer
• Easy to use– No die size penalty– No PLL/DLL or special semiconductor technology– Low Power
• Can be used anywhere that fast switching or low power is useful
JAZiO™ Incorporated18
JAZiO for DRAM• JAZiO Technology can be applied to
scaled-up versions of existing protocols like DDR or RDRAM
• Or new protocols can be developed to match JAZiO’s low latency and high bandwidth to reduce pins and increase parallelism
JAZiO™ Incorporated19
16-WideMP Server
L3
BSB
CONTROLLER
FSB
CPU
1GHz CPU
I/O
DRAM
1GHz Data Rate
Quad Processor Module
Quad Processor Module
Quad Processor Module
2GHz Interprocessor
Communication (Scalable to 4GHz)
Quad Processor Module
CPU
L3
CPU
L3
CPU
L3with 2GHz FSB & BSB
All scalable to 2x
frequencies
JAZiO™ Incorporated20
Hardware EmulationFPGA FPGA FPGA
FPGA FPGA FPGA
FPGA FPGA FPGA
Narrow, very high speed JAZiOTM interconnect that allows many FPGAs to appear as a massive logic array
JAZiO™ Incorporated21
Notebook / Internet ApplianceSOC DRAM
Power consumed in the memory interface is reduced due to low
switching levels of VTT=1.0v and VLOW=0.5v
Pavg = K•v•VTT K (Cf+1/Rt)
Therefore
Power Ratio = (0.5v•1)/(0.8v•1.8)
When compared to existing pseudo differential with VTT=1.8v, v=0.8v, similar
load capacitance, operating frequency and termination resistance
Small swing and slower transition time reduces EMI, allowing it to
be under FCC limits for higher frequency operation
JAZiO™
JAZiO™ Incorporated22
How Can JAZiO Be Used?• JAZiO is “essentially” an Open Standard• All technology is publicly visible w/o NDA• Anyone can see it, study it, simulate it, design
it in, build test chips, build prototypes, etc• Just don’t sell products without licensing it• A JAZiO demonstration chip is in design by
Micro Magic, Inc – a JAZiO Design Services partner
JAZiO™ Incorporated23
Conclusion• JAZiO uses lower levels and slower edges• Achieves high performance, low power, high
robustness• JAZiO technology is fundamentally different
from traditional methods– Time domain rather than voltage domain– Look for change first– Change vs No-change rather than High or Low
• JAZiO is available to everyone at low cost and applies to any application