Jap 2002 Relationship Between Channel Mobility

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Relationship between channel mobility and interface state densityin SiC metaloxidesemiconductor field-effect transistor

Shinsuke Harada,a) Ryoji Kosugi, Junji Senzaki, Won-Ju Cho, Kenji Fukuda,and Kazuo AraiUltra-Low-Loss Power Device Technologies Research Body and National Institute of Advanced IndustrialScience and Technology, Tsukuba Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

Seiji Suzuki

Ultra-Low-Loss Power Device Technologies Research Body and R&D Association for Future ElectronDevices, Tsukuba Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

Received 23 April 2001; accepted for publication 24 October 2001

Temperature dependence of threshold voltage in n-channel SiC metal oxidesemiconductor

field-effect transistors MOSFETs was studied. Linear relation was observed between the threshold

voltage shift when the temperature varies from 150 to 150 C and the number of the interface

states present within the energy range of 0.20.4 eV from the conduction band edge energy Ec . This

relationship revealed that the interface state profile near Ec in n-channel SiC MOSFETs can be

represented by that in n-type SiC MOS capacitors. The relationship between the channel mobility

and the interface state profile also suggested that the interface states within the energy range of

0.20.4 eV from Ec have little influence on the channel mobility. 2002 American Institute of

Physics. DOI: 10.1063/1.1428085

INTRODUCTION

4H SiC metal oxidesemiconductor field-effect tran-

sistor MOSFET is a promising candidate for high power

electronic switching devices. However, some problems still

exist in order to achieve high quality 4HSiC MOSFETs.

The most important problem is the low channel mobility of

electrons in the surface inversion layer. n-channel 4HSiC

MOSFETs with a thermally grown gate oxide have a channel

mobility of less than 10 cm2/V s, which is much lower than

that in 6HSiC.

1,2

The channel mobility may be lowered byseveral parameters such as interface trap, fixed charge, sur-

face roughness, and effective field normal to the interface.

Within these parameters, the interface trap has a significant

influence on the channel mobility in 4HSiC MOSFETs. It

drastically reduces the electrons in the inversion layer, and

trapped electrons act as a scattering center of the electrons.3,4

It is believed that the high density of interface trap D it near

the conduction band edge energy Ec causes the low channel

mobility in 4HSiC MOSFETs.2 6 Saks et al. have reported

the measurements of D it near both band edges in 4H and

6H SiC MOSFETs using the GrayBrown technique, and

have shown that D it near Ec is much higher in 4H com-

pared to 6HSiC MOSFETs.7

Generally, the D it can be sim-ply evaluated using the MOS capacitor. In the case of the

SiC MOS structure, since the D it in the upper half of the

band gap cannot be measured from the p-type MOS capaci-

tors due to the wide band gap, the n-type MOS capacitors are

used to measure the D it near Ec . The D it near Ec in the

n-type MOS capacitor is affected by the oxidation conditions

of the gate oxide.8,9 However, the channel mobility in the

n-channel MOSFET does not exhibit an obvious correlation

with the D it measured in the n-type MOS capacitor.10 It is

not clear that n- and p-type MOS interfaces have the same

D it profile, since the dopants are different in n- and p-type

SiC. In order to characterize the MOS interface in the

n-channel MOSFET using the n-type MOS capacitor, it is

necessary to clarify whether the n-channel MOSFET and the

n-type MOS capacitor have the same D it profile.

For the SiC MOSFET, threshold voltage for the strong

inversion Vth drastically varies with temperature due to the

large number of D it near Ec .

6,11

The D it can be roughlyestimated from the variation of Vth with temperature. There-

fore, we expect that a comparison of the temperature depen-

dence of the Vth and the D it extracted from the n-type MOS

capacitors will clarify whether the D it profile in the n-type

MOS capacitor can represent that in the n-channel MOSFET.

EXPERIMENTAL PROCEDURE

4H and 6HSiC 0001 wafers used in this study were

purchased from Cree Research Inc. Doping concentration

(NAND) of the epitaxial layers was about 51015 cm3.

MOSFETs were fabricated on p-type wafers. Length and

width (L/W) of the channel region were 10/50 and 200/200m. Source and drain regions were formed by phosphorous

ion implantation at 500 C with a total dose of 7

1015 cm2, followed by annealing at 1500 C for 5 min in

Ar ambient. Surface cleaning before oxidation was done by

RCA cleaning, sacrificial oxidation, and HF dip. The gate

oxide was grown by thermal oxidation in dry or wet O2atmosphere at 1200 C, and following Ar annealing for 30

min, resulted in a thickness of 40 nm. Gate and source/

drain contacts were formed by aluminum deposition. The Vthof MOSFETs were measured in the temperature range be-

a Author to whom correspondence should be addressed; electronic mail:

[email protected]

JOURNAL OF APPLIED PHYSICS VOLUME 91, NUMBER 3 1 FEBRUARY 2002

15680021-8979/2002/91(3)/1568/4/$19.00 2002 American Institute of Physics

Downloaded 11 Jul 2006 to 132.234.251.211. Redistribution subject to AIP license or copyright, see http://jap.aip.org/jap/copyright.jsp


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tween 150 and 150 C. MOS capacitors were fabricated on

n-type wafers. The oxidation conditions of the gate oxide

were the same as those for the MOSFETs. Combined high

low frequency capacitancevoltage measurements were per-

formed to evaluate the D it near Ec in n-type MOS capacitors

using the Keithley KI-82 system. The step voltage and the

delay time for the measurement were 50 mV and 10 s, re-

spectively.

RESULTS AND DISCUSSION

Figure 1 shows the D it profiles near Ec obtained fromthe n-type 4H and 6H SiC MOS capacitors with a gate

oxide formed in dry or wet atmosphere. The D it profiles are

apparently different in these four samples. The SiC/SiO2 in-

terfaces of 4HSiC have a higher D it at the shallow energy

level than those of 6HSiC, while the SiC/SiO2 interfaces of

wet oxidation samples have a higher D it at the deep energy

level than those of the dry oxidation samples. It is confirmed

that the D it profiles measured in the n-type SiC MOS capaci-

tors are affected by the polytypes and the oxidation methods.

Our previous study has shown that the peak value of the

field effect FE mobility FE is almost independent of these

oxidation methods dry, wet .10 In order to examine the in-

fluence of the polytypes and gate oxidation methods in de-tail, gate voltage dependence of the FE was measured. Fig-

ure 2 shows FE as a function of gate voltage VG in 4H and

6HSiC MOSFETs. The VG for the measurement ranges

from 0 to 30 V. Solid and dashed lines represent the charac-

teristics of dry and wet oxidation samples, respectively. The

FE was calculated from the following formula at the drain

voltage VD of 0.1 V:

FEIDVG

1

CoxVD

L

W, 1

where ID is the drain current and Cox is the oxide capaci-

tance extracted from MOS capacitors. Comparing the FE in

4H and 6HSiC MOSFETs, the FE in the 6HSiC MOS-

FET is much higher than that in the 4HSiC MOSFET. Fur-

thermore, regarding the gate voltage dependence of the FE ,

apparently different behaviors are observed. In the 6HSiC

MOSFET, two peaks exist around the gate voltages of 10 and

25 V, suggesting the existence of two Vth . On the other hand,

comparing the FE in dry and wet oxidation samples, they

exhibit a quite similar behavior.

In Fig. 3, the peak values of the FE are compared with

the number of interface state Nit in the n-type MOS capaci-

tor. The Nit is the summation of the D it within the energyrange of 0.20.4 eV from Ec in Fig. 1. 6HSiC MOSFETs

have a higher FE and lower Nit than 4HSiC MOSFETs,

suggesting that polytype dependence of the FE can be ex-

FIG. 1. Energy distribution of interface state density D it near the conduction

band edge energy Ec in n-type 4HSiC open symbols and 6HSiC full

symbols MOS capacitors. The gate oxides are grown by dry or wet oxida-

tion. FIG. 2. Field effect mobility FE as a function of gate voltage in 4H and

6HSiC MOSFETs. Solid and dashed lines represent FE in dry and wet

oxidation samples, respectively.

FIG. 3. Relationship between the number of interface state Nit near Ec in

n-type MOS capacitors and the FE in the MOSFETs. The Nit is the sum-

mation of interface state density D it within the energy range of 0.20.4 eV

from Ec .

1569J. Appl. Phys., Vol. 91, No. 3, 1 February 2002 Harada et al.



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plained by the D it in this energy range. In contrast, dry and

wet oxidation samples in the same polytype exhibit different

values ofNit , although their FEs are almost same. Thus, the

lower Nit within the energy range of 0.20.4 eV from Ec in

the n-type MOS capacitors does not always bring about the

higher FE in the n-channel MOSFET.

In order to justify the use of the n-type MOS capacitors

to measure the D it profiles near Ec , the temperature depen-

dence of the Vth was measured and compared with the D itextracted from the n-type MOS capacitors. The theoretical

threshold voltages Vcal were calculated from the following

formula, neglecting the contribution of charges in the inter-

face traps and the fixed charges:

VcalVFB2B2

Cox2S0NA 2B 2

with a bulk Fermi potential (B)

BKT

qln

P

n i, 3

where VFB is the flatband voltage determined from the dif-

ference between the work functions of the gate metal and the

semiconductor, P is the free hole concentration,12 n i is the

intrinsic carrier density, and NA is the acceptor concentration.

When the charges in the interface states and the fixed charges

are included, the Vth is described as follows:

VthVcalQ itQf

Cox, 4

where Q it and Qf are charges in the interface states and the

fixed charges, respectively. The surface Fermi potential at

VGVth (S2B) varies with temperature as can be seenin Eq. 3 . Therefore, if Qf is assumed to be constant with

temperature, the Nit within the energy range where the sur-

face Fermi level sweeps with temperature is described as

follows:

Nit VthVcal Cox

q, 5

where (VthVcal) is the variation of ( VthVcal) with the

temperature. Figure 4 a shows the temperature dependence

of Vth in 4HSiC MOSFETs in the temperature range be-

tween 150 and 150 C. The Vth of Si MOSFET is also

shown in the same figure for comparison. The Vth was ex-tracted from the IDVG plot at VD10 V in the saturationregion. The Vth of Si MOSFET is in good agreement with the

Vcal , indicating that the charges in the interface traps and

fixed charges are mostly negligible. In contrast, the Vth of

4HSiC MOSFETs are considerably higher than the Vcal at

lower temperatures, and drastically decreases with increasing

temperature. Comparing dry and wet oxidation samples,

higher Vth is obtained from the wet oxidation sample. As

shown in Fig. 4 b , the temperature dependence of Vth in

6HSiC MOSFETs is similar to that in 4HSiC MOSFET.

The Vth of both dry and wet oxidation samples decrease with

increasing temperature and higher values are obtained from

the wet oxidation sample. These values and their variations

with temperature are somewhat smaller than those for 4H

SiC.

For 4H and 6HSiC MOSFETs with NA of 51015 cm3, the surface Fermi level at VGVth sweeps

from 0.2 to 0.4 eV from Ec when the temperature increases

from 150 to 150 C. Below this temperature range, the

variation of the surface Fermi level is very small. (VthVcal) between 150 and 150 C reflects Nit within the en-

ergy range of 0.20.4 eV from Ec . Figure 5 compares the

(VthVcal) with the Nit within the energy range of 0.20.4

eV from Ec . A linear relationship between (VthVcal) and

Nit indicates that the behavior of Vth with temperature re-

flects the Nit in the n-type MOS capacitor. From this result,

we conclude that the D it profiles near Ec in the n-channel

MOSFET can be measured using the n-type MOS capacitor.

FIG. 4. Temperature dependence of threshold voltage Vth for: a 4H and

b 6HSiC MOSFETs. In a Vth of Si MOSFET is also shown for com-

parison. Lines represent the theoretical threshold voltage Vcal .

1570 J. Appl. Phys., Vol. 91, No. 3, 1 February 2002 Harada et al.



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As shown in Fig. 3, the FE does not depend on the oxida-

tion conditions, whereas Nit measured within the energy

range of 0.20.4 eV from Ec depends on them. This indi-

cates that the D it within the energy range of 0.20.4 eV from

Ec is not the major cause for the low FE in the 4HSiC

MOSFET. It has been reported that the D it increases very

rapidly within the energy range of 0.2 eV from Ec in the

4HSiC MOSFET.7 Therefore, we suppose that the D itwithin the energy range of 0.2 eV from Ec has a great influ-

ence on the FE , and that the influence of the oxidation

method of the gate oxide on the D it within the energy range

of 0.20.4 eV from Ec is different from that in the energy

range of 0.2 eV from Ec . In order to discuss the correlationbetween the D it and the FE using the n-type MOS capaci-

tors, it will be necessary to measure the D it within the energy

range of 0.2 eV from Ec .

CONCLUSIONS

In this study, we fabricated 4H and 6H SiC MOSFETs

with the gate oxide grown by dry or wet oxidation, and ex-

amined the temperature dependence of Vth to clarify the re-

lationship between the channel mobility and the D it profile in

SiC MOSFETs. The linear relationship between the VthVcal variation from 150 to 150 C and the value of Nitwithin the energy range of 0.20.4 eV from Ec revealed that

the D it profile near Ec in n-channel SiC MOSFET can be

represented by that in the n-type SiC MOS capacitor. The

channel mobility did not show obvious correlation with the

value of Nit within the energy range of 0.20.4 eV from Ec .This result suggests that the interface states within this en-

ergy range are not the major cause for the low channel mo-

bility in the SiC MOSFET.

ACKNOWLEDGMENT

This work was performed under the management of FED

as a part of the METI Project R&D of Ultra-Low-Loss

Power Device Technologies supported by NEDO.

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FIG. 5. Relationship between the Nit within the energy range of 0.20.4 eV

from Ec in the n-type MOS capacitors and the variation of the Vth Vcalwhen the temperature increases from 150 to 150 C.

1571J. Appl. Phys., Vol. 91, No. 3, 1 February 2002 Harada et al.


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