January 28th, 2010Clermont Ferrand, Paul Scherrer Institut DRS Chip Developments Stefan Ritt.

January 28th, 2010Clermont Ferrand,

Paul Scherrer Institut

DRS Chip Developments

Stefan Ritt

Stefan Ritt January 28th, 2010Clermont Ferrand,

Agenda

• DRS4 chip has been developed at PSI and has been shown at this Workshop in Lyon 2008

• No new chip development since 2008, but –deployment of 3000 channels in the MEG experiment–many chips and boards shipped worldwide

• Experiences in designing large systems• Some new ideas about next generation

DRS4Chip

DRS4Chip

Evaluation BoardEvaluation Board


DRS4

• Fabricated in 0.25 m 1P5M MMC process(UMC), 5 x 5 mm2, radiation hard

• 8+1 ch. each 1024 bins,4 ch. 2048, …, 1 ch. 8192

• Differential inputs/outputs

• Sampling speed 500 MHz … 6 GHz

• On-chip PLL stabilization• Readout speed

30 MHz, multiplexedor in parallel

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

STOP SHIFT REGISTER

READ SHIFT REGISTER

WSROUT

CONFIG REGISTER

RSRLOAD

DENABLE

WSRIN

DWRITE

DSPEED PLLOUT

DOMINO WAVE CIRCUIT

PLL

AGND

DGND

AVDD

DVDD

DTAPREFCLKPLLLCK A0 A1 A2 A3

EN

AB

LE

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8/MUXOUT

BIASO-OFS

ROFSSROUT

RESETSRCLK

SRIN

F U N C T IO N A L B L O C K D IA G R A M

MUX

WR

ITE

SH

IFT

RE

GIS

TE

R

WR

ITE

CO

NF

IG R

EG

IST

ER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

MUX

LVDS


DRS4 @ MEG

4 x DRS4LMK03000

32 c

hann

els

3000 Channels


DRS4 around the world


Worldwide Community

• 750 chips and 50 evaluation boards shipped worldwide

• Community forming• sharing ideas• helping each other• more elaborate chip characterization• helps to reduce chip prices• motivate other groups to develop their own SCA

• Pushing the field of SCA technology forward

• 750 chips and 50 evaluation boards shipped worldwide

• Community forming• sharing ideas• helping each other• more elaborate chip characterization• helps to reduce chip prices• motivate other groups to develop their own SCA

• Pushing the field of SCA technology forward


The problem of big systems

t=1 ps

t=1 pshow to synchronize?

Machine RFMachine RF


Jitter Measurement 1

Use LeCroy WavePro 7300A (3 GHz, 20 GSPS) with analysis statistics:


Problems

Low Gain:

Scope noise (6-7 bit)leads to timing jitter

overestimation

High Gain:

Not enough samplepoints in window

underestimation

Single ended probe: 20 psDifferential probe: 2 psSingle ended probe: 20 psDifferential probe: 2 ps


Jitter Analysis with SA

carrier frequency (e.g. 20 MHz)

85 k$85 k$


Quarz Jitter


PLL Behavior

Quartz through FPGA:

Quartz through DCM:

Improvement 9 ps 1.3 psif FPGA clock

was turned off!

Improvement 9 ps 1.3 psif FPGA clock

was turned off!

9ps

23ps


First Results

Measured Jitter WavePro

7300AAgilent E5052A

1 kHz – 20 MHz

Data Sheet

66 MHz Quartz Oscillator 8 ps 3.8 ps <1 ps

66 MHz Quartz through FPGA 18 ps 9 ps

66 MHz Quartz through DCM 23 ps 22 ps 100 ps

Quartz

FPGA

DCM


Jitter with differential signals

voltage noiseband of signal

timing jitter arising from voltage noise

timing jitter is much smallerfor fasterrise-time

Single Ended Differential

+ -


Differential Signals through FPGA

Quartz

FPGA

DCM

Differential clocks won’t help!Differential clocks won’t help!

VDD/2

t’t

VDD noise


DRS4 @ MEG

Temperature StabilizedMaster Quartz

LVDS fan-out

LVDS fan-out LVDS fan-out

20 MHz

200 low jitter LVDS lines200 low jitter LVDS lines

Is the jitter low enough or should we use a jitter cleaner?Is the jitter low enough or should we use a jitter cleaner?


LMK03000

20 MHz1.2 GHz

1.56 MHz

240 MHz

LMK03000 Clock Conditioner(National Semiconductor)

LMK03000 Clock Conditioner(National Semiconductor)

Jitter: 400 fsJitter: 400 fs


Measurement with test board

FPGAoutput


Phase Jitter after cleaner

National Semiconductor Application Note AN-1734


Timing Big Systems II

Channel 0

Inverter Chain

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

PLLLMK03000

Experiment wideglobal clock

SCAChip

•Global clock locks all DRS4 PLLs to same frequency and phase

•Residual PLL jitter: 25 ps

•Even better timing can be obtained by direct clock sampling: 2 ps

•MEG Experiment: Single LVDSclock distributed over 9 VMEcrates


Global Timing 1

12

0 LMK03000MEGClock

20 MHz

FPGA

DRS4

REFCLKPLL

CH9240 MHz1

20

EN

EN EN

120


Global Timing 2

12

0 LMK03000MEGClock

20 MHz

FPGA

DRS4

REFCLKPLL

CH9240 MHz1

20

EN

EN EN

120

Driven by FPGAmissing MEG clock

Driven by FPGAmissing MEG clock


Global Timing 3

12

0 LMK03000MEGClock

20 MHz

FPGA

DRS4

REFCLKPLL

CH9240 MHz1

20

EN

EN EN

120

Driven by MEG clockDriven by MEG clock


Synchronization of clock chips

1.2 GHz

1.56 MHzChip 1

1.56 MHzChip 2

n * 0.83 ns

SYNC & 20 MHz

• SYNC has to arrive on all board within 50 ns trigger bus• 20 MHz MEG clock has to arrive on all boards within 0.83 ns

• SYNC has to arrive on all board within 50 ns trigger bus• 20 MHz MEG clock has to arrive on all boards within 0.83 ns

20 MHz

50 ns


What we learn from LMK03000

• Differential inverter chain VDD noise cancels

• Use only small VCO rangeLMK03000: 1185-1296 MHz

• Use partly internal andexternal loop filter

• Use separate VDD and GND for PLL

• use LDO on chip

Consider fo

r next g

eneration SCA desig

n

Consider fo

r next g

eneration SCA desig

n


Away from crate-based systems

1 k$/slot

1 k$/slot

fiberoptics

G. Varner: BLAB2 readoutsystem for f-DIRC

G. Varner: BLAB2 readoutsystem for f-DIRC

Pre-amp

Pre-amp GBit

Ethernet

WaveDREAMBoard (PSI)

WaveDREAMBoard (PSI)

GBitEthernet


Next Generation SCA

• Low parasitic input capacitance High bandwidth

• Large area low resistance bus, lowresistance analog switches high bandwidth

Short sampling depth

• Digitize long waveforms

• Accommodate long trigger delay

• Faster sampling speed for a given trigger latency

Deep sampling depth

How to combinebest of both worlds?

How to combinebest of both worlds?


Cascaded Switched Capacitor Arrays

shift registerinput

fast sampling stage secondary sampling stage

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

• 32 fast sampling cells (10 GSPS/130nm CMOS)

• 100 ps sample time, 3.1 ns hold time

• Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz)

• Shift register gets clocked by inverter chain from fast sampling stage

• 32 fast sampling cells (10 GSPS/130nm CMOS)

• 100 ps sample time, 3.1 ns hold time

• Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz)

• Shift register gets clocked by inverter chain from fast sampling stage


How is timing resolution affected?

voltage noise u

timing uncertainty tsignal height U

rise time tr

dBss

r

sr

rrr

ffU

u

f

t

U

u

ft

t

U

ut

nU

ut

U

ut

33

1

number of samples on slope

dBr ft

33

1


How is timing resolution affected?

dBs ffU

ut

33

1

U u fs f3db t100 mV 1 mV 2 GSPS 300 MHz 10 ps

1 V 1 mV 2 GSPS 300 MHz 1 ps

100 mV 1 mV 10 GSPS 3 GHz 1 ps

today:

optimized SNR:

next generation:

includes detector noise in the frequency region of the rise time

and aperture jitter


Conclusions

• SCA community growing!

• Building big systems with O(ps) accuracy is tough but possible

• New generation of SCA chips on the horizon

January 28th, 2010Clermont Ferrand, Paul Scherrer Institut DRS Chip Developments Stefan Ritt.

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Transcript of January 28th, 2010Clermont Ferrand, Paul Scherrer Institut DRS Chip Developments Stefan Ritt.