JA108 Datasheet_v1.8

JA108 - Universal Java Accelerator

JA108 - Universal Java AcceleratorCharacteristics• Single chip solution that enables Java software to

execute faster and conserve system energy- Hardware accelerated execution of Java bytecode instructions

- Low power 0.18 micron CMOS logic- Clock frequency to 100 MHz- Integrated power management- Interfaces to asynchronous 16 bit SRAM and Flash

memory, including page mode access support- Microcode architecture supports in-field updates- Internal scan with JTAG for testability- 4K byte 2-way set associative Java bytecode instruction cache

- 2K byte 2-way set associative write-through data cache with a 4 word write-back buffer

• Software kernel enables operation with any Java Virtual Machine (JVM)- Support for adapting any third-party JVM

• Packaging- 128 pin µBGA, 10 mm x 10 mm, 0.8 mil pitch- Custom packaging available

Features• 15X to 60X acceleration of Java software• Zero additional memory required• Power-saving standby and sleep states

• Compatible with any embedded microprocessor, SoC and mobile handset chipsets for: GSM, GPRS, CDMA, WCDMA, PCS and PHS

• Ready support for Sun Microsystems J2ME CLDC™ VM (KVM)

• Compliant with all Java standards• Clock doubling Phase Lock Loop (PLL)• JTAG support

Benefits• Transparent system integration

- No changes to the operating system kernel- No changes to legacy software and applications- No new development or debugging tools required- No additional glue logic- No additional memory required

• Quick time to market- Unique memory bus interface affords fast design-in- Leverages investments in system software, legacy application software, development tools and in-house expertise

• Responsive and consistent execution of Java soft-ware

• Reduced system energy usage when executing Java software

• Seamless acceleration of any Java Virtual Machine- Sun Microsystems authorized- Independently developed

1. General DescriptionThe JA108 is a stand-alone chip based on Nazomi's

KChip™ family of performance boosting solutions forJava™ technology. It delivers fast and efficient execution

JA108

Accelerator

System

Memory

Data

Address

Control

Data

Address

Control

Host

Rev. 1.8 NAZOMI Communications, INC. CONFIDENTIAL - 1 -


of intermediate languages such as Java software com-piled to Java bytecode instructions. The JA108 has beencarefully designed with a universal SRAM/Flash memoryinterface for fast adaptation into any system. The combi-nation of faster execution and reduced memoryaccesses significantly lowers overall system-level energyusage when running Java software compared to tradi-tional Java Virtual Machine implementations using a soft-ware interpreter.The JA108 easily interfaces directly to typical memorysystem designs and is fully transparent to all system soft-ware providing its benefits without requiring any portingor new development tools. Memory transactionsbetween the host microprocessor (“HOST”) and systemmemory pass through the JA108. Only the JVM needs tobe modified to drive Java bytecode execution into theJA108, all other system components and software areunaware of the JA108’s presence. This allows any andall commercial development tools, operating systemsand native application software to run as-is without anychanges and without requiring any new tools or software.

The JA108 directly accesses system memory to executeJava bytecode instructions. While the HOST servicesinterrupts, the JA108 may continue executing, contribut-ing to the system's speed-up of Java software execution.When not executing bytecodes, the JA108 is placed intoa power-saving state.

2. Java Bytecode InstructionsThe JA108 executes most of the Java instructions withinits hardware. Table 1 on page 2 and Table 2 on page 3list the bytecodes that are executed for J2ME CLDCVMK Virtual Machine (KVM). Bytecodes that are not exe-cuted by the JA108 hardware are executed by softwarethat runs on the HOST, using a synchronized a callbackmechanism.The JA108 software kernel detects callback requestsfrom the JA108 and invokes the appropriate bytecodeexecution routine to run on the Host. Bytecode executionwithin the JA108 is driven by the microcode, allowing theJA108 to accelerate any JVM, unique quick-bytecodeimplementations and even custom bytecodes.

Table 1: J2ME CLDC VM Bytecode Instructions Executed by the JA108

Java bytecode instructions executed by the JA108 chip

Constant Loads: aconst_null, iconst_ml, iconst_x, lconst_x, bipush, sipush

Local Variable Load: iload, lload, aload, iload_x, lload_x, aload_x

Load from Constant Pool: ldc, ldc_w, ldc2_w

Local Variable Store: istore, lstore, astore, istore_x, lstore_x, astore_x

Stack Operations: pop, pop2, dup, dup_x1, dup2, dup_x2, dup2_x1, dup2_x2, swap

Arithmetic: iadd, ladd, isub, lsub, imul, lmul, ineg, lneg, iinc

Logic: ishl, lshl, ishr, lshr, iushr, lushr, iand, land, ior, lor, ixor, lxor

Type Conversion: i2l, l2i, i2b, i2c, i2s, wide

Control Flow: nop, lcmp, ifeq, ifne, iflt, ifge, ifgt, ifle, if_icmpeq, if_icmpne, if_icmplt, if_icmpge, if_icmpgt, if_icmple, if_acmpeq, if_acmpne, ifnull, ifnonull

Unconditional Branch: goto, goto_w, jsr, jsr_w, ret, tableswitch, lookupswitch

Return: ireturn, lreturn, areturn, return

Array: arraylength, iaload, laload, aaload, baload, caload, saload, iastore, lastore, bastore, castore, sastore

Quickcodes: getstatic_quick, getstaticp_quick, getstatic2_quick, putstatic_quick, putstatic2_quick, getfield_quick, getfield2_quick, getfieldp_quick, putfield_quick, putfield2_quick



Quickcodes based on v1.0.2 and v1.0.3 of the SunMicrosystem’s J2ME CLDC VM (KVM) reference imple-mentation.

Table 2: J2ME CLDC VM Bytecode Instructions Executed by the Host

Java bytecode instructions executed in software on the HOST

Arithmetic (Integer): lmul, ldiv, lrem, idiv, irem,

Array and Objects: newarray, anewarray, multianewarray, new, checkcast, getstatic, putstatic, getfield, putfield, instanceof, aastore

Method Invocation: invokevirtual, invokespecial, invokestatic, invokeinterface

Thread Synchronization: monitorenter, monitorexit

Exception Handling: athrow

Reserved: Breakpoint

Quickcodes: invokevirtual_quick, invokestatic_quick, invokeinterface_quick, invokespecial_quick, new_quick, anewarray_quick, multianewarray_quick, checkcast_quick, instanceof_quick



3. JA108 Overview

The system diagram in Figure 1 above shows how theJA108 integrates into a typical device design as well asthe main functional units within the JA108. The JA108integrates between the HOST (a chip set or SoC thatincludes an embedded microprocessor) and the systemSRAM and/or Flash memory. From the perspective ofthe HOST and system software, the system SRAM and/or Flash memory is behind the JA108. Inclusion of aJA108 into a system has the following effects:• The JA108 has direct access to the system SRAM

and/or Flash memory• The HOST has transparent access to the system

SRAM or Flash memory through the JA108 (i.e., memory is behind the JA108)

• Data throughput delays through the JA108 need to be considered (refer to “HOST Interfacing” on page 7 for a discussion of the round-trip delay between the HOST and memory behind the JA108)

To start the JA108, the JA108 software kernel loads spe-cific registers in the JA108, including the starting addressof a Java bytecode instruction sequence. The software

kernel then starts the JA108 so that it can execute thesequence of Java bytecode instructions. The JA108 syn-chronizes with the HOST via a polling mechanism in theJA108 software kernel that runs on the HOST. While theJA108 is executing, the HOST waits in a polling loop untilit detects that the JA108 has requested servicing via theHOST callback synchronization mechanism. With eachcallback, the JA108 provides information that indicatesto the HOST whether it is requesting the HOST to pro-cess a bytecode not handled in the chip, or that all byte-codes have been executed or that an exception hasoccurred. When the software kernel initiates processinga callback, it places the JA108 into its standby power-saving state until callback processing has been com-pleted. Once all bytecode execution is complete, thesoftware kernel will put the JA108 into its sleep state.

The JA108 fetches the entire Java bytecode instructionincluding the operands from memory, through its internalcaches, and executes the instructions. Instructions anddata resident in the caches are executed faster and withreduced energy because system memory transactions

Figure 1: System Block Diagram with a JA108

HOST

Gnd JTAG

10 4

ClkRst#

IO0:IO15

A0:A23

BHE#,BLE#

CS0#, CS1#,CS2#

CS1

_J#

Async Flash& SRAMcombo

OE#, WE#

IO0_J:IO15_J

A0_J:A23_J

OE_J#, WE_J#

Async Flash pin RY/BY#

Hostinterface SRAM

Masterinterface

InterfaceRegisters JTAGPLL

D-Cache

BC-Cache

ModifiedJstar

ExecutionEngine

ADV#

ADV_J#

BHE_J#, BLE_J#

CS

2_J#

SRAM

RUN_Mode

PLL-BypVcc_1.8Vcc_3.366

CS0

_J#CS3#

Note: all memories canbe up to 16M x 16b

JA108 Chipselect



are minimized. Locally cached Java stack entries andvariables results in the fastest execution possible.Since the JA108 is a separate stand-alone Java byte-code execution engine, it can execute concurrently whilethe HOST is either waiting in its polling loop or process-ing interrupts (assuming the interrupt code is in theHOST’s cache or in memory which is not behind JA108).The JA108 may be halted during instances when theHOST has control of the bus or needs to access systemmemory. For example, if the HOST is executing an inter-rupt service routine from within its own cache, then theJA108 can concurrently execute bytecodes as the HOSTwill not be accessing memory via the bus. Similarly, ifJava bytecode instructions reside within the JA108'sinternal caches, the JA108 can concurrently executebytecodes even if the HOST needs to access systemmemory behind it.

3.1 JA108 CachesThe JA108 includes two internal caches: a 4K byte Javabytecode instruction cache and a 2K byte write-throughdata cache. The data cache also includes a 4 word write-back buffer. Both caches are 2-way set associativedesigns with cache line sizes of 16 bytes. The cachescan be invalidated in one cycle, under software controlper the options listed below. The caches and write-backbuffer are used exclusively by the JA108 and do nothave snooping capability. Memory and cache coherencyis the responsibility of software running on the HOST,which is handled within a JVM that has been adapted tooperate with the JA108.Within the JA108 is a register that controls the cachefunctions listed below. As with other interactionsbetween the JA108 and software running on the HOST,the software kernel provides API calls to manage thecache control register that manage the caches. Specificcache functions are:• Invalidate the entire instruction cache• Invalidate one line in the instruction cache• Invalidate the entire data cache• Invalidate one line in the data cache

3.2 Java Accelerator States and Power Management

The JA108 has integrated power management to mini-mize overall system level energy. Table 3 on page 5describes the power-saving features and operatingstates. Anytime the JA108 is not executing Java byte-code instructions, specific API calls within the softwarekernel are used to place the JA108 into one of its power-saving states, contributing to efficient energy conserva-tion.Referring to Figure 2:, you can see that the JA108 hasseveral states (described below). The JA108 automati-cally transitions between its running and standby states.In standby state, the JA108 draws minimal power as theJava engine core and associated components are idled(refer to Table 3 on page 5 for details on what compo-

nents are active and idle in each state). When the JVMis not running, the JA108 can be placed into its sleepstate.Once activated, the JA108 runs until any of the followingevents occur:1. Callback occurs.2. A memory conflict occurs when the HOST already

has control of the memory bus or seizes the bus because it needs to access system memory. This typically only occurs during interrupt and exception processing (explained further below).

3. The HOST halts the JA108 by forcing it into either its standby or sleep state.

Figure 2: State Diagram

Table 3: JA108 Java Accelerator Power Management

Operating States

Run Standby Sleep

Power Supply Current

400 �A/MHz

150 �A/MHz

leakage only

JA108 Java

Execution Engine

enabled disabled(internal clocks off)

disabled(internal clocks off)

internal Caches

enabled disabled(internal clocks off)

disabled(internal clocks off)

Internal registers

enabled enabled disabled(internal clocks off)

Memory Interface / Wake-up

Logic

enabled enabled enabled

Sleep: clocks off

Run: Clocks on

Standby: J Regs Clocks on

Wr Standby Adr or Soft Reset

or Hdwr Exception

Wr BCI_LOOP_REG

Wr Sleep Adr or Hdwr Reset

Hardware Reset Hardware Reset

Hardware Reset

Soft Reset

Wr Standby Adr



4. JA108 Operation

4.1 Pass-Through CapabilitiesThe JA108 automatically comes up with pass-throughactive after a reset, allowing the HOST to run and inter-act with memory behind the JA108. When pass-throughis active, the JA108 is invisible to the native operatingsystem and other software.

4.2 Initialization and ActivationThe JA108 must be initialized after a reset and on a perinvocation basis, as described below. Initialization isdone by loading specific values into the JA108's regis-ters.• Per Reset. The JA108’s reset can be asserted

asynchronously. Resetting the JA108 takes 8 cycles to complete, and should be done when the system or device is powered-up. The JA108 registers are set to specific addresses upon a reset (Refer to “Software Considerations” on page 10. for the spe-cific address and register values).The JA108 needs to be initialized after being reset, which includes pro-gramming the internal memory controller and setting the memory map offset registers. This initialization is handled by API calls within the software kernel. The JA108’s registers occupy a pair of 4K byte areas mapped into the system memory. Depending upon the device's memory map it may be necessary to move the JA108's registers by altering the default values (listed in the Software Considerations sec-tion). Changing the register offsets must be pro-grammed by a small routine inserted into the operating system’s own initialization handler (most operating systems support inclusion of custom device initialization). The JA108 includes a program-mable memory controller as an integral part of its memory interface circuitry. Its memory controller needs to be programmed in a manner typical that supports SRAM and/or Flash memory controllers. The actual programming is done by API calls within the JA108 software kernel with the specific memory addresses and memory timing parameters set according to each device's unique architecture and memory map.

• Per Invocation. The Java execution registers must be initialized each time the JA108 is invoked, which is handled by API calls within the software kernal that are intergrated into a modified JVM's initializa-tion sequence. Specifically, JA108 registers must be loaded with the address of where Java bytecode instructions are stored and where the Java heap is located.

When the system calls on its JVM to execute Java soft-ware, the JVM loads the starting address of a Java byte-code instruction sequence into the JA108's JavaProgram Counter (JPC). The JA108 software kernel thencauses the JA108 to begin executing (by writing to the

register: BCI_LOOP_REG). The software kernel thencauses the host to run a simple polling loop, that moni-tors the JA108 until the JA108 signals for callback sup-port.Monitoring the JA108 for callback servicing is done inone of two ways: by reading its callback register(BCI_LOOP_REG), or by reading the status of theRUN_Mode pin which can be connected to a GPIO bit.These two polling options are further discussed later inthis document (Refer to “High Performance Synchroniza-tion and Polling” on page 7.).When the JA108 is executing the contents ofBCI_LOOP_REG is zero and the RUN_Mode signal pinof the JA108 is high. The JA108 places non-zero datainto BCI_LOOP_REG and lowers the RUN_Mode pin tosignal that callback servicing is necessary. The data inBCI_LOOP_REG is used by the software kernel to takeaction; in other words, BCI_LOOP_REG contains a call-back ID. When the software kernel detects a callbackrequest it places the JA108 into its standby or sleepstate. Whenever the JA108 is in its standby or sleepstate, the RUN_Mode signal pin is low.

4.3 Sleep StateIn this state, all of the internal clock signals are disabledto conserve power. The JA108 is disabled (in its sleepstate) and transparent to all native resident software bydefault, and it is enabled when a properly adapted JavaVirtual Machine initializes it and calls on it to executeJava bytecode instructions. When the JA108 is in itssleep state, accesses to SRAM or Flash memory fromthe HOST pass through the JA108. Register contentsremain intact, even while in the sleep state, until deliber-ately changed, or until the chip is reset, as the JA108uses static registers.

4.4 Standby StateIn this state the internal clock is only applied to the inter-nal registers to conserve power. Similar to the sleepstate, when in the standby state, accesses to SRAM orFlash memory from the HOST pass through the JA108.All of the JA108's registers are accessible in the standbystate. The JA108's registers are used as the means tosynchronize operation between the HOST and hardwareJava bytecode instruction execution specific API callswithin the software kernel transition the JA108 in and outof its standby state contributes to how the JA108 pro-vides energy efficient operation.

4.5 Run State In this state, all of the internal clock signals are enabled.The JA108 is enabled when a properly adapted Java Vir-tual Machine initializes it and calls on it to execute Javabytecode instructions.All of the JA108's registers are accessible in the runstate. In the run state, the JA108 is actively executingbytecodes. The HOST is able to read from and write tomemory behind the JA108 and the HOST takes control



of the bus when HOST initiated memory accesses aredetected by the JA108.

4.6 HOST Interrupt and Exception HandlingThe JA108 does not disturb interrupt or exception pro-cessing, nor does it impose any latency. When an inter-rupt or exception occurs while the JA108 is processing,the HOST diverts to an appropriate handler routine with-out affecting the JA108. Upon return from the handler,the HOST returns execution to the JA108 software ker-nel and in turn resumes monitoring the JA108. Evenwhen the HOST takes over the memory bus, the JA108can continue executing Java bytecodes from its internalcache, which can continue so long as a system memorybus conflict does not arise.

4.7 Hardware Considerations

4.8 Endian Support

The JA108 has an automatic endian configuration mech-anism, allowing it to adapt to the endian-ness of the HOST. The JA108 determines the “endian-ness” of the HOST by writing a specific 32-bit value of 0x0000FFFF to the register: ENDIAN_REG. The endian setup should be the first initialization step, and is handled within the JA108 software kernel's initialization section.

4.9 Interfacing the JA108 to the Address BusThe JA108 looks to the HOST like a standard fast 16-bitword addressed SRAM device. The HOST must there-fore be programmed to address the JA108 in the samemanner as it would any standard 16-bit wide SRAM. TheHOST address bus (A0:A23) and the memory addressbus (A0_J:A23_J) present the address for a 16 bit datafield. For example, an address value of 0x000000 isword 0 representing bytes 0 and 1, and 0x000001 isword 1 representing bytes 2 and 3, and so on. To accessor write individual bytes in the 16 bit data field from theHOST, byte high enable (BHE#) and byte low enable(BLE#) signals are provided for addressing the high byte(IO8 :I015) and low byte (IO0:IO7), respectively. Thememory side of the JA108 also has the same addressingformat with its respective signals.

4.10 High Performance Synchronization and PollingThe JA108 synchronizes with a HOST using a pollingloop within the JA108 software kernel that runs on theHOST. A low power polling option is available that uses aspecific hardware signal (RUN_mode) from the JA108that can be interfaced to a general purpose I/O (GPIO)pin of the HOST. This method allows the HOST to syn-chronize by monitoring the state of an internal I/O pin,rather than poll by reading the status of a JA108 registerover the system bus. This is the most energy efficientmethod of synchronizing, provided that the HOST has anavailable GPIO pin. In either case, a simple software

polling loop must run on the Host to monitor the chosenGPIO pin or the JA108’s BCI_Loop register.The RUN_Mode signal pin and the JA108 software ker-nel have been designed to only support connection to aGPIO pin. While it is possible to use this signal to inter-rupt the HOST, doing so is not recommended for adapta-tion and performance reasons. The software kernel doesnot provide a means to integrate an interrupt service rou-tine with a JVM. Should using RUN_Mode as an inter-rupt be considered, then careful consideration must begiven to custom software adaptation, interrupt latencyand other related system design considerations.

4.11 Phase Lock Loop & Bus Clock FrequencyThe JA108 has a Phase Lock Loop (PLL) that generatesan internal core clock signal that is twice the frequency ofthe clock input. The JA108 is intended to receive the sys-tem bus clock as its clock input. The bus clock frequencycan be used direct or doubled by the PLL, which meansthat the JA108 executes either at the bus frequency or attwice the bus clock frequency.Because the JA108 has a maximum core operating fre-quency of 100 MHz, that means that the clock doublingoption can only be used in systems where the bus clockoperates at up to 50 MHz. Also note that the PLL has aminimum clock frequency of 25 MHz. The PLL can bebypassed allowing the JA108 to be clocked at up to 100MHz directly without using the clock doubling feature.The PLL requires 10 microseconds to lock after wakingup.

4.12 PLL Test ModeWhen CS1# and CS2# are both low (illegal in normaloperation) then the PLL Output (2X) will be put out onCS1_J# and the PLL Lock signal will be put out onCS2_J#.

4.13 HOST InterfacingAll accesses in and out of the JA108 are asynchronouswith respect to its clock. Referring to Figure 1 on page 4,it can be seen that the JA108 is positioned between theHOST and the system SRAM and/or Flash memory. Thismeans that all system memory accesses by the HOSTpass through the JA108. While fully transparent to allsystem software, small memory access delays are intro-duced for each direction. For read operations, the totaldelay is equal to the sum of the address assertion anddata acquisition delays. For write operations, the totaldelay is just the address assertion delay. The sum ofTADD and TI/OD represents total round-trip delay betweenthe HOST and memory behind the JA108.

Note: The address in to address out delay signal (TADD)includes the JA108’s internal mux switching delay.

4.14 SRAM and Flash Memory InterfacingThe JA108 readily interfaces to any system designedwith asynchronous SRAM and asynchronous Flash



memory with or without page mode capability. TheJA108 easily integrates into such designs because itlooks to the system and appears to the HOST to act likea fast SRAM. When page mode memory is used, burstsof 4 or 8 bus accesses are supported. The JA108 treatsFlash memory as read-only memory. Writing to Flashmemory by the JA108 is not supported and if attemptedwith cause a hardware exception. Writing to Flash mem-ory can only be done by the HOST through the JA108.Each register in the JA108 is not enabled until it hasbeen written to. The memory interface can generate several differentmemory transactions:• Read a 16 byte line, using page mode if available (8

bus transactions)• Read a 4 byte word (2 bus transactions)• Write a 4 byte word (2 bus transactions)• Write a 2 byte half-word (1 bus transaction)• Write a byte (1 bus transaction)The HOST must use the CS3# to select and read/write the JA108’s registers. The JA108 uses its ownmemory controller based on a 16-bit memory interface. Itaccesses memory directly via its Java Program Counter(JPC). As with any program counter, the JPC alwayspoints to the address of the next instruction to be fetchedand executed. This allows the JA108 to operate asyn-chronously and concurrently with regard to the HOST.The JA108 immediately switches to its pass-throughmode giving up the bus when the HOST accesses mem-ory. Any memory transactions aborted to grant the bus tothe HOST will be restarted.

4.15 JA108 Memory ConfigurationThe JA108 includes a programmable memory controller,that can control up to three (3) memory segments usingany of three chip select lines (CS0# - CS2#). Each mem-ory chip select (CS0#-CS2#) must be configured inde-pendently to support various memory devices accordingto the following parameters:• Memory size. The following sizes (in bytes) can be

accommodated per chip select: 256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M

• Page mode memory. The JA108 supports burst accesses of either four (4) or eight (8) accesses for Flash and SRAM.

• First access wait states. These wait states are used for the setup and first access for page mode memories, as well as for non page mode memories. Zero (0) to fifteen (15) wait states can be applied to accommodate memory access times. The number of wait states for a particular device can be deter-mined using formulas provided later in this docu-ment.

• Subsequent access wait states. These wait states are used for subsequent accesses after the first access has completed. Zero (0) to three (3) wait states can be configured for page mode accesses. The number of wait states for a particular device can

be determined using formulas provided later in this document.

• Device base address. Memory devices must be located on boundaries that are multiples of 4K bytes, where the lower 12 bits of the device base address are 0.

4.16 Wait State DeterminationBefore discussing wait state determination, it is neces-sary to more clearly understand how the HOST inter-faces to the JA108 and any memory located behind theJA108. Refer to Figure 3 on page 8, three memoryaccess paths are shown.• Memory path #1, is for JA108 internal memory and

internal register transactions between the HOST and the JA108.

• Memory path #2 is for memory transactions between the HOST and any memory situated behind the JA108. These transactions occur through the JA108. The JA108 adds delays to memory accesses when the HOST accesses memory behind the JA108. The delay has two components - the delay for the address to reach the memory, and (for read operations only) for the data to return to the HOST. Using formula #2 that follows and access times within the operating range of the JA108, at most one wait state will need to be added.

• Memory path #3, is for memory transactions between the JA108 and any memory situated behind the JA108.

Because both the HOST and the JA108 have program-mable memory controllers, it is necessary to properlyprogram both controllers. Access by the HOST to thememory behind the JA108 is independent of the internalJA108 memory controller (i.e. pass-through accesses)

Figure 3: Memory Access Paths

HOSTJA108

mempath #1

path #3

path #2 path #2



Formula 1: Host memory controller wait state formulafor memory access path 1:

Use this formula for the JA108 connected to CS3#.[1/ BCLK] + [(Nhost)/ BCLK] - tsdhost > tacc

tacc is the access time of the JA108.BCLK is HOST memory controller bus speed tsdhost is the setup time required by the HOST for reads, which is dependant upon the specific HOST.Nhost is the required number of wait states for the HOST to use.

Formula 2: Host memory controller wait state formulafor memory access path 2:

Use this formula to program the HOST’s memory con-troller when the HOST is accessing memory through theJA108 (path 2). [1/ BCLK] + [(Nhost)/ BCLK] - tsdhost - PTdelay > tacc

tacc is the access time of the SRAM and/or FLASH.BCLK is the HOST memory controller bus speed PTdelay is the pass through delay of the JA108 (refer to tI/OD and tADD).tsdhost is the setup time required by the HOST for reads. This is dependant upon the specific HOST.Nhost is the required number of wait states for the HOST to use.

Formula 3: JA108 memory controller wait state formulafor memory access path 3:

Use this formula to program the JA108’s memory con-troller so that it may access any memory behind it. Whenthe JA108 executes Java bytecode instructions, itaccesses SRAM and/or FLASH behind it (the HOST isnot involved in these accesses). The following formulashould be used to program the number of wait state val-ues for wait state 1 and wait state 2 in the JA108 (refer to“JA108 Page Mode Read Timing” on page 17 orFigure 11 on page 17 for information on wait states 1 and2). Wait state 1 is for the initial access, and wait state 2 isfor the subsequent burst accesses.

(1/Clk_int) + ((NJA108)/ Clk_int) - tsd > tacc

tacc is the access time of the SRAM/FLASH.Clk_int is the internal clock rate of JA108. - When PLL_Bypass=0, Clk_int = 2x Clk input - When PLL_Bypass=1, Clk_int=Clk inputNJA108 is the required number of wait states for the JA108 to use.tsd = is the setup time required by JA108 for reads.

4.17 JTAG SupportThe JA108 provides full industry standard (IEEE 1149.1compatible) JTAG boundary scan, however note that theTRST (the reset pin) is not brought out, but is connectedinternally to the Rst# pin.

Note: For information about IEEE 1149.1 Standard TestAccess Port and Boundary Scan Architecture refer to thefollowing Website: http://www.standards.ieee.org/catalog/olis/testtech.html

4.18 Interactions Between HOST Accesses and JA108 AccessesHost read/write operations behind the JA108 use eitherCS0#, CS1# or CS2#, while a JA108 read/write usesCS3#. In other words, CS3# is dedicated for use by theHOST to adress the JA108. The subtype of a Host reador write operation (byte, 2 byte, 4 byte (dual two byte), orburst) has no impact on the interactions. The only thingthat the subtype impacts is how long the JA108 is"locked-out" (i.e. a burst is a longer time then a byteread). Table 4 on page 9 shows Host and JA108Accesses.

Abort is an automatic action in which the 2:1 muxes thatcontrol the output on the _J pins switch to allow the Hostsignals to pass through immediately, reguardless of whatthe JA108 internal memory controller is doing. In fact,the internal memory controller discovers the abort action2 cycles after it has happened, due to the asynchronous.nature of switching. For example, the Host asserts CS0#to CS2# and the muxes switch immediately. Subse-quently it takes two more cycles to sync the informationto the memory controller's clock. JA108 read operations are always bursts of 16 bytes (8accesses), using burst mode where possible, unless thecache requesting the read is disabled in which case 4bytes are read (2 accesses). Again, if possible, burst

Table 4: Host and JA108 Acceses

JA108 No External Access

JA108 Read Operation (SRAM or FLASH)

JA108 Write Operation (SRAM only)

Host Read behind JA108 (no JA108 action0

Normal Host Read Opera-tion(No JA108 action)

Normal Host Read Opera-tion (JA108 read aborted)

Normal Host Read Operation (JA108 write aborted)

Host Write Operation behind JA108

Normal Host Write Opera-tion (No JA108 action)

Normal Host Write Opera-tion (JA108 read aborted)

Normal Host Write Opera-tion (JA108 write aborted)

Host Read Operation to JA108

Normal Host Read Opera-tion (No JA108 action)

Normal Host Read Opera-tion (Normal JA108 read)

Normal Host Read Opera-tion (Normal JA108 write)

Host Write Operation to JA108

NormalHost Write Opera-tion (No JA108 action)

Normal Host Write Opera-tion (Normal JA108 read)

Normal Host Write Opera-tion (Normal JA108 write)

Host no Access

No action Normal JA108 Read Operation

Normal JA108 Write Operation


http://www.standards.ieee.org/catalog/olis/testtech.html


mode is used. JA108 write operations can be either 8, 16or 32 bits in length and require one access for 8 or 16 bitaccesses and two accesses for 32 bit write operations.Also, each JA108 write cycle is double length, where thefirst half is just to get the address and data stable beforeasserting the write enable (WE) signal. Figure 4 onpage 10 shows a Generic Abort and Retry of a JA108Operation due to a Host passthrough.

Figure 4: Generic Abort and Retry of a JA108 Operation due to a Host Passthrough

Note: IO0_J:IO15_J, can be either JA108/Host or mem-ory values, depending on read/write; Delay to sync withJA108 mem ctlr clk, 3 cycle max.

4.19 Avoiding Bus CollisionsThe JA108 contains a delay circuit to prevent bus colli-sions that occur when the JA108 is attempting to readfrom memory while at the same time the HOST is writ-ing to memory. This delay is required to compensate forthe time it takes to turn-off the output drivers for mostmemories, which is 20 to 40 nS. Therefore, the JA108must inhibit turning on its output drivers until the mem-ory's drivers have gone to high impedance. This delay is programmable via software to give therequired delay. Care must be taken to not make thedelay so long as to violate data set-up time of the mem-ory.

Figure 5: Output Delay Timing

4.20 Software ConsiderationsThe JA108 has several shared registers that are mappedto specific memory locations that are at fixed offsetswithin the CS3# memory space (as is listed in Table 5 onpage 11). These registers are set and managed by codewithin the JA108 software kernel using specific API calls.For this reason detailed descriptions of the JA108's reg-isters is not provided.

5. Memory Organization

5.1 JA108 Accelerator Register MapCommunicating with the JA108's registers is done byasserting CS3# and reading from and writing to specificmemory addresses. The memory space used by theJA108 is 8K bytes, divided into two 4K byte blocks (theJNPC block and the JNPUC block). The JA108 registersare grouped into several categories, as follows:• Callback Support Registers• Java Instruction Loop (JIL) register• JSTAR Java Engine Registers• Miscellaneous Registers• General Purpose Registers

In Table 5 on page 11, two 4K byte memory spaces areused and mapped into the CS3 memory area, as follows:• The JNPC base plus the specific register addresses

should be located in a cached memory space if pos-sible. The default set on reset locates this group of registers at: 0xxxx40000

• The JNPUC base plus the specific register addresses must be located in uncached memory space. The default value set on reset locates this group of registers at: 0xxxx41000

IO0:IO15

A0:A23

OE#,WE#,ADV#,BHE#,BLE#

one of CS0# to CS2#

IO0_J:IO15_J

A0_J:A23_J

OE#_J,WE#_J,ADV#_J,BHE#_J,BLE#_J

CS0#_J-CS2#_J

JA108 Values Host Values



Host Values

Host Values

Host Values

JA108 Value Host Value

Passthru Muxes cutovers

JA108 Retry Values

JA108 Retry Value

JA108 Retry Values

JA108 Retry Values

Pt Mux select andpropagate delay

JA108 Mem Ctlr Clk Don't careetc

JA108 Values

JA108 Values

JA108 Values

JA108 Value

Memory Data JA108 Data

CS#

OE_J#

I/O15_J:I/O0_J

tPTDOV



Table 6 on page 11 illustrates an example memory orga-nization and the types of software and data that are likelyto be stored in each type of memory. Placement of theitems listed in the left hand (“SRAM”) column of Table 5is necessary so that the JA108 can access the byte-codes and data necessary for it to execute Java byte-code instructions.

5.2 Virtual Memory MappingIf the HOST has an MMU, then the operating systemrunning on the HOST must be setup such that virtualmemory equals real memory for all areas of memory thatthe JA108 will access as part of its Java processing. Theitems that the JA108 will need to access are in theSRAM and Flash memory as shown in Table 6 onpage 11.

.

6. Java Virtual Machine AdaptationFull details explicitly describing how to adapt a JVM tosupport the JA108 are beyond the scope of this docu-ment. Nazomi provides the requisite documentation andreference implementations of adapted versions of stan-dard JVMs - contact Nazomi for the JA108 Software andJVM Adaptation Guide. Nazomi provides a referencesoftware kernel for the Sun Microsystems J2ME CLDCVM (KVM), and Nazomi provides a toolkit to supportadaptatioin of any JVM to work with the JA108, includingindependently developed JVM implementations. Adapta-tion with a JVM is accomplished by following the subse-quent procedures listed below, with code supplied bythe JA108 software kernel:• Inserting the JA108 initialization code into the JVM's

own initialization sequence.• Removing the Java bytecode interpreter and redi-

recting the functionality for the remaining Java byte-code instructions that are not directly executed within the JA108's hardware into the callback mech-anism enabled by the JA108 software kernel. Addi-tionally, for the quick bytecodes, when the JVM modifies the bytecode to its quick form, the cache line within JA108's instruction cache holding the bytecode being modified ("quickified") must be inval-idated. The same is true when JVM reverses this process and restores the bytecode to its original form. The JA108 software kernel provides API calls to handle all of these situations.

Table 5: JA108 Register Memory Map

Host Microprocessor Address Space Register

relative to JNPUC

100-17C (R/W) General PurposeRegisters, 32 words

F0-FF Reserved

0C0-0DC (R/W) Callback SupportRegisters, alternative view

B0-BF Reserved

080-0AC (R/W) Msc Regs (12 words)

000-07C (R/W) JSTAR Java Execution Engine Registers32 words

relative to JNPC

20-5C (R/W) Java Instruction Loop Registers, 16 words

00-1C (R/W) Callback SupportRegisters, 8 words

Table 6: Example System Memory Organization

SRAM Flash

• Java Heap• Java Stack• Downloaded Java

class files (including the constant pool)

• downloaded Java applets/applications

• Java Runtime Envi-ronment (JRE)- Java Virtual Machine (JVM, CVM, KVM)- Java class libraries- Profile class librar-ies

• Downloaded Java class files (including the constant pool) intended to be saved as resident

• Downloaded Java applets/applications intended to be saves as resident

• Operating system & device drivers

• Native resident applications



• Adapting the garbage collector. The JVM's garbage collector must be adapted to invalidate the data cache within the JA108 before scanning the Java Heap or Java Stack to avoid cache coherency prob-lems. Specifically, the following actions must occur that are easily accomplished using an API function within the JA108 software kernel:

• Updating the current Java frame in memory by copying all cached Java stack entries from within the JA108 to the memory-based Java stack

• Invalidating the JA108's internal data cache• Invalidating the data cache of the HOST

6.1 JA108 ExceptionsWhile the JA108 is executing, if it detects either of fourerror conditions it generates specific callbacks that indi-cate the specific exception. These exceptions only applyto the JA108 while it is running. The error conditions are(1) an unaligned memory access, (2) attempting toaccess memory that does not exist, or (3) an attempt bythe JA108 to write to Flash memory. (4) Two chip selectsgoing low (active) for the same access. When an excep-tion occurs the JA108 halts all execution, enters into thestandby state, causing the Run_Mode pin to go Low andasserts a specific callback. Upon detecting the exceptioncallback, the software kernel performs recovery actionsand, if appropriate, causes the JVM to terminate.



7. JA108 Pin Functions

Table 7: Host Microprocessor to JA108 Interface Signal Descriptions

Signal Pin number Input/Output Function and Description

IO0 : IO15 D3, D1, E3, F4, F2, G1, H1, J1, H4, K2, L2, J4, K4, L4, K5, M5

IO 16-bit Data bus: This is a bi-directional data bus consisting of 16 lines used during access to SRAM/FLASH or JA108 Interface registers access. These are HOST data bus connected to the JA108. These are input to the HOST and output from JA108 when HOST reads data from the JA108. These are output from the HOST and input to the JA108 when HOST writes data to the JA108.

A0 : A23 J6, M7, K7, L8, K8, K9, M11, L11, L12, J10, H9, H10, G12, G9, F11, E12, D12, D11, D10, B12, C10, A11, A10, D8

I Address bus: The address from the HOST (to the JA108) is used for SRAM/FLASH or JA108 Interface registers access.

BHE# B8 I Byte High Enable: Active low, it indicates that the HOST demands access for data IO15:IO8.

BLE# B7 I Byte Low Enable: Active low, it indicates that the HOST demands access for data IO7:IO0.

OE# A6 I Output Enable: Active low, it indicates that the HOST wants to read data from the JA108. The JA108 uses this OE# to enable its out-put data. This signal works in conjunction with the WE# signal.

WE# C7 I Write Enable: An active low signal enables the drivers from the JA108 onto the HOST bus. If high, and OE# is low, then a read from the bus is enabled.

CS0# :CS3#

B5, B4, C4, J2 I SRAM/FLASH chip select lines: Active low, these are SRAM/FLASH memories chip select lines. The chip select CS3# is the only one used by the JA108 chip to compare its mapped base address for JA108 Registers.

ADV# A5 I Flash Address Valid: Active low, page mode address latch signal for Flash memory access.

RUN_Mode

G4 O JSTAR request: Active high, when high, the JA108 is busy execut-ing Java bytecode instructions. Upon transitioning to a low state, this pin can be used to signal to the HOST that it has completed execut-ing, a callback needs to be executed or an exception has occurred.



Table 8: JA108 SRAM Master Interface to Memory Signal Descriptions


IO0_J : IO15_J

D2, E4, E2, F3, F1, G2, H2, H3, L1, J3, K3, M2, M3, J5, L5, M6

IO 16-bits Data bus: This is a bi-directional data bus consisting of 16 lines. These are SRAM/FLASH data bus connected to the JA108. These are input to the JA108 and output from SRAM/FLASH when JA108 reads data.These are output from the JA108 and input to the SRAM/FLASH when JA108 writes data into the SRAM/FLASH memories.

A0_J : A23_J

L6, L7, M8, M9, L9, L10, M12, K10, K11, K12, J12, H11, G10, G11, F10, F9, E10, C12, C11, A12, D9, B10, B9, A9

O Address bus: The address is generated by the JA108. It is con-nected to the SRAM/FLASH. Whenever JA108 requires access to SRAM/FLASH the JA108 generates this address or whenever the HOST requires access to the system memory the JA108 passes the HOST generated address.

BHE_J# A8 O Byte High Enable: Active low, upper Byte access enable

BLE_J# D7 O Byte Low Enable: Active low, lower Byte access enable

OE_J# B6 O Output Enable: Active low, it indicates that the JA108 wants to read data from the SRAM/FLASH memories. The SRAM/FLASH memo-ries use this signal to enable its output data.

WE_J# A7 O Write Enable: Active low, it indicates that the JA108 needs to write data into the SRAM/FLASH memories. The SRAM/FLASH uses this signal to write data into it.

CS0_J#: CS2_J#

A4, C5, C3 O SRAM/FLASH chip select lines: Active low, these are SRAM/FLASH memories chip select lines generated by JA108.

ADV_J# D6 O Flash Address Valid: Active low, page mode address latch signal for Flash memory access.

NC K1 N/A Ball K1 must not be connected



Table 9: JA108 Accelerator Control Signal Descriptions


Rst# M10 I Reset signal: Active low. The JA108 chip resets to the known state.

Clk A1 I Clock is used for internal state machines and other JA108 func-tions.

Table 10: JTAG Signal Descriptions

Signal Pin Number Input/Output Function and Description

TMS C2 I Test Mode Select: User system

TCK B3 I Test Clock: User system

TDI C1 I Test Data In: User system

TDO A3 O Test Data Out: User system

Table 11: Power Signal Descriptions

Signal Pin Number Function and Description

Vcc_1.8 D5, C9, J9, F12, E1 Core power supplied to the internal logic of the JA108

Vcc_3.3 L3, C6, K6, J7, E9, J11

I/O Power: JA108 signal pin/pad power, which supplies power to signal pin-pads

Gnd M1, J8, G3, M4, B11, E11, C8, H12, D4

Ground

VCC_1.8_Clk A2 PLL Power: 1.8V for JA108 PLL circuit

Gnd_Clk B1 PLL Ground: Ground for JA108 PLL circuit



8. Timing Diagrams

8.1 Host Read and Write TimingFigure 6 on page 16 below shows the waveforms andtiming information that applies to the HOST reading datafrom the JA108 Java Accelerator. Similarly, Figure 7 onpage 16 below shows the waveforms and timing informa-tion that applies to the HOST writing data to the JA108Java Accelerator.

Figure 6: Host Read Timing

Figure 7: Host Write Timing

Figure 8 on page 16 shows the waveforms and timinginformation that illustrates the delays the HOST willexperience when reading from and writing to systemmemory through the JA108 Java Accelerator. The upperwaveform shows the latency for the memory to receiveaddress information from the HOST, which applies toboth reads and writes. In the case of writes, each write isskewed by the latency. The lower waveform shows thelatency for the HOST to receive data from memory. In thecase of reads the sum of both latency times are the totalread latency for the HOST to receive data from systemmemory.

Figure 8: Host Memory Delays

8.2 JA108 SRAM Read and Write TimingFigure 7 and Figure 8 show the waveforms and timinginformation that applies to the JA108 Java Acceleratorreading from and writing to system SRAM memory,respectively.

Figure 9: SRAM Read Timing

Figure 10: SRAM Write Timing

A23:A0

CS3#

tAA

I/O15:I/O0tDON

tCSZ

OE#

tOEZ

tAS

BHE#, BLE#tAOE

tBOE

tACS

tRC

I/O15:I/O0

A23:A0

WE#

CS3#

tAVWE

tPWE

tSCS

tSD

tADH

tHD

tAS

BHE#, BLE#

tSD

tHD

tAS

tWC

A 23_ J:A 0 _J

A 23 :A 0

I/O 15_ J:I/O 0_J

tA D

tI/O D

I/O 15 :I/O 0

C lk IN

tC lkH tC lkL tC lkRtC lkF

BHE_J#, BLE_J#

A23_J:A0_J

WE_J#

OE_J#

I/O15:I/O0_J

CS_J#

ProgrammableWait State1

tSD

tHD

Clk_Int

BHE_J#, BLE_J#

tAA

A23_J:A0_J

WE_J#

OE_J#

CS_J#

I/O15_J:I/O0_J

tWHD

tWHA



8.3 JA108 Page Mode Read TimingFigure 11 on page 17 below shows the waveforms andtiming information that applies to the JA108 Java Accel-erator reading system memory in page mode.

Note: If the page size is 8, the varying bits would be 0-2and N would be 0.

Figure 11: Page Mode Memory Read Timing

8.4 JTAG TimingFigure 12 on page 17 below shows the waveforms andtiming information that applies to the JA108 JTAGboundary scan.

Figure 12: JTAG Timing

WE_J#

OE_J#

CS_J#

ProgrammableWait State 1

ProgrammableWait State 2

Clk_Int

ADV_J#

tSD

tHD

tADHtAVVH

tVLVH

A23_J:AN_J

AN_J:A0_J

I/O15_J:I/O0_J

TCK

TDI

TMS

TDO

t TCKH t TCKL

t TDISU t TDIH

t TMSHt TMSSU

t TDOV t TDOZ



9. Electrical SpecificationsABSOLUTE MAXIMUM RATINGSStorage Temperature..................... -65°C to +150°CAmbient Temperature.................... -65°C to +70°CSupply Voltage.............................. -0.3 V to +3.6 VStresses above those listed under Absolute MaximumRatings may cause permanent device failure. Function-ality at or above these limits is not implied. Exposure toAbsolute Maximum Ratings for extended periods mayaffect device reliability.

OPERATING RANGESFor Commercial (C) DevicesTemperature (TA)............................. 0°C to +70°CCore Supply Voltage (Vcc_1.8).............. +1.8 V ±5%Signal and I/O Voltage (Vcc_3.3)....+ 3.3 V ±5%�jc=23.9 (C/W)

�jc represents the resistence to the heat flow from thechip to the package top case

Operating ranges define those limits between which thefunctionality of the device is guaranteed.

9.1 DC Electrical CharacteristicsAll DC characteristics are over commercial operating ranges unless otherwise indicated.

9.2 AC Electrical CharacteristicsAll AC characteristics are over commercial operating ranges unless otherwise indicated.

AC Measurement Notes:• VCC_3.3 = 3.135 for all measurements. The AC

characteristics must be derated for lower voltages.• Inputs driver at VCC_3.3 voltage for a “I” and 0.0V for

a ”0”• Input and output timing ends at VCC_3.3 / 2• Input rise and fall times < 5 nS• CL = 30 pF

Symbol Parameter Test Conditions Min Max Units

VCC_3.3 I/O Power Supply 2.2 3.3 V

VCC_1.8 Core Power Supply 1.7 1.9 V

IIL Input Leakage VCC_3.3 = Max. Vin = Vss to VCC_3.3 ±10 �A

IOL Output Leakage VCC_3.3 = Max. Vout = Vss to VCC_3.3 ±10 �A

VOH Output High Voltage VCC_3.3 = Min. IOH = -2mA 2.4 V

VOL Output Low Voltage VCC_3.3 = Min. IOL = 2mA 0.4 V

VIH Input High Voltage VCC_3.3-0.4

V

VIL Input Low Voltage 0.4 V

ICC Operating Current Fclk=50MHz, Fcore=100MHz(400 uA/MHz)

40 mA



10. Host - Read Cycle

11. HOST Write Cycle

Symbol Description Min Max Units

tRC Read Cycle Time 20 nS

tAA Address to Data Valid 15 nS

tACS CS Low to Data Valid 15 nS

tAOE OE Low to Data Valid 15 nS

tBOE BHE, BLE Low to Data Valid 15 nS

tAS Address set up to CS low 3 nS

tDON I/O Bus On from CS3 or OE 5 nS

tCSZ I/O Bus High Impedence from CS3 High 5 nS

tCEZ I/O Bus High Impedence from OE High 5 nS


tWC Write Cycle Time 20 nS

tAS Address set up to CS3 low 3 nS

tAS Address set up to BLE, BHE low 3 nS

tSA Address Valid to Write End 20 nS

tADH Address Hold from Write End 5

tPWE WE Pulse Width 10 nS

tOHA Data Hold from Address Change 2 nS

tSCS CS Low to Write End 10 nS

tSD Data Set-Up to Write End 8 nS

tHD Data Hold to Write End 2 nS

tZON Chip Select to Data On 3 nS

tCSZ Chip Select to Data High Impedance 3 nS



11.1 JA108 SRAM Read

11.2 JA108 SRAM Write

11.3 JA108 Page Mode Read


tSD Data Set-Up to CS 10 nS

tHD Data Hold from CS 0 nS

tAS Address set up to CS low 0 nS


tAA Address Valid to Data Valid 5 nS

tWHD Data Hold to WE high 5 nS

tWHD Address Hold to WE high 5 nS


tSD Data Set-Up to Address Change 10 nS

tHD Data Hold from Address Change 0 nS

tADH Address Hold to ADV High 10 nS

tAVVH Address Set Up to ADV High 10 nS

tVLVH ADV Pulse Width Low 10 nS



11.4 Miscellaneous Signals

11.5 JTAG Port

11.6 Output Delay Timing


ClkIN Clock Input Frequency, if clock doubling enabled 25 50 nS

ClkIN Clock Input Frequency, if clock doubling disabled 0 100 nS

PLL start up time 0 10 nS

tClkR Clock Input Rise Time (10-90%) 2 nS

tClkF Clock Input Fall Time (90-10%) 2 nS

tClkH Clock Input Low Time when PLL_Bypass=0 8 nS

tClkH Clock Input High Time when PLL_Bypass=0 8 nS

tClkH Clock Input Low Time when PLL_Bypass=1 4 nS

tClkH Clock Input High Time when PLL_Bypass=1 4 nS

tADD Address In to Address Out Delay 4 nS

tI/OD I/O In to I/O Out Delay 5 nS


tTCKH JTAG Clock High 500 MHz

tTCKL JTAG Clock Low 500 MHz

tTDISU TDI set up time to TCK 100 nS

tTDIH TDI hold time to TCK 100 nS

tTMSSU TMS set up time to TCK 100 nS

tTMSH TMS hold time to TCK 100 nS

tTDOV TCK to data out valid 50 nS

tTDOZ TCK to data out high impedance 50 nS


tPTDOV Passthru Data on Delay from CS# low when JA108 is reading from memory

Prog Prog nS



12. Mechanical Information and Physical DimensionsThe JA108 is available in one standard 128 pin package.• Micro BGA package measures 10mm x 10mm, with a 0.8 mil pitchOptional packaging is available. Contact Nazomi or your Nazomi representative for details.

12.1 128 Pin Micro BGA Mechanical Specifications

Figure 13: General View of the MicroBGA package



12.2 JA108 Accelerator 128 Pin Micro BGA Pinout

Figure 14: JA108 Top View Signals

Note: Ball K1 (NC) must not be connected.

A1 CORNER

CDEFGHJKLM

31 4 5 6 7 8 9 10 11 122

A19_JA21A22

A19

A17_J

A16

A15

Vcc_1.8

A12

Gnd

A10_J

A9_J

A8

A6_J

Gnd

A18_J

A17

Gnd

A14

A13_J

A11_J

Vcc_3.3

A8_J

A7

A6

A21_J

A20

A18

A16_J

A14_J

A12_J

A11

A9

A7_J

A5_J

Rst#

A23_J

A22_J

Vcc_1.8

A20_J

Vcc_3.3

A15_J

A13

A10

Vcc_1.8

A5

A4_J

A3_J

BHE_J#

BHE#

Gnd

A23

Gnd

A4

A3

A2_J

WE_J#

BLE#

WE#

BLE_J#

Vcc_3.3

A2

A1_J

A1

OE#

OE_J#

Vcc_3.3

ADV_J#

A0

Vcc_3.3

A0_J

IO15_J

ADV#

CS0#

CS1_J#

Vcc_1.8

IO13_J

IO14

IO14_J

IO15

CS0_J#

CS1#

CS2#

Gnd

IO1_J

IO3

RUN_Mode

IO8

IO11

IO12

IO13

Gnd

TDO

TCK

CS2_J#

IO0

IO2

IO3_J

Gnd

IO7_J

IO9_J

IO10_J

Vcc_3.3

IO12_J

Vcc_1.8_Clk

PLL_Byps

TMS

IO0_J

IO2_J

IO4

IO6_J

IO5_J

CS3#

IO9

IO10

IO11_JGnd

IO8_J

NC

IO7

IO6

IO5

IO4_J

Vcc_1.8

IO1

TDI

Gnd_Clk

Clk

AB



Figure 15: JA108 Bottom View Signals

Note: Ball K1 (NC) must not be connected.

A1 CORNER

CDEFGHJKLM

AB

23 1456789101112

A19_J A21 A22

A19

A17_J

A16

A15

Vcc_1.8

A12

Gnd

A10_J

A9_J

A8

A6_J

Gnd

A18_J

A17

Gnd

A14

A13_J

A11_J

Vcc_3.3

A8_J

A7

A6

A21_J

A20

A18

A16_J

A14_J

A12_J

A11

A9

A7_J

A5_J

Rst#

A23_J

A22_J

Vcc_1.8

A20_J

Vcc_3.3

A15_J

A13

A10

Vcc_1.8

A5

A4_J

A3_J

BHE_J##

BHE#

Gnd

A23

Gnd

A4

A3

A2_J

WE_J##

BLE#

WE#

BLE_J#

Vcc_3.3

A2

A1_J

A1

OE#

OE_J#

Vcc_3.3

ADV_J#

A0

Vcc_3.3

A0_J

IO15_J

ADV#

CS0#

CS1_J#

Vcc_1.8

IO13_J

IO14

IO14_J

IO15

CS0_J#

CS1#

CS2#

Gnd

IO1_J

IO3

RUN_Mode

IO8

IO11

IO12

IO13

Gnd

TDO

TCK

CS2_J#

IO0

IO2

IO3_J

Gnd

IO7_J

IO9_J

IO10_J

Vcc_3.3

IO12_J

Vcc_1.8_Clk

PLL_Byps

TMS

IO0_J

IO2_J

IO4

IO6_J

IO5_J

CS3#

IO9

IO10

IO11_J Gnd

IO8_J

NC

IO7

IO6

IO5

IO4_J

Vcc_1.8

IO1

TDI

Gnd_Clk

Clk



13. Product Identification and Ordering InformationNazomi standard products are available in several fea-ture and package options. The product identifier isformed using a combination of the elements below.JA108 - X 16/32 S/D B/F/D nnn

JA108: Product/device IDX: Version 16/32: Bus width - 16 bits or 32 bitsS/D: Bus interface/memory type

- Asynchronous SRAM and/or Flash memory- SDRAM and/or synchronous Flash memory

B/F/D: Package type (micro BGA, TQFP, Bumped Die) nnn: Speed in MHz

Valid CombinationsJA108 - X16SB



14. Revision History:Preliminary Revision 1.0, August 2001

Initial draft

Preliminary Revision 1.1, September 19, 2001Added pinout and corresponding diagrams.Updated timing diagrams and specifications.

Preliminary Revision 1.2, September 29, 2001Updated wait state formulas.Changed bytecodes to include returns executed in the JA108.

Fixed mA to uA errors in Power Management table.Other miscellaneous updates, edits, new diagrams and formatting changes.

Preliminary Revision 1.3, October 3, 2001Added information to 3.4.3 and 3.4.7.Added section 3.4.9Changed VCC_Clk to VCC_1.8_Clk in Table 10

Other miscellaneous updates, edits, new diagrams and formatting changes.

Preliminary Revision 1.4, October 8, 2001Added missing bytecodes to tables 1 and 2. Other miscellaneous updates, edits and formatting

changes.

Preliminary Revision 1.5, October 18, 2001Changed introduction under 2. Java Bytecode InstructionsUpdated bytecode tables 1 & 2Replaced System Block DiagramReplaced State Diagram

Text edits in 3.4.6 and 3.4.8 and Table 7; to update that no other memory is to be interfaced to CS3Replaced SRAM Read Diagram Replaced figs 11 & 12Other miscellaneous updates, edits and formatting changes.

Preliminary Revision 1.6, October 22, 2001Updated HOST read and write timing info: Figures 4 & 5, and Tables 6.2.1 & 6.2.2

Revision 1.7, January 2, 2001. Updated cross-references, timing diagrams andElectrical Specifications; added a section aboutThree State

Delay Control and a section about Interactionsbetween Host accesses and JA108 accesses.Unreleased datasheet.

Revision 1.8, January 4, 2001. Fixed formatting issues with timing diagrams and tables

Nazomi Communications, Inc.2200 Laurelwood Road Santa Clara, California 95054 USA

tel: (408) 654-8988 fax: (408) 654-2938www.nazomi.com, [email protected]

© 2001, Nazomi Communications, Inc. Nazomi, Nazomi logo and JSTAR are trademarks and/or service marks of Nazomi Communications, Inc. Otherbrands or products are trademarks of their respective holders. The specifications contained herein are subject to change without notice. Nazomiassumes no responsibility or liability arising out of the application or use of any legal information, product or service described herein except as expresslyagreed to in writing by Nazomi Communications Inc. Nazomi customers are advised to obtain the latest version of the device specifications before relyingon any published information and before placing orders for products or services. All rights reserved


JA108 Datasheet_v1.8

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Transcript of JA108 Datasheet_v1.8