J-C Brient LLR -2002 1 - Progress report on the ECAL prototype 2 - New informations on the cost of...

J-C Brient LLR -2002

1 - Progress report on the ECAL prototype

2 - New informations on the cost of the W-Si ECAL

3 - A proposal for a new design of the detector slab

4 - Conclusion

News of the CALICE - ECAL

Sampling calorimeter tungsten-silicon


Mid-march Mid-march A first sample of tungsten plates arrives at LLR => metrologyThe design of the front-end chip is fixed. First batch for test.End-march End-march Production of the final set of masks for the silicon wafers processingBeginning-April Beginning-April Start the production of a sample of 40 tungsten plates corresponding to the first technological test and first stack of prototypeApril-MayApril-May Processing of the first 25 silicon wafers (DC coupled) May-September May-September Processing and test of about 100 silicon wafers Final submission of the VFE chip for the prototype

Progress report on the prototype


1.37

1.38

1.39

1.4

1.41

1.42

1.43

1.44

1.45

thic

kn

ess (

mm

)

0 25 50 75 100 125 150 175 200 225 250 275 300 325 3500

75

length (mm)

width (mm)

thickness measurement (W n°1)1.44-1.45

1.43-1.44

1.42-1.43

1.41-1.42

1.4-1.41

1.39-1.4

1.38-1.39

1.37-1.38

1.37

1.38

1.39

1.4

1.41

1.42

1.43

1.44

1.45

1.46

thic

kn

ess (

mm

)

0 25 50 75 100 125 150 175 200 225 250 275 300 325 3500

75

length (mm)

width (mm)

thickness measurement (W n°2) 1.45-1.46

1.44-1.45

1.43-1.44

1.42-1.43

1.41-1.42

1.4-1.41

1.39-1.4

1.38-1.39

1.37-1.38

1.37

1.38

1.39

1.4

1.41

1.42

1.43

1.44

1.45

thic

kn

es

s (

mm

)

0 25 50 75 100 125 150 175 200 225 250 275 300 325 350

0

50

100

length (mm)

width (mm)

thickness measurement (W n°3)1.44-1.45

1.43-1.44

1.42-1.43

1.41-1.42

1.4-1.41

1.39-1.4

1.38-1.39

1.37-1.38

Metrology of the firstMetrology of the first3 tungsten plates made3 tungsten plates madeat LLRat LLR

It confirms the goodquality of the platesAs measured atIHEP and ITEP


Second configuration : using PCB solution + internal Frond End

(C / W) structure type H

Front End electronics

Silicon wafer

PCB

Cooling system

Aluminium

Signals output

Technological prototype – detector slab


PCB and Front End electronics details :Silicon wafer

Composite

Tungsten

PCB

Front End electronics

Flexible circuit

max 4.5 mm

Possible thickness for Front End electronics in this case : 4.5 mm

Physics prototype – detector slab


Physics prototype – cosmic tests

Cross-section

1st X-Y line(scintillating fibers)

2nd X-Y line(scintillating fibers)4 silicon wafer tested

Detector slab

1 mm

- Measurement surface : 128128 mm- Precision : 0.5 mm


0.1

ATLAS

CDF

GLAST

CMS

NOMAD

AMS01

CDF

LEP

DO

Sil

icon

Are

a (m

²)

100

1000

10

1

~ 2000 m²

DATA From H.F-W. Sadrozinski, UC-Santa Cruz

Moore's Law for Silicon Microstrip Detectors

Some interesting distributions (updated

recently)

About the cost of the W-Si ECAL

J-C Brient LLR -2002 DATA From H.F-W. Sadrozinski, UC-Santa Cruz

50

(Guestimate from H.S.)WARNING : cost (2010) < 2 $/cm² is for microstrip Processing

cost

/are

a (

$/cm

²)

Moore's Law for Silicon Detectors

Used in the TDR

BUT for ECAL W-Si Number of masks (x 0.5 )Industrial Yield (x 2 )

use of 8'' wafers ?

At least a factor 2 cheaper is expected

Cost 2 $/cm²

Blank wafer price 6''

< 2 $/cm²

1

2

10

4''

6''Wafer size

New elements for the cost of the ECAL


Re-calculate the estimation of cost, using the 2 €/cm²for the silicon

The cost of the ECAL is between 68 (20 layers) to 99 (40layers) M€

With the HCAL (i.e. version DHCAL) , the total cost of the calorimeter ranges from 129 (20 layers) to 175 (40 layers) MCH (CMS equivalent is 145 MCH)

1 - For the complete set ECAL + HCAL + Muon-CH ( MCH)

2 - The change of the geometry can further reduce the cost (length of barrel, internal radius,...)

CMS

Calice -FLC

216

132/178

18/40% reduction


Proposal for a new design of the detector slab

There is a very small available space for the VFE board (0.2x1x2cm³) Number of bonding/cm on the VFE board (about 160/cm) Some risk of pick-up noise (EMC) (coherent noise with 32 Mchannels) Number of wires/lines per cm in the flex (from diodes to VFE) Industrial feasibility for these processes seems difficult COST

Why ?

What else ?START from usual electronics industrial processes

1 - Use PCB with low density readout strip 2 - Keep industrial yield of the silicon diodes as high as possible 3 - Keep the small thickness of the total 4 - Keep the pad size open (from 0.5 to 1.5 cm) (SD, LD, ...or Rext. TPC)


Point 1 Multiplexing inside the alveolus VFE chip inside PCB low density cooling inside ??My comments UP to 200cm PCB low density is quasi-INDUSTRIAL (130 cm is already in the box)

Point 2 VFE and Si wafer have independent fabrication processIndustrial Yield (VFE is not ``bump bonded'' on the wafer) VFE chip on one side of PCB and diodes on the other

My comments - No thermal dissipation through the silicon wafer - Put a silicon wafer on one side and VFE chip on the other side is

INDUSTRIAL Point 3 Thin packaging , large area VFE chip Small overall thickness

My comments Thickness of the VFE-chip packaging 1mm is INDUSTRIAL

Point 4 The pad size depends on the power/channel , cooling systemAdaptable pad size and duty cycle of the VFE My comments The pad size can be as low as 0.5 cm


Calculation by J.Badier (LLR) With 5mW/c (which not so easy...)

1 - A cooling is NEEDED (at the middle of a module , T 400°)

2 - It is not so demanding for the thickness

Rectangular tube 1mm x 20 mm

bar/

m


Pad

Silicon wafer

PCB

Aluminium

Cooling tubeCooling tube

VFE chip 1.1 mm

1.0 mm

0.5 mm

Thermal contact

if needed

Conductive glue for electrical contact

AC coupling elementsif needed

powerline command line signal out

Budget (mm) 0.3 Al(sup) 0.1 Glue

1.0 VFE

2-3 cm

Transverse view - New design of the detector slab - ECAL

0.3 mm


A priori, all processes are uncorrelated (Si wafer , VFE chip , PCB,...) we could expect a good Industrial Yield

A priori, all processes are (quasi-) industrial

The mounting of the detector slab is a classical job for electronics industrial

Probably easier access to VFE board (not so trivial argument)

Technically, There are interesting challenges, BUT there are no orders of magnitude to gain Almost feasible today

What is the behaviour of a VFE chip when a 400 GeV e.m. Shower goes through ??

Advantages

Drawbacks

Could (and will) be rapidly tested

Advantages and drawbacks


Conclusions

New design of the detector slabNew design of the detector slabA lot of advantages - INDUSTRIAL processesThe extrapolation from VFE chip is reasonableThe extrapolation for the readout lines is reasonable

Costing of the calorimeter for FLCCosting of the calorimeter for FLC The project is in the extrapolation of the Moore's law for the cost and area of silicon to be processed Very probably, the processed silicon wafers will be <2$/cm ² Even with W-Si ECAL , there is an important cost reduction when compared to the equivalent in cost reduction when compared to the equivalent in CMSCMS

Progress report on the prototypeProgress report on the prototype Tungsten, first plates arrived, first sample soon in productionSilicon wafers, final masks have been designedVFE chip is in production for the first batch (test)

CA

LIC

E C

olla

bora

tion

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