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The Annual Conference for V93000 and V5000 Memory Series Users and Partners

September 23 – 24, 2008

Program Guide

It’s not our Voice.It’s yours.

Innovative minds.Brilliant possibilities.

Moderator: G. Dan HutchesonCEO, VLSI and Director, weSRCH.com

Topic: Achieving the TTx (Market, Volume, Yield): Meeting Exponentially Rising Expectations

As CEO of VLSI Research, Inc., Mr. Hutcheson is a recognized authority and well-known visionary for the semiconductor industry whose career experience spans more than thirty years. Much of his career has been spent advising companies in strategic and tactical marketing; business management; and manufacturing trends, productivity, and strategy. He has authored numerous publications, developed many industry models, and researched most aspects of the semiconductor industry. Mr. Hutcheson is probably best known for being the first to forecast an industry recession and for having developed the industry’s first cost-of-ownership model in the early eighties. He also built the first factory cost-optimization model in 1984. Similar models are now the mainstay of capital decision-making. Mr. Hutcheson is also a founder and director of weSRCH.com, the leading Science 2.0 website covering the Electronics, Medical and Solar disciplines. He holds a master’s degree in Economics from San Jose State and has completed additional engi-neering coursework from UC Berkeley.

Panelist: Octavio MartinezDirector of Test Engineering, QUALCOMM CDMA Technologies Division

Octavio Martinez is in charge of product and test development for QUALCOMM’S Single Chip solution product family, which inte-grates Digital, Analog, Power Management and RF into a single package. As Mixed Signal Test Engineering department manager, Mr. Martinez has been involved with ATE testing for over 16 years. He has experience in testing digital, analog, mixed signal and RF circuits. In his latest role, he is in charge of test development for SiP (System in Package) and SOC (System On Chip) devices that will keep QUALCOMM in the forefront of technology. Professional interests include ATE (Automated Test Equipment) IC testing, COT (Cost of Test), DFT (Design for Test) and DFM (Design for Manufacturability). Prior to joining QUALCOMM, Mr. Martinez worked for Brooktree Corporation as a mixed signal test engineer. He holds a B.S.E.E. and an M.B.A from San Diego State University.

Panelist: Scott GatzemeierProduct Integration Engineering Manager, IMFT

Scott Gatzemeier started his career at Micron as a Probe DRAM Engineer after graduating from the University of North Dakota in 1997 with an Electrical Engineering degree. He was promoted to Probe Flash Engineering Supervisor in 2001, with responsibility for Micron’s NOR Flash product lines, as well as for hiring and training engineers on probe test equipment and device operation. With the launch of the NAND Flash product line in 2004, he became Flash Engineering Manager in the Probe area with responsibility for both NOR and NAND product lines. While working for Micron, he also found time to complete his MBA from NTU. In 2006, Mr. Gatzemeier was selected as the Fab 2 Probe Section Manager, where he successfully led the Probe Team during startup and fab ramp. His team installed, qualified, and released over 100 Probe tools, and implemented many cost-saving projects focused on test time reduction, increased tool utilization, and full wafer contact probing. In March 2008, he was was promoted to IMFT Product Integration Engineering Manager and now has responsibility for Probe, QA, Yield Enhancement and Process Integration.

Panelist: Sanjiv Taneja, VP of the Encounter Test Business, Cadence

Prior to assuming his current role in 2005 as Vice President of the Encounter Test business unit, Mr. Taneja held a variety of senior management positions at Cadence in engineering, product marketing and busi-ness development. He started his career at Bell Labs in Murray Hill, NJ, where he spent over 13 years in EDA software development and management, led the Custom/Analog Layout Automation group, and launched and rapidly grew the EDA technology licensing business. Mr. Taneja holds a BS degree in Electrical Engineering from Indian Institute of Technology, New Delhi, an MS degree in Computer Science from Ohio State University, and an MBA from New York University.

Welcome to VOICE 2008. It’s our great pleasure to welcome you to this annual gathering of Verigy V93000 SOC and V5000 Memory Series enthusiasts.

This year’s theme is “The Right Stuff,” and in that spirit, we’ve made it our goal to deliver the right tools, training, and networking opportunities to help you be competitive in the coming year. Close to �30 technical abstracts were submitted for this year’s event, covering an extensive range of topics in test: memory, high-speed digital, DC and mixed-signal, communications, software, productivity and more. As always, you’ll find roundtables, panel discus-sions, and new this year, technical kiosks that allow you to explore subjects at your own pace.

This year’s Suppliers Expo should be more popular than ever, featuring extended hours through �0pm on Tuesday, which means you’ll have the choice of attending the Expo, the Evening Event, or both.

Reconnect with colleagues, discover something new, relax, learn, enjoy. That’s what your annual conference is all about.

Sincerely,

Keith Barnes CEO, Verigy

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Distinguished Industry Speakers

At the end of the second day, all forms received will be entered in a drawing to win a special prize. The drawing will be held on Wednesday, Sept. 24, at the close of the event. You must be present to win.

VOICE ‘09 Steering CommitteeJoin the VOICE ’09 board and help create next year’s event. We will be holding a business meeting during the morning session on Wednesday. Please stop by, volunteer for a board position, and be part of the VOICE Team.

Cell Phone/Pager PolicyA friendly reminder: please silence your cell phones and pagers during the conference sessions.

Smoking PolicyThe Hayes Mansion is a non-smoking building. Smoking is permitted outside in designated areas only.

Oktoberfest Evening EventThis year’s Evening Event will transform the Dolce Hayes Mansion into a Bavarian village with German beer, classic fare, a DJ with karaoke, and games of skill and chance. Relax, raise a glass, and take a well-deserved break. Cost: free—included in your event registration fee.

Suppliers ExpoSuppliers Expo ’08 will be open from 1pm to 6pm on Tuesday and noon to 4pm on Wednesday. Suppliers also have the option of staying open from 6pm to 10pm on Tuesday to coincide with the Evening Event. The Expo is a big part of the show each year. Grab a snack, wander around, see old friends and make new ones.

Help DeskIf you need help with any aspect of the conference, visit the Verigy Help Desk located in the Hayes Foyer Upper Level.

Internet AccessHigh-speed wireless internet is available in most rooms and meeting areas in the Hayes Mansion. Visit the registration desk for more information and to order service. Both days of the conference, Pragmatics Technologies, Inc. is sponsoring 50 lines. Visit them at the Hayes Foyer for more information.

Evaluation FormsLend your voice to next year’s conference by filling out speaker evaluation forms. Your input is a crucial part of our planning sessions, so make sure you turn the forms in to technical session room hosts or the registration desk by the end of each day.

Panelist: Raymond LeeVP of Engineering, Nano Integrated Solutions, Inc.

Mr. Lee has vast experience with semiconductor design, debug and failure analysis, and as VP of Engineering, brings his experience and insights to Nano Integrated Solutions’ comprehensive product engineering solutions. Prior to helping launch Nano Integrated Solutions in 2007, he was founder and President of FIB International, Inc., an analytical lab focused on testing, debug and failure analysis of microelectronic devices. The company was founded in 1996 and quickly became the leader in FIB technologies thanks to its highly experienced staff and state-of-the-art equipments. Mr. Lee worked with startups and established design houses on the latest generation of products while developing new protocols and methodolo-gies to meet the challenges of the industry. Earlier, he worked for various semicon-ductor equipment companies such as FEI and Schlumberger ATE in marketing and application development. His collaboration with equipment suppliers and customers allowed him to help develop new solutions for the increasingly complex semiconductor sector. He holds an MBA from Santa Clara University and a BS from the University of California, Berkeley.

Panelist: John Y. Chen VP of Technology and Foundry Operations, Nvidia Corp.

Dr. Chen worked for Hughes Research Laboratories, Xerox Palo Alto Research Center (PARC) and Cypress Semiconductor before joining TSMC in 1992 as Senior Director in Product Engineering and Assembly/Test. As VP Operations, he helped launch WaferTech, where his team ramped fab to 30 thousand wafers a month. He has authored or co-authored 100 papers, and his book on “CMOS Devices and Technology for VLSI “ was published by Prentice Hall in 1990. He was elected IEEE Fellow in 1992, and was a member of the Technical Advisory Committee for ITRI (Industrial Technology & Research Institute) Taiwan from 1988 to 1992. He currently serves on the Technical Committees for SIA and GSA (formerly FSA), and is a board member of Monte Jade Science and Technology Association. Dr. Chen was a Howard Hughes Doctor Fellow and received a Ph.D. in EE and an Executive Management degree from UCLA. He also holds a M.S. from University of Maine and a B.S. from National Taiwan University, both in E.E.

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General Information

Memory Track Keynote Address: Bill McClean, IC Insights

Topic: Major Forces Shaping the Global Semiconductor Industry

Prior to forming IC Insights, Mr. McClean worked at ICE Corporation for 17 years—the last ten as Vice President of Market Research. With more than 25 years of experience tracking the IC industry, Mr. McClean has become a well-known authority on market and technology analysis and forecasting. He specializes in tracking global

economic conditions, developing IC market forecasts, analyzing capital spending and fab capacity trends, researching ASIC markets and technologies, and following emerging markets for ICs such as cellular phones. He serves as Contributor and Managing Editor of IC Insights’ studies and other products, and has been a guest speaker at many important annual conferences held worldwide, including SEMI’s Industry Strategy Symposium, Rose Associates’ Electronic Materials Conference, and Future Horizons’ Electronics Industry Forum. Mr. McClean has a Bachelor of Science degree in Marketing and an Associate degree in Aviation from the University of Illinois.

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Agenda — Tuesday, September 23Time Location Event7:30 am Hayes Upper Foyer Registration, Light Breakfast8:30 am Hayes Ballroom Welcome Address and Introduction8:45 am Hayes Ballroom Pascal Ronde, VP Sales, Service and Support Welcome9:00 am Hayes Ballroom Panel Introduction by Debbora Ahlgren, Vice President &

Chief Marketing Officer9:15 am Hayes Ballroom Panel Discussion10:45 am Hayes Upper Foyer Break – Networking & Refreshments11:00 am Hayes Ballroom SOC Roadmap11:45 am Hayes Lower Level

Meeting RoomsTechnical Sessions

1:00 pm Hayes Ballroom Lunch, Expo Opens

2:00 pm Hayes Lower Level Meeting Rooms

Technical Sessions & Technical Kiosks

4:05 pm Hayes Ballroom and Upper and Lower Foyer

Break – Expo, Snacks, Technical Kiosks

4:35pm Hayes Lower Level Meeting Rooms

Technical Sessions & Technical Kiosks

6:00 pm Hayes Ballroom Cocktails, Evening Event Begins6:30 pm Hayes Ballroom Dinner and Gaming

Agenda — Wednesday, September 2�Time Location Event

8:00 am Hayes Upper Foyer Light Breakfast9:00 am Hayes Ballroom Agenda Review and VOICE Business Meeting & Elections9:15 am Hayes Ballroom MTS & Inovys Roadmap Presentations10:30 am Hayes Upper Foyer Break – Networking & Refreshments10:45 Hayes Lower Level

Meeting Rooms and Lower Level Lobby

Roundtables & Technical Kiosks

12:00 pm Hayes Ballroom Lunch, Expo Opens1:00 pm Hayes Lower Level

Meeting RoomsTechnical Sessions

2:45 pm Hayes Upper Foyer Break – Expo & Refreshments3:15pm Hayes Lower Level

Meeting RoomsTechnical Sessions

5:00 pm Hayes Ballroom Meeting Closure, Best Paper Awards & Raffle Drawing5:15 pm Departure

Technology Kiosks

1. SmarTest Usability Future Vision, Yoshiki Toyama, Verigy

2. V93000 Technical Documentation Center, Falk Kronsbein, Verigy

3. Inovys FaultInsight on the V93000, Michael Braun, Verigy

4. DC Scale VI Curve Tracer, Aether Lee, Verigy

5. New SmarTest Features: TOP Enhancements; IP Reuse; Tabular Solution, Rainer Held, Verigy

6. Software Tools, Andree Weyh, Verigy

7. Test Method API for Analog and RF Instrument, Johannes Hauf, Verigy

8. Productivity Improvement for Port Scale RF Online Debugging, Zhang Hao, Verigy

Roundtable Discussions

1. DUT Board Design Process, Frederick Crist and Kelley Demange, Verigy

2. Utilizing V93000 CCT to Minimize Vector Memory Requirements, Meir Gellis and Dimitry Angert, Test Insight

3. The Concept of Differential Signaling on Pin Scale 400, Stefan Walther and Michael Kozma, Verigy

4. A Comprehensive Design for Test Approach, Martin Froehle, AMD and Markus Seuring, Verigy

5. Yield Learning, Erik Volkerink, Verigy

6. STDF Fail Datalog Standard: Overview and Examples, Ajay Khoche

7. Why Statistical Analysis is Critical for Correlation and how it is Managed on V93000, Phanu Kisamanon, Broadcom and Siva Raman, Verigy

8. Characterizing “At the DUT” on the V93000: Focus Calibration and Loadboard Characterization, Jose Moreira and Heidi Barnes, Verigy

9. Quick Hardware Prototyping, David Johansen, Verigy

10. Sharing Pin Scale V93000 Licensing Globally, Jason Wiseman, Tom Micek, John Pitts, Freescale and Erika Vasquez, Verigy

11. Online Adaptive Test Techniques for the Verigy V93000, Taylor Scanlon, Pintail Technology

12. New STDF Validation Tool for Scan Datalog, Phil Burlison, Verigy

Technical SessionsTrack �: High-Speed Digital (HS) and

DC and Mixed Signal (DC)

HS9

4:1 HDMI Switch: 5ms for Testing: Myth or Reality?

Stephen Rimbault & Regis Poirier, NXP Semiconductors

The TDA9996 is a switch with four DVI/HDMI inputs (HDMI 1.3a compliant) and one DVI/HDMI output (up to 2.5Gbit/s). This type of device requires multiple high-speed I/O resources which are typically limited on low-end tester configurations. This paper describes a new methodology based on an analog Bist opening the door for ultra low cost testing in a production environment.

HS21

Novel Clock Signal Analyses with a Waveform Sampler – Rise/Fall Time, Jitter and Jitter Separation

Hideo Okawara, Verigy

The 6GHz bandwidth waveform sampler MCC in the V93000 captures high-speed and high-frequency signals/waveforms. This paper reports how the V93000’s MCC sampler measures a 1.25GHz clock signal and shows how to analyze the waveform using various DSP techniques. Total jitter (TJ), random jitter (RJ), and deterministic jitter (DJ) are discussed.

HS44

A Time Domain Reflectometry Kit for ATE Test Fixtures

Ross Winters, Intel Jose Moreira, Heidi Barnes & Callum McCowan, Verigy

Verifying the performance of ATE test fixtures is critical when dealing with high-speed digital applications. This paper presents a simple solution for achieving the required signal integrity when performing time domain reflectometry measurements on test fixtures.

HS54

Solving MIPI D-PHY Test Challenges with V93000 SOC Test System, Part 2

Ricky Lau, AMD Yu Hu, Daniel Simoncelli & Stefan Walther, Verigy

The MIPI D-PHY standard introduces different data transmission modes for advanced applications: besides a low-swing,

high-speed differential mode for data transmission, it also employs a large-swing, low-power, single-ended mode for control purposes. This paper focuses on the subtle-ties of changing tester receiver termination on the fly for multi-level waveform detec-tion to ensure comprehensive MIPI test coverage.

HS58

PCI Express Protocol Testing on Verigy V93000 SOC Pin Scale 3600

Toby McPheeters & Jim Chua, Broadcom Jinlei Liu, Verigy

Protocol testing for semiconductor ICs gets more complex as speeds increase and data encoding becomes more sophisticated. This paper addresses the challenges and discusses how existing test platforms can solve current and future challenges.

HS111

Functional Testing of PCI Express Using Pin Scale 3600

Steve Karako, Freescale Michael Kozma & Barry Schmidt, Verigy

This paper explores the protocol testing of a Freescale multi-lane PCI Express-enabled device on the Verigy V93000 using Pin Scale 3600 cards. Protocol challenges of PCI Express testing, test setup and test-time measurements will be covered.

DC6

Reducing the COT with V93000 Per-Pin Time Interval Analyzer

Don Blair, Verigy

This paper explores how to modify levels for the measured pins, modify digital patterns, build and register a PPTIA library, modify test suites in the test flow, modify the test suite dialog fields and limits, and run and debug tests. Extensive correlation data and test execution time data are also covered.

DC45

A DFT for Measuring Rdson and its Application on V93000 SOC

Maarten Derks, NXP Semiconductors Jiamin Wang, Verigy

In the field of power management IC testing, Rdson test plays an important role as one of the key parameters of the power FETs. Traditional Ohm’s law cannot be applied due to the very low resistance of Rdson and the voltage drop on contact resistance. This paper presents a DFT from NXP for precise measurement of Rdson, and applies a library-based test method (part of NXP DClib) on a V93000 SOC.

DC48

Utilizing DSP Filters of Local DSP and RT-SPU in DAC Linearity Test for Higher Throughput and Accuracy

Satoshi Nomura, Verigy

10 ~ 14 bits class DACs are widely used in various types of SOC devices. One of the test challenges for this type of DAC is getting enough accuracy and stability without long test times. This paper discusses how the Local DSP of AV8 and RT-SPU of MBAV8 address this common test challenge. The presentation covers theoretical explanations using simulation results to real test results using the AV8 and MBAV8.

DC77

Dynamic DC Measurement Using DC Scale on the V93000 Test System

Aether Lee & Takashi Shibata, Verigy

DC Scale VI32, a complement to the hot-selling product family member DC Scale DPS32, was introduced with SmarTest 6.3, and features new functionality called “Dynamic DC Measurement.” In this paper, two different test setups are optimized to present this new functionality with prom-ising results by advanced composing skills.

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DC78

Optimized Solutions to Measure PMIC Parameters

Sophia Zhang, Verigy

More and more PMIC modules are inte-grated into one PMIC or SIP device, making it difficult to meet speed, accuracy, and low-cost requirements when testing PMIC parameters. This paper introduces two solutions for measuring PMIC parameters using V93000 DC and analog resources, greatly reducing test time and improving test accuracy.

DC81

Implementation of Video Signal Test for a TV-IC Device

Teruaki Itabisashi, Renesas Technologies Yasuhiro Kizu, Verigy

This paper covers the test methodolo-gies used to test video signal processing. Characterization of chroma, deflection, YUV, parabora and video/sound IF will be covered, along with techniques for improving test program development and reducing test time.

DC135

Sample Rate Conversion: The Possibility to Create as Many Clock Domains as Available Digitizers

Achim Rosenau, NXP Semiconductors Erhard Schuetz, Verigy

On AV8 and MBAV8, the sample rate for AWGs and digitizers typically fits the AV8’s clock scheme, but for some devices, the sampling frequency of the source signal leads to incoherent sampling frequencies for the digitizer. This paper describes how to get the wanted sampling frequency with sampling rate conversion, thus creating many independent clock domains as avail-able digitizers.

Track 2: Productivity Software & Tools (PST)

PST32

The V93000’s New High-Volume Manufacturing Capabilities

Joel Taylor and Henry Arnold, Verigy

High-volume manufacturing presents new challenges to how SmarTest and the V93000 tester are integrated onto factory test floors. This paper discusses how Verigy’s new High Volume Manufacturing Application Programming Interface (HVM-API) simplifies the move to high volume/high complexity environments across large and diverse factory test environments.

PST33

Robust Test Platform Conversion Using Galaxy Examinator

Wes Smith, Galaxy Kathleen Miller, Verigy

This paper will describe the use of Examinator's data analysis capabilities,specifically the Gage R&R and bin correlationutilities, to compare the test results between the two systems and isolate the specific teststhat required corrective action. The processby which Examinator was used to identify yield issues related to load board problems,and to ensure the product's successful transferto production overseas, will also be described.

PST36

A Novel Way to Explore V93000 Test Programs with Web Browser

Zuliang Zhang and Zhijun Xue, Verigy Ltd.

The V93000 is a leading ATE platform utilized in SOC semiconductor testing. Often, there is a need to explore and share the V93000 test program details outside of the tester platform’s workstation or programming environment. The solution is to create a well-organized and readable form of test program documentation. A novel web-based tool was developed to imple-ment the solution by the authors, who are members of the Verigy Shanghai ADC.

PST38

Advanced Boundary Scan Diagnostic Tool on V93000

Herve Brocheton and Ming Lu, Verigy

Testing SOC devices with the boundary-scan and Test Access Port standard is great—as long as you have in-depth knowledge of the JTAG protocol. This paper discusses a V93000 diagnostic tool that simplifies boundary-scan test debug, and identifies the root cause of boundary scan test failures without the help of a JTAG expert.

PST41

Automating Production and Engineering Testflow Reuse within the Manufacturing Environment

William Polanco, Freescale Semiconductor Erika Vasquez, Verigy

With ICs becoming more complex, creating a testflow that can be reused for multiple setups is a real time-saver. This paper covers creative techniques and productive processes to setup the work-order environ-ment, so one testflow can cover literally hundreds of test program setups.

PST53

Core-based Programming and Test IP Reuse in Mixed Signal SOC Test Development on V93000

Zane Jiang & ZuLiang Zhang, Verigy

Time-to-market and time-to-revenue issues are driving test development processes to be shorter and more automated. This paper addresses mixed signal test program development requirements on the V93000 SmarTest environment, and uses a generic conceptual test architecture in an SOC device to explore practical concepts of reus-able Test IP on the V93000.

PST82

Protocol Aware Approach for ATE Debug

Sean Lu, Broadcom Rodrigo Gonzalez, Verigy

This paper describes a protocol-aware approach with a standalone utility tool to access register through serial interface. The application examples for this utility tool are MDIO, JTAG, I2C and SPI. This tool can be executed outside the SmarTest Eclipse environment in the Linux console window with the help of UTM (Unified Test Method).

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PST88

Efficient Test Program Development in a Multi-Discipline Globally Distributed Team

Ben Van der Waal, NXP Semiconductors Hagen Goller, Verigy

Integration across the semiconductor world has resulted in a variety of disciplines being represented on a single die or package. This paper discusses how to preserve efficiency, time-to-market, and time-to-volume in test program development by using three pillars: Revision Control for program re-use, Masterfiles for linking programs, and Multiports for parallel test.

PST100

Test Assist – A New Way to Manage V93000 Test Programs

Vikram Shirgur and Vinuta Shetty, NANO Sangeet Karamchandani, Verigy

Test Assist is a new tool which has the ability to manage testflows, test programs, and device directories. It provides a central database with all information about transla-tion, changes to test programs, and device revisions. This paper discusses how Test Assist (TA) works with SmarTest to augment current workflow and generate production-worthy test programs with minimal effort.

PST101

Integrating ATE Test in the Design Flow – A Case Study

Somnath Sen & Sreenivas Gandavaapu, Cypress Semiconductor Kirit Kichadia, Simutest

Every test teams wants to accelerate the design-to-test cycle to improve time-to-market and reduce test development costs. This paper presents examples of design-to-test vector conversion on the V93000, and discusses how the Simutest Verifier software suite uses efficient conversion and pre-silicon verification of functional and scan vectors to reduce test development/debug time while increasing the first-pass success rate for test programs.

PST130

Getting More out of SmarTest Eclipse Work Center

Michael Vogt, Michael Kozma & John Buoy, Verigy

The Eclipse platform was chosen as host of the new SmarTest Work Center 6.0. This paper discusses how to get most benefit from Eclipse in test program development. User interface preferences, integration with external tools, plug-ins, consistent setup, best practices, and troubleshooting tips and techniques are covered.

Track 3: Communications & RF (CRF)

CRF10

A Fast and Accurate Method to Perform Evaluation Board to Production Board Correlation by Using Non-linear Device Characteristics

Michael Engelhardt, Verigy

With more RF parts in consumer applica-tions, and more RF ports per device, RF test engineers need fast methods to establish correlation between bench evaluation boards and production load boards. This paper investigates a fast and simple method to perform RF correlation without external equipment or probes using nonlinear device characteristics to accurately determine input and output loss of production boards rela-tive to bench evaluation boards. Examples of critical RF parameters are covered.

CRF19

Concurrent Test Implementation on a 2G/3G Baseband Device

Fabien Perez, NXP Semiconductors Markus Vogt, Verigy

Combining different silicon into multichip packages extends device functionality but leads to longer development cycles and increased test times. This paper explores how the unique architecture of the V93000 allows different IP cores to be tested concur-rently to save test time. Three IP cores on a complex 2G/3G Baseband device are covered, including port definition, analog resource distribution, clock domains and triggering.

CRF20

Multi-Threading on V93000 Reduces Multi-Site RF Test Time on Intel Front-End Transceiver

Leon Sassoon, Intel Michael Engelhardt, Jason Smith & Joe Kelly, Verigy

Hardware DSP is great for large data acquisitions in production test, but for smaller data arrays, the first-bit processing rate and other overhead can reduce its efficiency. SmartCalc multi-threading on the V93000 can fill the gap, especially as a complement to hardware DSP. This paper discusses multiple scenarios for using SmartCalc to reduce test time in multi-site environments.

CRF22

Making MIMO Measurements in a Manufacturing Environment

Vivek Verma and Craig Kanetake, Verigy

The multi-transceiver architecture and strin-gent performance requirements of MIMO systems presents unique test challenges in a manufacturing environment. This paper addresses some of these challenges and presents solutions using V93000 Port Scale. The primary focus is on channel isolation and channel phase offset measurements.

CRF34

A High-Parallelism Low-Cost Solution for RF-to-Digital Receiver Test on V93000

Jie Ren and Liang Ge, Verigy

The V93000 Port Scale RF incorporated with MBAV8 not only provides multi-modulated stimulus capability, flexible power range and better noise performance, but also enables high-parallelism, so more devices can be tested in parallel. This paper discusses how the V93000 Pin Scale 400 digital cards with highly flexible digital capture and post-processing capability provide a low-cost solution with high-parallelism to handle BER test, instead of using a dedicated BER measurement box instrument.

CRF65

Concurrent Test Techniques to Reduce MCU+RF Single Chip Test Time

Jean Mounie, Freescale Semiconductors Eric AUBRY, Verigy

As IC complexity and integration increase, test engineers face contradicting goals with SOC devices: lower test cost, higher test coverage. This paper discusses how to combine multi-site and concurrent test on a Port Scale RF tester. Constraints, method-ologies and results are presented.

CRF72

IQ Phase and Magnitude Mismatch Calibration

Jonathan Rimon, Verigy

The need for phase and magnitude, IQ matched AWG, and DGT in today’s radio products is bigger than ever. This paper explores BB IQ calibration (Hypercal), a new SmarTest procedure that calibrates the possible phase and magnitude mismatch between the AWG and DGT by using a new API with a new loadboard. Methodology, performance gains, and support for future EVM tests are discussed.

CRF76

Demodulating WIMAX—An Introduction to New V93000 Demodulation Capabilities

Edwin Lowery, Guenther Bleifuss & Hiroshi Kikuyama, Verigy

Using WiMax Uplink/Downlink as an example, this paper shows how to make complex modulation measurements on the V93000. Solutions for many more modula-tion formats including Bluetooth, 802.11a/b/g, WCDMA, Mimo, and others are also presented.

CRF89

On the Use of Multi-Tone for the Measurement of Inter-Modulation Distortion in RFIC

Cheng Huang, Verigy

This paper presents an accurate, nonlinear distortion method with fewer tones. Measurement results show that the variance is below 0.4dB after averaging 100 NPR distortions excited by 60-tone with different random phases. Compared to the NPR measurement results obtained by 10000-tone, the measurement error is only 0.23dB using 60-tone with averaging.

CRF95

Pure Clock Solution for Improved PLL Performance

Roger McAleenan, Oscar Solano & Khaled Ben-fatma, Verigy

Pure Clock resource is a high-performance, low-phase-noise source that provides common reference frequencies to trans-ceivers, replacing many common external circuit solutions, for greater reliability and performance. This paper explores benefits and operation of a low-phase-noise source as a frequency reference for SOC applica-tions; gives an overview of current applica-tions where pure clock references improve spectral performance and system-level tests such as EVM; and makes side-by-side

comparisons of the Port Scale RF Pure Clock board against external

solutions such as sources with and without the divider circuitry that are commonly used to improve phase noise.

CRF103

Testing Bluetooth 2.0 + EDR with Port Scale RF: Challenges and Solutions

Martin Dresler, Paul Chen & Joe Kelly, Verigy

This paper describes typical Bluetooth 2.0 + EDR tests, and discusses how embedded software algorithms in Port Scale RF help improve test program development efficiency and reduce test time. Primary focus is on the implementation of the TX and RX modulation tests, the use of parallel RF tester resources, and hardware trigger to optimize the usage of RF parallel sources and RF receivers.

CRF115

Wideband RF Measurement

Frank Goh, Verigy

PSRF measurement is limited to 55MHz BW. While multiple measurements can be used to capture spectrum above 55MHz, this is not suitable for demodulation. This paper shows how to measure an RF signal wider than 55MHz BW on the PSRF, and describes how to create the FIR filter needed for demodulation.

CRF136

RT-SPU to Manage Small Signal Test Requirements for Effective Test Time

Ilya Tsiperfal, Broadcom Siva Raman, Verigy

In the RF world, small-signal sensitivity tests are executed to verify device spectral efficiency. These test conditions are created to validate device functionality performance in the real environment where distortions and interference have enormous impact. This paper presents the RT-SPU capabili-ties of Port Scale RF on the V930000, and discusses how the instrument accurately captures and analyzes method RF signals.

Track �: Memory (M)

M57

Closing the Loop Between Design and Test: Enabling the Validation and Debug of MTL-based Memory Test Patterns by Logic Simulation

Alexander Roskin & Daniel Blank, Verigy

Currently, HSM V93000 users write MTL code and validate the resulting test patterns with real devices. This paper presents alternate approaches for an MTL pattern export functionality that allows SmarTest test patterns to be used in a simulation environment. This solution is based on a FW-command EARD and is implemented in the form of a Test Method. An actual customer pattern is translated as proof of concept.

M66

GDDR5 Test Challenges and their Solutions on the V93000 HSM Series

Han-Ho Jin & Hee-Won Kang, Hynix Semiconductor Hubert Werkmann & Ji-Won Seo, Verigy

With anticipated data rates in the 5Gbps range on single-ended signals, GDDR5 devices challenge existing high-speed memory ATEs. This paper presents how the V93000 HSM series can reduce data rates with techniques such as multi-stage device training and CRC error code genera-tion and checking with variable read/write latency.

M80

Utilize V5XXX Features to Test Beyond 100MHz

Houfeng Zuo, Verigy

Although the Verigy V5XXX platform is focused primarily on applications below 100MHz, testing beyond 100MHz with ECR logging can still be achieved. This paper discusses two approaches.

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M83

V5000 Code Structure Standardization and Automatic Generation

Jian Zhang & Brian Lu, Verigy

The Verigy V5xxx platform is a powerful memory tester, but it can be complicated to create a basic structure due to the manual setup required. Plus, the system’s inherent flexibility can lead to a variety of different coding styles that are difficult to understand or maintain. This paper presents a standard coding structure, and introduces a GUI tool to generate a main skeleton and template.

M120

Flash Memory Bitmapping – Future Challenges and Solutions

Mark Greenwood, Verigy

As flash memory continues to grow in density and die size continues to shrink, it’s common for wafers to contain several hundred devices and generate potentially terabytes of data in a single touchdown probe flow. This paper discusses specific issues at wafer sort including coverage vs. test time, and proposes solutions to dealing with the massive amount of data generated during front-end testing.

M127

Mass Production Test Solution for XDR 4.8Gbps on the Leading Edge of DRAM

Kunihiko Kato, Elpida Takeshi Sonoda, Verigy

XDR DRAM has extended its data rate to 4.8Gbps, the fastest in the industry, to meet the demands of high-speed digital consumer applications. This paper introduces the prac-tical techniques for 4.8Gbps mass produc-tion test using the V93000 HSM3600.

M139

Factory Automation in a 300 mm Memory Test Environment

Larry Goldsmith, Verigy

With larger wafer sizes comes the need to fully automate and standardize the move-ment and testing of wafers in a high-volume manufacturing memory test facility. This paper discusses an ATE solution utilizing the SECS/GEM and Semi Standards to drive the test cell from a Host Controller integrated into its MES.

M141

A Comparison of Pin Electronics Designs to Increase Test Parallelism for Memory Devices

Scott West, Verigy

This paper reviews the advantages and disadvantages of several PE design strategies

used to increase test parallelism, considering performance and cost of test implications. Traditional driver/comparator channels, passive fan-out (i.e. wired-OR), and buffered fan-out strategies are compared for Flash and SDRAM device testing. Both wafer sort and final test implications are discussed.

M142

Sub-40nm Multi-Level Flash Challenges for Production Test

Paul Okino, Verigy

This paper summarizes the technical and economic test challenges facing Flash memory manufacturers as they scale process geometries below 40nm. It discusses the advantages and limitations of presently known solutions, and identifies future trig-gers for adoption of new test methodologies.

Track 5: Test Techniques & Methodologies (TTM)

TTM15

Dynamic Supply Current Signature (Iddcs) Analysis Using the Qstar Module on V93000

Richard Durant & Daniel Ahrens, LSI Ariadne Salagianis, Verigy

For Iddcs measurements on the V93000, the Qstar plug-in ATE loadboard module provides a fast and accurate dynamic Idd measurement that runs in parallel with an independent pattern synchronized to the V93000. This paper explores the benefits, including improved test program debug, device characterization, test coverage, silicon process evaluation, and failure analysis.

TTM28

Yield Ramp Acceleration Using an Enhanced Diagnostic Solution

Thomas Jackson, Anis Uzzaman, Joe Swenton & Thomas Bartenstein, Cadence Design Systems

New CAD tools provide Failure Diagnosis capability, which can identify systemic defects during early product development, and provide enough information so that each defect is understood and can be addressed.

TTM37

Hiding Calculation Time with Multi-Threaded Test Program on V93000

Martin Dresler & Kyoichi Hatabu, Verigy

This paper explains how to design and imple-ment a multi-threaded test program with the V93000, and introduces how to hide calcula-tion time under other tests. Throughput and test results on an actual device and DUT board are presented, showing how the calculation time of four tests were hidden to achieve 20% test time reduction.

TTM55

Security Key Management and Programming on V93000 in a Production Environment

Alberto Ascagni & Luca Parma, STMicroelectronics Simondavide Tritto, Verigy

Today’s communication systems must be able to create and protect unique identifiers for access control and application security. This paper describes the identification and authentication (I&A) approach used by STMicroelectronics for ensuring data protec-tion on a specific Digital Radio device by means of a unique identification key fused into every device’s One-Time-Programmable (OTP) memory cell.

TTM60

Efficient Scandump Technique

Krishna Dusety, Arul Subbarayan, & Neetu Agrawal, Qualcomm

Scandump is debug functionality that dumps valuable failure information through scan chains when failure modes are set. This paper discusses a test-method approach to efficiently obtaining this information using the V93000 SOC. This method captures and organizes the failure information for various fail modes by modifying the vectors dynamically.

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TTM61

ATE Test Method to Overcome Contact Resistance during HSTL Programmable Buffer Impedance Test

Norman Pan, LSI Dimitri Beausejour, Verigy

This paper discusses the challenges involved in developing a test methodology that can distinguish between contact resistance and HSTL buffer impedance. Topics include: Test method solution implementation (interface design), design specification for portability across different devices and various plat-forms, requirement for solution to be robust while maintaining high product yields, and requirement for measurement test time.

TTM64

A New Compatible V93000 Probe Card Design—One Hardware for Wafer and Package Samples Debug

Harold Calderon, Melvin Cu & Lhilbert Magpantay, NXP Semiconductors Yun Dai, Verigy

This paper proposes a new compatible probe card design solution with a simple debug tool to easily debug test programs at wafer setup using a package device. The solution is based on an existing PMIC device wafer sort test program. Authors discuss high-speed impedance match, additional routine voltage lost, probe card external circuit design, and correlation results.

TTM91

The “d2s Framework”: Targeting the TTM and TTV Challenges of Complex SOC DUT Registers Programming

Neal Burgner, Qualcomm Daniel Blank & Gianluca Lombardi, Verigy

The d2s (dynamic-to-static) framework automates generation of static setup patterns while maintaining the ability to dynamically change them during the test program lifecycle. This paper introduces the d2s framework, shows how test engineers can use it, and outlines the necessary steps to apply it to a generic device.

TTM94

Adaptive Test at Its Best with V93000 and OptimalTest

Gil Balog, OptimalTest

This paper discusses how OptimalTest executes Adaptive Testing on the V93000 SmartTest platform from the outside at zero overhead, without recompiling the test program. OptimalTest’s new generation of adaptive testing solutions not only reduce test time (TTR) but also enhance quality, reliability and yield learning.

TTM104

Characterization Techniques for a High-Performance Digital Signal Processor SOC: Wavewizard to V93000 Testflow

Roberta Myers-Baturin, Heath Perry & Mark Sleininger, ADI

This paper describes a novel characteriza-tion method that uses Wavewizard, several scripts and customized TestMethods to reduce characterization time on DSPs. The technique is fully automated, graphical, and allows isolated targeting of the peripheral I/O transactions that are specific to the AC timing specification being measured.

TTM108

A Technique to Automate Characterization of DUT Configurable Parameters Through the JTAG Port

Babak Vaez & Derek Lee, nVidia Chris Koknat, Verigy

Parameters in nVidia’s DUTs can be tuned by altering the DUT’s registers, a time-consuming manual process. This paper describes an automated TestMethod and Perl code that can be used to iteratively change the vector data, run tests, and datalog the results, allowing test engineers to create programs quickly and characterize many devices over a wide variety of register settings.

TTM113

Unified Volume Diagnostics for ATE and In-System Logic-BIST Using the Inovys Scan-Imager Solution

Douglas Kay & Matthias Kamm, Cisco, Lien Tran, Nano

Standard “Volume Diagnostics” involves broadside ATPG testing and Scan-Out error capture during wafer sort. Cisco ASICs go a step further with at-speed, embedded logic BIST, which can be run on the ATE as well as in-system during diagnostics, manufac-turing, even in the field. This paper presents the details of a unified approach to capturing LIBIST failing flops on the ATE and board-level environment for diagnostics.

TTM114

Programmable Clock Controller for On-Chip, In-System Frequency Shmoo

Han Ta, Houngshin Jun, & Matthias Kamm, Cisco

Cisco Systems has designed and patented a new PCC that supports on-chip frequency modifications, and is setup and controlled via the JTAG interface using only the low-speed chip reference clock. This paper will discuss PCC design and application, and review test and manufacturing results from actual Cisco ASICs. Correlation between V93000 Pin Scale clock (ps3600) and on-chip PCC clock is also reviewed.

TTM131

Rapid Device Setup through JTAG Protocol Language

Chun Lai Brian Lin, Broadcom Peter Obregozo, Verigy

As the complexity of SOC devices continues to increase, device bring-up with designer-generated patterns is no longer feasible. This paper illustrates how to bring up an RF SOC device for RX and TX testing by writing to the device registers, and without having to convert patterns from simulation. The implementation emulates the JTAG protocol and program device registers through the device’s JTAG port for fast, efficient communication.

TTM132

Fast and Secure OTP Production Solutions using Certicom on the V93000

Tom Heckman, Certicom Fritz Mockler, STMicroelectronics Frank Gurtovoy, Verigy

Fast and secure programming of OTP keys is critical in production for many electronic devices. This paper shows how Certicom’s secure delivery of OTP keys and program-ming techniques with the V93000 can achieve low-cost test.

TTM133

Demystifying Digital Capture

Amit Monga, Daniel Simoncelli & Michael Kozma, Verigy

Though a common technique on the V93000, Digital Capture frequently presents challenges in implementation. This paper investigates different metrics for setting up and using the technique. Things like card type, test head size, ICE vs. non-ICE, pattern type, Xmodes, tester period, selective vs. sequential capture, number of pins, and more are discussed.

TTM138

Highly Parallel DC Measurements for Fab In-line Monitoring

Ernesto Shiling & Lou Medina, IBM, Robert Smith, Verigy

This paper introduces a method for testing in-line test structures on wafers at various process levels (CA, M1, M2, etc.) in a highly parallel fashion. Each pin will have the ability to: force and measure voltage and current, with low current measurement capability down to 10 Pico amps; measure frequencies up 50 MHz; source small vectors for register programming; provide hard grounds for any pin; and provide decoupling per pin when needed. Throughput improve-ments are covered, along with data-gathering considerations.

Ken Meadeken.meade@allianceate.com(408) 486-0900www.allianceate.com

Alliance ATE is a semiconductor test services company that optimizes back-end processes by bridging SOC chip design to High Volume Manufacturing (HVM). Alliance ATE brings industry-leading experience in chip design, test and software engineering services for Mixed Signal, RF, High-Speed and complex VLSI devices. Alliance ATE’s Flex-Force team approach enables companies to manage excessive resource demands while achieving time-to-market requirements. Combining Flex-Force with our Velocity CAE automation tool suite provides an effi cient design to HVM link.

Junko Nakayajunko_nakaya@cmicro.com (503) 601-1180www.cascademicrotech.com

Cascade Microtech’s Pyramid probe cards provide excellent signal integrity and mechanical alignment capabilities. Ideal for multi-die testing for RF wireless, high-speed digital in SiP/SoC, and parametric testing. Gryphics high-performance test sockets provide a very fi ne pitch and excellent signal fi delity for today’s high frequency applications, whilst driving down the cost-of-test.

Gold

Hau Lamhau.lam@tessi.com(503) 913-3479www.tessi.com

TSSI, inventor of WGL (Waveform Generation Language), and a leading innovator of standard pattern conversion and validation technologies, introduces at VOICE2008: TSSI Silicon Debug Laboratory. Contact us for all turnkey services from full test program development, wafer sort and fi nal test, to silicon debug, throughput optimization, and yield enhancement.

Ric Conradtsales@galaxysemi.com(617) 678 7621www.galaxysemi.com

Galaxy Semiconductor Solutions is a leading provider of test data analysis and defect reduction software for the semiconductor industry. Galaxy products are utilized by over 1500 users worldwide to help improve device yields, reduce DPM (defects per million), and enhance engineering productivity. Galaxy products are easy to learn and use and are available for trial download at www.galaxysemi.com.

Becki Wattbecki_watt@mentor.com(603) 685-4806www.mentor.com/dft

Mentor Graphics DFT advanced test and diagnosis solutions deliver the most effective means for detecting defective parts as well as diagnosing failures to pinpoint the type and location of defects. The role of test is expanding into the yield learning space through production volume diagnosis.

Tom Dyertomdyer@simutest.com(408) 988-4032www.simutest.com

Simutest presents its full suite of best-in-class EDA and ATE integration tools for faster ATE test program generation and offl ine validation. The diagnostic features of the tools, by presenting silicon failures in the design environment also expedites the post-silicon debug process.

Shaida Kashanishaida.kashani@nanoisi.com(408) 496-4110www.nanoisi.com

Nano Integrated Solutions, Inc. with 5 labs in North America and 100+ engineering staff, provides Semiconductor Design fi rms with a complete vertical integration of essential engineering services including full Functional Test (Development, Consulting, Services, Training), Complete FA & Debug Services (TEM, FIB, SEM, etc.), ESD & Latch-up, Reliability Qualifi cation, PCB Layout Design & Assembly, and accredited equipment & ATE Calibration & Repair services. Nano Integrated Solutions, Inc. is SO 17025 Accredited and DSCC Certifi ed.

Sponsors Diamond

Platinum

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AltanovaJames Dressersales@altanova1.com (408) 225-7011www.altanova1.com

Altanova provides a complete turnkey solution for semiconductor test. We specialize in Hi-Speed Digital, Mixed Signal & RF ATE boards. Altanova designs, simulates, fabricates & assembles ATE, Characterization Boards & Probe Cards. The company also produces contactors, heat sinks and docking plates.

Robert Cross rcross@cmrsummit.com(408) 844-9066www.cmrsummit.com

CMR Summit Technologies is your “full turn-key provider” for ATE solutions of test load boards, probe cards and other types of PCB projects. We provide applications engineering support, ATE design/lay out services, and PCB fabrication including full assembly services. “We are unique with all our services under one company’s ownership and support.”

Al Castanedaal@gorillacircuits.com(408) 386-0438www.gorillacircuits.com

Gorilla Circuits is a leader in the manufacturing of custom Printed Circuit

Boards for the ATE market. Our Engineering staff excels at assisting engineers with Design for Manufacturability methods and gener-ating successful formulas to achieve critical impedance values. Gorilla Circuits utilizes an advanced manufacturing system and the latest equipment available to deliver your time-critical requirement.

Vincent Chiangvincent_c@jtron-tech.com+886 3 552 6986, ext. 160www.jtron-tech.com

Jtron Technology was founded in May, 2004. We are Agilent and Verigy’s partner in Semiconductor and LCD testing outsourcing service business. We are also the professional RFID system integra-tion provider for IC test facilities. Our service locations have been across Asia, including Taiwan, Shanghai, Singapore, Malaysia, Thailand, and Korea.

Anita Mastilockamastilock@mctest.com408 264 8880amastilock@mctest.com

MC Test Products, Inc. Turnkey load boards, probe cards, bench and characterization boards. RF, Mixed signal, Digital. FR4, Nelco 4000-13, Rogers and other distinctive materials. Schematic Capture: Orcad, Concept, & DX Designer. Layout: Allegro, Pads,

Protel.We invite our customers to our facility to work with the designers improving the design time process.

Taylor Scanlontaylor.scanlon@pintail.com(972) 464-5919www.pintail.com

Pintail Technologies is a leading supplier of adaptive test soft-ware that can dynamically improve test yield, reduce test time and increase test reliability of complex integrated circuits. The software runs in real-time under the O/S of the ATE like Verigy’s V93000. Products also include real-time database tools that give instant visibility to your test operations and test subcontractors.

Karen Lynchsales@svprobe.com(480) 635-4700www.svprobe.com

SV Probe is a leading test solutions provider with a diverse product offering that includes cantilever, vertical and blade probe cards, along with PCB/PMB design and fabrication. SV has recently expanded its group of products to include memory probe card solu-tions. Headquartered in Gilbert, Arizona, SV Probe has manufac-turing and support centers worldwide. Put Us to the Test™.

Charles Corbinsales@testar.us(866) 808-1899www.testar.us

Testar specializes in state-of-the-art test interface boards. Using the latest in high-performance materials, manufacturing techniques and design layout software, we do fast-turn, multi-layer designs combining RF, high-speed digital, mixed-signal and analog circuits.

Van Limburg Engineering Inc.

Eric Brewereric.brewer@vl-eng.com(714) 329-5897www.vl-eng.com

Van Limburg Engineering (VLE) is a worldwide engineering company that specializes in providing ATE Test Development Engineering services for semiconductor manufacturers and fabless companies. Engineers are programming the latest probe/fi nal test solutions for a wide variety of devices (digital, analog, mixed-signal, RF, etc) on various industry standard ATE platforms.

Rob LaNocerlanoce@wentworthlabs.com (408) 919-1875 www.wentworthlabs.com

Wentworth Laboratories presents proprietary, customer onsite-maintainable vertical probe cards with the ability to accommodate over 16,000 contacts and guaranteed for 1,000,000 touchdowns: Accumax®, for high speed, tight pitch, multiple die and high current fl ip chip devices; and Megamax™, for ultra-high current fl ip chip/ C4 devices at standard pitch.

Sponsors, cont.

Silver

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Suppliers Expo ‘08 Don’t miss it!

Hayes Balloom

Hayes Foyer Upper Level

5 6 7 8

1 2 3 4

Altanova

12

34 5

67

8

9

Verigy Technical Kiosks

Reg M-Z Reg A-L

1211

10 15

13

Internet Cafe

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Day � Tuesday, Sept. 23, 2008

Track DC & Mixed Signal (DC)

Productivity Software & Tools (PST)

Communications & RF (CRF)

Memory (M) Test Techniques & Methodologies (TTM)

High Speed Digital (HS)

Live Oak Room San Martin Room Morgan Hill Room Madrone Room Monterey Room

11:45 - 12:25 DC78Optimized Solutions to Measure PMIC Parameters

PST41 Automating Production and Engineering Testflow Re-Use Within the Manufacturing Environment

CRF34 A High-Parallelism Low-Cost Solution for RF-Digital Receiver Test on V93000

Keynote Bill McClean, IC Insights Major Forces Shaping the Global Semiconductor Industry (in Monterey Room)

TTM104Characterization Techniques for a High Performance Digital Signal Processor SoC: Wavewizard to V93000 Testflow (Madrone Rm)

12:25 - 1:00 DC45A DFT for Measuring Rdson and its Application on V93000 SOC

PST36A Novel Way to Explore V93000 Test Programs with Web Browser

CRF72IQ Phase and Magnitude Mismatch Calibration

TTM108A Technique to Automate Characterization of DUT Configurable Parameters Through the JTAG Port (Madrone Rm)

1:00 - 2:00 Lunch Lunch Lunch Lunch Lunch

2:00 - 2:35 HS44A Time Domain Reflectometry Kit for ATE Test Fixtures

PST88Efficient Test Program Development in a Multi-Discipline Globally Distributed Team

CRF95 Pure Clock Solution for Improved PLL Performance

M66 GDDR5 Test Challenges and Their Solutions on the Verigy V93000 HSM Series

TTM132Fast and Secure OTP Production Solutions Using Certicom on the V93000

2:35 - 3:10 DC6 Reducing the COT with V93000 Per Pin Time Interval Analyzer

PST33 Robust Test Platform Conversion Using Galaxy Examinator

CRF22 Making MIMO Measurements in a Manufacturing Environment

M139 Factory Automation in a 300 mm Memory Test Environment

TTM28 Yield Ramp Acceleration Using an Enhanced Diagnostic Solution

3:10 - 4:05 HS111Functional Testing of PCI Express Using Pin Scale 3600

PST53Core-based Programming and Test IP Re-Use in Mixed Signal SOC Test Development on V93000

CRF115Wideband RF Measurement

M80 Utilize V5000 Features To Test Beyond 100 MHz

TTM15 Dynamic Supply Current Signature (Iddcs) Analysis Using the Qstar Module on V93000

4:05 - 4:35 Break Break Break Break Break

4:35 - 5:25 HS58 PCI Express Protocol Testing on V93000 SOC Pin Scale 3600

PST101 Integrating ATE Test in the Design Flow – A Case Study

CRF89 On the Use of Multi-Tone for the Measurement of Inter-Modulation Distortion in RFIC

M142 Sub-40nm Multi-Level Flash Challenges for Production Test

TTM37Hiding Calculation Time with Multi-Threaded Test Program on V93000

5:25 - 6:00 DC48 Utilizing DSP Filters of Local DSP and RT-SPU in DAC Linearity Test for Higher Throughput and Accuracy

PST100 Test Assist—A New Way to Manage Verigy V93000 Test Programs

CRF10A Fast and Accurate Method to Perform Evaluation Board to Production Board Correlation by Using Non-linear Device Characteristics

M141 A Comparison of Pin Electronics Designs to Increase Test Parallelism for Memory Devices

TTM133 Demystifying Digital Capture

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Day 2 Wednesday, Sept. 24, 2008 Track DC & Mixed Signal

(DC)Productivity Software & Tools (PST)

Communications & RF (CRF)

Memory (M) Test Techniques & Methodologies (TTM)

High Speed Digital (HS)

Live Oak Room San Martin Room Morgan Hill Room Madrone Room Monterey Room

1:00 - 1:35 HS54 Solving MIPI D-PHY Test Challenges with Verigy V93000 SOC Test System, Part 2

TTM55 Security Key Management and Programming on V93000 in a Production Environment

CRF20 Multi-Threading on Verigy V93000 Reduces Multi-Site RF Test Time on Intel Front-End Transceiver

M83 V5000 Code Structure Standardization and Automatic Generation

TTM114 Programmable Clock Controller for On-Chip, In-System Frequency Shmoo

1:35 - 2:10 HS9 4:1 HDMI Switch: 5 ms for Testing: Myth or Reality?

PST38 Advanced Boundary Scan Diagnostic Tool on V93000

CRF103 Testing Bluetooth 2.0 + EDR with Port Scale RF: Challenges and Solutions

M127 Mass Production Test Solution for XDR 4.8 Gbps on the Leading Edge of DRAM

TTM138 Highly Parallel DC Measurements for Fab In-Line Monitoring

2:10 - 2:45 HS21 Novel Clock Signal Analyses with a Waveform Sampler— Rise/Fall Time, Jitter and Jitter Separation

TTM131Rapid Device Setup Through JTAG Protocol Language

CRF65Concurrent Test Techniques to Reduce MCU+RF Single Chip Test Time

M120 Flash Memory Bitmapping—Future Challenges and Solutions

TTM94 Adaptive Test at its Best with Verigy’s V93000 and OptimalTest

2:45 - 3:15 Break Break Break Break Break

3:15 - 4:00 DC81Implementation of Video Signal Test for a TV-IC device

PST130 Getting More Out of SmarTest Eclipse Work Center

CRF76 Demodulating WIMAX— An Introduction to New V93000 Demodulation Capabilities

M57 Closing the Loop Between Design and Test: Enabling the Validation and Debug of MTL-Based Memory Test Patterns by Logic Simulation

TTM91 The “d2s-Framework”: Targeting the TTM and TTV Challenges of Complex SOC DUT Registers Programming

4:00 - 4:30 DC77 Dynamic DC Measurement Using DC Scale on the V93000 Test System

PST32 The V93000’s New High Volume Manufacturing Capabilities

CRF19 Concurrent Test Implementation on a 2G/3G Baseband Device

TTM64 A New Compatible V93000 Probe Card Design — One Hardware for Wafer and Package Samples’ Debug

TTM113 Unified Volume Diagnostics for ATE and In-System Logic-BIST Using the Inovys Scan-Imager Solution

4:30 - 5:00 DC135 Sample Rate Conversion: The Possibility to Create as Many Clock Domains as Available Digitizers

PST82 Protocol Aware Approach for ATE Debug

CRF136 RT-SPU to Manage Small Signal Test Requirements for Effective Test Time

TTM61ATE Test Method to Overcome Contact Resistance During HSTL Programmable Buffer Impedance Test

TTM60 Efficient Scandump Technique

Steering Committee

Conference Chair

Catherine Warzek

Americas Applications Manager, Verigy

Technical Chair

Mary Israni

VP of Product Engineering, Nano Integrated Solutions

Marketing Chair

Cassandra Koenig

Americas and European Field Marketing Manager,

Verigy

Live Oak Madrone

Lower Level

MorganHill

SanMartin

Wo

men

Men

Monterey

SanJuan

Bautista

LowerLobby

Hayes Ballroom

Upper Level

Hayes I & II

HayesFoyerUpperLevel

Hayes Mansion