itron SMART TFT Modules PN28 SOM Series PN28 SOM Series ... SOMi5.pdf · itron SMART TFT Modules...

Noritake Itron Doc No: 49267 Iss5 14th Oct 2014 of 21

itron SMART TFT Modules PN28 SOM Series

Dimensions and Pin Assignment Copyright 2014, Itron UK Limited

PN28 SOM Series Hardware Specification pumaNova Compact System on Module

Customer Standard Product

Product Range PN28 SOM

Description Compact System on Module (SOM) for TFT Displays

Document Number 49267

Document Date 14th

October 2014

Document Issue 5

Product Overview

* 4.3”, 5.0, 5.6” & 7” Sizes * 480x272, 640x480, 800x480px

* Up to 16 million colours * LED Backlight Converter * 4.0V – 12.0V PSU Modes * Internal Battery Charging * USB High-Speed Host

* 450MHz ARM9 CPU * 512M byte RAM max * 4GB eMMC NAND * 8K EEPROM Memory * 4GB+ μSDHC Slot * 10/100 Ethernet PHY * USB OTG Host/Device

* 2x I2C 3V3/5V Logic * 2x SPI 3V3 Logic * RS232 & RS485 * RS422 Option * 3x Async 3V3 Interfaces * 2x FlexCAN Interfaces * Up to 50 User Digital I/O

* Up to 8 ADCs (1x HSADC) * Up to 7 PWM Outputs * SAIF Serial Audio Interface * SPDIF * Real Time Clock / Alarm * Linux / iDevOS / Win CE6

Applicable Products

Part Number Ethernet Switch RS232 / 485 5V I2C SD Slot eNAND DDR2

PN28-41A* NO NO YES YES 4GB+ x1 4GB 128MB

PN28L41A* YES NO YES YES 4GB+ x1 4GB 128MB

PN28L42A YES NO YES YES 4GB+ x1 4GB 256MB


PN28S41A* YES YES YES YES 4GB+ x1 4GB 128MB



Suffix A 20 mA current

Suffix B 40 mA current

Suffix C 120 mA current

Operating system Suffix iDevOS -iDev; Linux OS -LNX; Windows CE -CE6 * - Made to Order

This product is subject to change and controlled by version number increment.

Check www.itrontft.com for the latest update.

http://www.itrontft.com/




Index

Section Contents Firmware Notes Page

1 Change Log & Planned Changes 2

2 Product Description 3

3 Circuit Block Diagram 3

4 Electrical Characteristics 4

5 Environmental Characteristics 4

6 EMC Test Results 4

7 ESD Test Results 4

8 Mechanical Drawing 5

9 Functional Assignment 6

10 Connector Assignment 6

11 Connector Function 7

12 TFT Connector Assignment 9

13 Jumper Settings 9

14 CPU Features 10

15 Memory Options 10

16 ENET - Ethernet MAC Controller 10

17 Power On, Reset, Watchdog, Brown Out 11

18 I/O Ports iDevOS K0-Kxx, Linux GPIO 11

19 Asynchronous Communication iDevOS AS1,AS2, Linux TTYSP0,TTYSP3 11

20 RS232 Communication RS2 iDevOS RS2, Linux TTYSP0 11

21 RS485 Communication RS4 iDevOS RS4, Linux TTYSP1 11

22 I2C Communication iDevOS I2C, Linux driver required 12

23 SPI Interface iDevOS SPI, Linux driver required 12

24 FlexCAN 13

25 USB0 OTG (On-The-Go) Host/Device Interface iDevOS USB 14

26 USB1 High-Speed Host Interface iDevOS USB 14

27 SAIF - serial audio interface 15

28 SPDIF - Sony-Philips Digital Interface Format Transmitter

16

29 Analogue to Digital Conversion LRADC1-LRADC7 and HSADC

iDevOS ADC1-8, Linux driver required 16

30 Pulse Width Modulation PWM1 - PWM7 iDevOS PWM1-7, Linux driver required 16

31 Battery Charging 17

32 Product Image – Front and Rear 18

33 Packaging 19

34 Handling and Operating Precautions 19

Quick Reference Datasheet 20

1 – Change Log

Issue Changes / Additions Date

1 Document Transfer to PDF from DOC format 23/04/2014

2 Additional information about interfaces. The new section SPDIF 28/04/2014

3 Additional information about new I/O Ports 01/05/2014

4 Amended current and pin references added to assignment. Descriptive text amended 06/06/2014

5 Updated PCB (I2C, Jumper) changes, TFT connector assignment and updated parts nomenclature 14/10/2014

1.1 – Planned Changes

Item Date

More information about new I/O Ports Q4/2014

EMC Test Results Q4/2014

ESD Test Results Q4/2014




2 – Product Description

This PN SOM Module is a compact system on module (SOM) designed to control itron TN series TFT displays using a CPU block consisting of a 450MHz i.MX28 processor with up to 512M bytes of DDR2 RAM and the option to boot from SDHC card or internal eMMC NAND. A parallel µSDHC slot provides external SDHC/WIFI module interface. An 8Kbyte EEPROM provides non-volatile storage for boot patches, user application setup parameters and calibration values. The FPC connector supports direct connection to a TFT flexi providing 24 bit colour, constant current LED backlight supply and 4 wire resistive touch panel control. Backlight and touch panel control are also available via external pin out. The Ethernet port can be directly wired to an RJ45 or other connector with magnetics and status LEDs to provide web access for applications using a Linux browser or other data communications over the local network and internet. The modules are designed to be SMD bonded into a carrier PCB recess using IR reflow soldering or use a combination of pin headers and boxed connectors to optimize interconnection. Corner pins provide location and mounting to the rear of a TFT. Users have the option to select power supply modes dependent on power supply stability and back up battery type with up to 300mA of charge current available for 3.6VDC lithium ion rechargeable cells. USB cables rarely provide 5VDC from a PC due to voltage drop so we include a boost supply to support this eventuality. This module is designed to be RoHS compliant with sub class A EMI emission and 2kV human body contact model for resistive touch. 3 – Circuit Block Diagram




4 – Electrical Characteristics

Section Parameter Symbol Min Typ Max Unit Condition

5V Input Power Supply

Supply Voltage VCC1 4.0 5.0 12.0 VDC GND = 0V

Supply Current Icc1 800 mA Vcc1=5V – Subject to TFT backlight

Icc2 120 150 170 mA Vcc1=5V - LED backlight off

Icc3 40 51 70 mA Vcc1=5V – Reset LOW – std mode.

3V3 Output Power Supply

Supply Voltage VCC2 3.2 3.3 3.4 VDC GND = 0V

Supply Current ICC2 - - 200 mA VCC1=5V

Data Interfaces and I/O Ports

Logic Input Low VIL 0 - 0.5 VDC VCC2=3V3 User I/O, SDHC, ADC Maximum sink current 10mA per port Total sink current 70mA

Logic Input High VIH 2.0 - Vcc2 VDC

Logic Output Low VOL 0 - 0.7 VDC

Logic Output High VOH 3.0 - 3.4 VDC

I2C1 @ 5V / 3V3 Logic Input Low VIL -0.5 - 1.5 VDC Jumper selectable IOL=6mA

Logic Input High VIH 0.7*(Vcc) - 5.5 VDC

Logic Output Low VOL - 0.1 0.2 VDC

RS485 interface

Diff drive output VOD 1.5 - 3.4 VDC RL=54Ω max Max input drive +/-15V Rx diff threshold VTH -0.2 - 0.2 VDC

RS232 interface (RX)

Logic Input Low VIL -15.0 - 0.6 VDC VCC2=3V3

Logic Input High VIH 2.0 - +15.0 VDC VCC2=3V3

RS232 interface (TX)

Logic Output Low VOL - -3.0 -2.0 VDC VCC2=3V3

Logic Output High VOH 4.0 7.0 - VDC VCC2=3V3

/RESET Logic Input Low VIL 0 1.2 VDC Vcc1=5V

Logic Input High VIH 2.2 3.4 VDC Vcc1=5V

Backup Battery Sustain Voltage Vbb - 3.6 - VDC Offstate current 25µA (50 µA max)

If data signals are applied before the power supply stabilizes, the module CPU may not start correctly until a watchdog timeout.

5 – Environmental Characteristics

Parameter Value

Operating Temperature Range -20C to +70C

Storage Temperature Range -30C to +70C

Storage Humidity 30 to 80% RH @ 25C Non condensing

Vibration – non operating 10-55-10Hz, amplitude 1mm for 30mins XYZ

Shock – non operating 250m/s² 10ms XYZ

Printed Circuit Board 8 layer FR4 V0

Avoid applying uneven pressure to the circuit board, connector. Avoid magnetic fields which could induce currents within the touch screen.

6 – EMC Conducted and Radiated Emissions Test

TBA

7 – Electro Static Discharge Test

TBA




8 – Mechanical Drawing

Dimensions are in mm.




9 – Functional Assignment

10 – Connector Assignment

Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function

1 SD0-Det

I/O 15 K7 I/O 28 ENET-RX- 42 RS232CTS 56 VIN/VDD 69

IRQ K27

83 ADC6 97 3V3OUT

2 SD0-D1

I/O 16 K8 I/O 29 ENET-TX+ 43 RS232RTS 57 GND 70

I2C1-CK K24

84 ADC1 98 USB1+

3 SD0-D0

I/O 17 K9 I/O 30 ENET-TX- 44 RS232TX 58 PWM2BL 71

I2C1-DA K26

85 ADC0 99 USB1-

4 SD0-CK

I/O 18 K10 I/O 31 ENET-LED1 45 RS232RX 59

SPI2/SS2 I/O

72 VIN/VD 86 GND 100 USB0-

5 SD0-CD

I/O 19 K11 I/O 32 ENET-LED2 46 GND 60

SPI2/SS1 I/O

73 GND 87 HSADC 101 USB0+

6 SD0-D3

I/O 20 K12 I/O 33 GND 47 3V3OUT 61

SPI3/SS0 I/O

74 SA-MCLK

K23 88

SPDIF I/O

102 USB0ID

7 SD0-D2

I/O 21 K13 I/O 34 ADC2 48 PSWITCH 62

MISO3 I/O

75 SA-LRCLK

K22 89

SCK2 I/O

103 VIN/VDD

8 K0 I/O GND

22 K14 I/O 35 ADC3 49 WDOG

I/O 63

MOSI3 I/O

76 SA-BITCLK

K21 90

MOSI2 I/O

104 GND

9 K1 I/O

3V3OUT 23 K15 I/O 36 ADC4 50 BATT 64

SCK3 I/O

77 SA-D0

K20 91

MISO2 I/O

105 BATT

10 K2 I/O

CAN1TX 24 3V3OUT 37 ADC5 51 /RESET 65

AS1-CTS K30

78 SA-D1

I/O 92

SPI2/SS0 I/O

106 GND

11 K3 I/O

CAN1RX 25 GND 38 EN3V3 52 VIN/VDD 66

AS1-RTS K29

79 PWM0

I/O 93

I2C0-CK I/O

107 GND

12 K4 I/O

CAN0TX 26 ENET-CT 39

DIR-485 I/O

53 GND 67 AS1-TX

K28 80

PWM1 I/O

94 I2C0-DA

I/O (76) PWM5

13 K5 I/O

CAN0RX 27 ENET-RX+ 40

RS485-A I/O

54 BL-LED-K 68 AS1-RX

K25 81

PWM3 K19

95 AS2-TX

I/O (77) PWM6

14 K6 I/O

41 RS485-B

I/O 55 BL-LED-A

82

PWM4 K18 I/O

96 AS2-RX

I/O (78) PWM7

Pin 86

Pin 1

Pin 53

Pin 33




11 – Connector Function

Pin Signal Function

1 SD0-Det / I/O SD0 Current detect or user I/O

2 SD0-D1 / I/O SD0 Data1 or user I/O


4 SD0-CK / I/O SD0 SCK or user I/O

5 SD0-CD / I/O SD0 CMD or user I/O



8 K0 I/O / GND K0 user I/O or 0V for remote SD Card (when jumper J16 soldered)

9 K1 I/O / 3V3OUT K1 user I/O or 3V3out for remote SD Card (when jumper J17 soldered)

10 K2 I/O / CAN1TX FlexCAN1 transmit output or K2 user I/O

11 K3 I/O / CAN1RX FlexCAN1 receive input or K3 user I/O

12 K4 I/O / CAN0TX FlexCAN0 transmit output or K4 user I/O

13 K5 I/O / CAN0RX FlexCAN0 receive input or K5 user I/O

14 K6 I/O K6 user I/O










24 3V3OUT 3V3 output

25 GND 0V

26 ENET-CT Ethernet Center Tap

27 ENET-RX+ Ethernet RX+ – receive positive

28 ENET-RX- Ethernet RX- – receive negative

29 ENET-TX+ Ethernet TX+ – transmit positive

30 ENET-TX- Ethernet TX- – transmit negative

31 ENET-LED1 Ethernet LED1

32 ENET-LED2 Ethernet LED2

33 GND 0V

34 ADC2 ADC channel 2 input / Touch




38 EN3V3 Enable for 3V3OUT

39 DIR-485 / I/O RS485 direction control or user I/O

40 RS485-A / I/O RS485-A or user I/O

41 RS485-B / I/O RS485-B or user I/O

42 RS232CTS RS232 flow control input

43 RS232RTS RS232 flow control output

44 RS232TX RS232 transmit output

45 RS232RX RS232 receive input

46 GND 0V


48 PSWITCH The pin is can be used for CPU recovery

49 WDOG / I/O Watchdog strobe output or user I/O

50 BATT External positive battery connection

51 /RESET This pin resets the chip if it is low.

52 VIN/VDD 5Vin/out - set jumper J19: 1-2 for 5Vout, 2-3 for 5Vin; linked to pin 56 and pin 72

53 GND 0V




11 – Connector Function contd.

Pin Signal Function

54 BL-LED-K Backlight Cathode

55 BL-LED-A Backlight Anode

56 VIN/VDD 5Vin/out - set jumper J19: 1-2 for 5Vout, 2-3 for 5Vin; linked to pin 52 and pin 72

57 GND 0V

58 PWM2-BL PWM channel for backlight dimming control

59 SPI2 /SS2 / I/O SPI2 Slave Select /SS2 or user I/O



62 MISO3 / I/O SPI3 MISO data or user I/O

63 MOSI3 / I/O SPI3 MOSI data or user I/O

64 SCK3 / I/O SPI3 SCK clock or user I/O

65 AS1-CTS / K30 I/O AS1 flow control input or K30 user I/O

66 AS1-RTS / K29 I/O AS1 flow control output or K29 user I/O

67 AS1-TX / K28 I/O AS1 transmit output or K28 user I/O

68 AS1-RX / K25 I/O AS1 receive input or K25 user I/O

69 IRQ / K27 I/O I2C1 /IRQ or K27 user I/O

70 I2C1-CK / K24 I/O I2C1 SCL clock or K24 user I/O

71 I2C1-DA / K26 I/O I2C1 SDA data or K26 user I/O

72 VIN/VD 5Vin/out - set jumper J19: 1-2 for 5Vout, 2-3 for 5Vin; linked to pin 52 and pin 56

73 GND 0V

74 SA-MCLK / K23 I/O SAIF MCLK or K23 user I/O

75 SA-LRCLK / K22 I/O SAIF LRCLK or K22 user I/O

76 SA-BITCLK / PWM5 / K21 I/O SAIF BITCLK / PWM channel 5 output or K21 user I/O

77 SA-D0 / PWM6 / K20 I/O SAIF Data0 / PWM channel 6 output or K20 user I/O

78 SA-D1 / PWM7 / I/O SAIF Data1 / PWM channel 7 output or user I/O

79 PWM0 / I/O PWM channel 0 output or user I/O

80 PWM1 / I/O PWM channel 1 output or user I/O

81 PWM3 / K19 I/O PWM channel 3 output or K19 user I/O

82 PWM4 / K18 I/O PWM channel 4 output or K18 user I/O

83 ADC6 ADC channel 6 input



86 GND 0V

87 HSADC High-Speed ADC

88 SPDIF / I/O SPDIF output or user I/O

89 SCK2 / I/O SPI2 SCK clock or user I/O

90 MOSI2 / I/O SPI2 MOSI data or user I/O

91 MISO2 / I/O SPI2 MISO data or user I/O


93 I2C1-CK / I/O I2C0 SCL clock or user I/O

94 I2C1-DA / I/O I2C0 SDA data or user I/O

95 AS2-TX / I/O AS2 transmit output or user I/O

96 AS2-RX / I/O AS2 receive input or user I/O


98 USB1+ USB1 Host data+

99 USB1- USB1 Host data-

100 USB0- USB0 Host/Device data-

101 USB0+ USB0 Host/Device data+

102 USB0ID USB0 Host/Device select

103 VIN/VDD 5Vin/out for USB0 - set jumper J14: 1-2 for 5Vout (Host), 2-3 for 5Vin (Device);

104 GND 0V

105 BATT External positive battery connection

106 GND 0V

107 GND 0V




12 – TFT Connector Assignment Pin TFT connector

1 VLED- - Backlight Cathode

2 VLED+ - Backlight Anode

3 GND - Ground

4 VDD - Power source

5 R0 - Red data signal








13 G0 - Green data signal








21 B0 - Blue data signal








29 GND - Ground

30 PCLK - Clock signal to sample data

31 DISP - Display on/off (H/L) signal

32 HSYNC - Horizontal synch. signal

33 VSYNC - Vertical synch. signal

34 DE - Input data enable control

35 NC - No connection

36 GND - Ground

37 TOUCH - Right

38 TOUCH - Bottom

39 TOUCH - Left

40 TOUCH - Top

13 – Jumper Settings

Name Description Function

J4 I2C 3V3 / 5V Logic I2C level shifter voltage : 1-2 for 5V 2-3 for 3V3

J10, J11, J12, J14 Boot Mode Internal boot selection, do not change

J13 5Vin/Vout 5V in/out selector for USB0: 1-2 for 5Vout, 2-3 for 5Vin

J15 Battery option Solder this jumper for a large external battery.

J16, J17 Remote SD Card Solder this jumpers for GND for the pin 8 and 3V3out for the pin 9

J19 5Vin/Vout 5V in/out selector for pin 52,56,72: 1-2 for 5Vout, 2-3 for 5Vin

J21 BL Control Option BL control: disabled BL no links, 1-2 PWM2 control, 2-3 force on

J31 BL Current Doubler / Voltage Booster Open = 20 mA, Short = 40 mA, 8R Resistor = 140 mA




14 – CPU Features

The i.MX287 is the most feature rich device in the i.MX28 family. The i.MX28 family of multimedia applications processors is the latest extension of Freescale's ARM9™ product portfolio. Optimized for performance and power consumption, the i.MX287 boasts of a premium feature set that includes: dual CAN, dual Ethernet, and LCD touch screen. The ARM926 Platform consists of the ARM926EJ-S™ core and the ETM real-time debug modules. It contains the 16-Kbyte L1 instruction cache, 32-Kbyte L1 data cache, 128-Kbyte ROM and 128-Kbyte RAM. Features

* 454MHz ARM926EJ-S core with 16KB/32KB Cache * PMU with high efficiency on-chip DC/DC, supports Li-Ion batteries * 10/100 IEEE® 1588 Ethernet * Dual CAN interfaces * LCD Controller with Touchscreen * NAND support – SLC/MLC and eMMC 4.4 managed * Hardware BCH (up to 20-bit correction) * 200 MHz 16-bit DDR2, LV-DDR2, mDDR external memory support * Dual High speed USB with embedded PHY * 7 General purpose 12-bit ADC channels and single 2 Msps ADC channel * Temperature sensor for thermal protection * Multiple connectivity ports (UARTs, SSP, SDIO, SPI, I2C, I2S) * 3.3V I/O, 10 year lifetime (Industrial) * Temperature – -40C to +85C (Industrial)

15 – Memory Options

TW-SOBM supports various memory options: 2x 4G+ SD cards, up to 256MB NAND and up to 512MB DDR2 RAM.

SD Card/NAND Part Number Options * S2 – 2x 4G+ SD card slots without NAND memory * SN1 – 1x 4G+ SD card slot and 128MB NAND memory * SN2 – 1x 4G+ SD card slot and 256MB NAND memory

DDR2 DRAM Part Number Options * R1– 128MB DDR2 memory * R2– 256MB DDR2 memory * R4– 512MB DDR2 memory 16 – ENET - Ethernet MAC Controller

The Ethernet controller (ENET) consists of two MACs (media access controllers), each with it's own dedicated uDMA (unified DMA) module. The MAC module is third party IP from "More Than IP" (MTIP). The MACs interface to 10 Mbps and 100 Mbps Ethernet/IEEE 802.3™networks. MAC0 is provided on the SOBM as standard. MAC1 is provided as custom for external PHY.

ENET Overview Block Diagram

The interface can wire to an RJ45 connector with integrated magnetics and status LEDs to provide web access for applications using a Linux browser or other data communications over the local network and internet.




17 – Power On, Reset, Watchdog and Brownout Protection

At POWER ON the internal and external 3V3 supply will rise in <20ms to supply the CPU and peripheral circuits. On /RESET, the peripheral supply is disconnected until 3V3OUTPUT is enabled. During power off the RTC can be maintained by a backup battery or separate power source. The watchdog and brownout protection are internal functions of the CPU but an external supervisor can also be used. 18 – I/O Ports

Many I/O ports have dual or triple functions as a general purpose logic level inputs/outputs or a fixed function interface. During reset and at power on all I/O ports are tri-state so it is important to provide an inverting circuit to ensure a low condition where required. Pull up resistors can be activated for each input and interrupts assigned for counting and other trigger functions by the firmware. 19 – Asynchronous Communication

The TW Series has two asynchronous interfaces: AS1 and AS2.

The asynchronous logic level (3V3) interfaces have a theoretical maximum baud rate of 3.2M bits per second subject to inter-connection. The baud rate, data orientation, stop bits, handshaking, buffer size and associated interrupts can be configured by the firmware. AS1 output MB - Module Busy and input HB - Host Busy support hardware handshaking between master and slave.

20 – RS232 Communication RS2

The RS232 interface has a theoretical maximum baud rate of 3.2M bits per second subject to inter-connection. The interface buffer IC provides a limited negative and positive supply (-3V,+7V) suitable for short distance, low load applications.

The baud rate, data orientation, stop bits, handshaking, buffer size and associated interrupts can be configured by the firmware. CTS and RTS can be selected depending on the required handshaking method.

21 – RS485 Communication RS4

A half-duplex two wire RS485 using a differential driver IC. RS485 can be used at the same time as RS232 RXD/TXD/CTS/RTS.

The Tx/Rx lines are high impedance when not used. Care must be taken not to exceed the maximum loading of 8 devices per line. Please consult us if a higher loading is required. Line termination should be external.

Rx/Tx

START D7 D0 STOP

Data 1

START D7 D0 STOP

Data 2

START D7 D0 STOP

Data 3

SI/SO

MB/HB

START

Data 1

D7 D0

Data 2

D7 D0 STOP

Data 3

D7 D0 STOP

STOP

START START

Buffer Full

RXD/TXD

START D7 D0 D7 D0 STOP

D7 D0 STOP

STOP

START START

CTS/RTS

Data 1 Data 2 Data 3 Buffer Full




22 – I2C Communication

The I2C is a standard two-wire serial interface used to connect the chip with peripherals or host controllers. This interface provides a standard speed (up to 100 kbps), and a fast speed (up to 400 kbps) I2C connection to multiple devices with the chip acting in either I2C master or I2C slave mode.

I2C Interface Block Diagram

The TW-SOBM module has two I2C interfaces. The I2C0 has 3V3 logic. For the I2C1 a level shifter is fitted for open collector drive at 3V3 or 5V (jumper selectable).

A START condition is signaled by driving SDA low while SCL is high. A STOP condition is signaled by driving SDA high while SCL is high. After a START condition is detected by the slave followed by ‘SLA+W’ with the 7 bit address and Read/Write from the master, the slave signals acceptance by raising the ACK bit. When a STOP condition is detected the data received is processed. The /IRQ can be used by a slave device to signal the host that data is available for read. When not active, the port is set to input and when active the port is set to output low. 23 – SPI Interface

Two SPI interfaces are available: SPI2 and SPI3. The theoretical maximum speed is 3.2M bits per second subject to inter-connection. The order of data bits and the rising or falling edge of clock can be defined in software In slave mode, the /SS (slave select) signal is used as a device select and must be low when clocking data in/out. Internal display receive / transmit logic is reset and resynchronized on the rising edge of /SS. Data is clocked into input MOSI and out of output MISO simultaneously on the software selected edge of SCK. The MB port can be enabled to signal the module is busy. In master mode the /SS or other I/O ports can be software configured as slave select to interface to multiple devices. Data is clocked out of output MOSI and in to input MISO simultaneously on the software selected edge of SCK. The example below shows clocking on the rising edge of SCK.

/SS

SCK

MOSI

MISO

D0 D7 D0 D7

SDA

SCL

START SLA+W

Addr MSB

Addr LSB R/W ACK

1 7 8 9

Data 1

MSB LSB ACK

1 8 9

Data n

MSB LSB ACK

1 8 9

STOP




24 – FlexCAN

The TW-SOBM module has two FlexCAN implementations CAN0 and CAN1 requiring just an external interface buffer IC.

FlexCAN Block Diagram

The Controller Area Network (CAN) protocol is a message based protocol used for serial data. It was designed specifically for automotive but is also used in industrial control and medical applications. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0B, which supports both standard and extended message frames. The Message Buffers are stored in an embedded RAM dedicated to the FlexCAN module. The serial data bus runs at 1 Mbps.

FlexCAN Timing Diagram Timing Diagram for FlexCAN Standby Signal

Timing Diagram for FlexCAN Shutdown Signal Timing Diagram for FlexCAN Shutdown-to-Standby Signal




25 – USB0 High-Speed OTG (On-The-Go) Host/Device Interface

The USB0 module provides high-performance USB On-The-Go (OTG) and host functionality (up to 480 Mbps), compliant with the USB 2.0 specification and the OTG supplement. The module has DMA capabilities for handling data transfer between internal buffers and system memory. When the OTG controller works in device mode, it can only work in FS or HS mode. The jumper J55 can be used to allow the USB0 host supply power to the module.

USB 2.0 Device Controller Block Diagram

26 – USB1 High-Speed Host Interface

The controller operates as host-only high-speed USB controller. Please refer to the web for USB 2.0 specification details.




27 – SAIF - serial audio interface

SAIF provides a half-duplex serial port for communication with a variety of serial devices, including industry-standard codecs and DSPs. It supports a continuous range of sample rates from 8 kHz–192 kHz using a high-resolution fractional divider driven by the PLL. Samples are transferred to/from the FIFO through the APBX DMA interface, a FIFO service interrupt, or software polling.

Serial Audio Interface (SAIF) Block Diagram

The SAIF is a half-duplex port, meaning it can either transmit or receive PCM audio, but not simultaneously. Data is communicated serially one sample at a time, alternating between left and right samples. One to two serial data lines (SDATA0 – SDATA1) can be used to transmit channels of digital PCM audio data. Samples boundaries are delineated by a left/right clock (LRCLK) pin and individual bits within each sample are delineated by a bit clock (BITCLK) pin. The LRCLK can be programmed to toggle every 16, 24, or 32 BITCLK transitions and because data ranges from 16 to 24 bits, serial data within each LRCLK period can either fully occupy the LRCLK cycle or cause the LRCLK period to contain BITCLK cycles in which no data is being communicated. Because of this, three basic types of sample frame formats can be programmed: I2S, left-justified, and right-justified. However, many programming options exist to alter these basic frame types, such as the LRCLK signal polarity, BITCLK edge selection to drive/sample serial data, and sample justification/delay within an LRCLK period. For codecs that do not contain their own PLL, or in applications where including a crystal oscillator to drive the codec is not desired, the SAIF can provide a master clock (MCLK) reference that can be configured from 512x down to 32x the audio data's sample rate. This master clock is used by the off-chip codec for all of its internal logic and to synchronize the BITCLK/LRCLK/SDATA inputs for DAC operation. The digital PCM audio sample rate is determined by programming a fractional divider within the clock controller module.

SAIF Transmitter Timing Diagram SAIF Receiver Timing Diagram Where: SS1 - BITCLK period; SS2 - BITCLK high period; SS3 - BITCLK rise time; SS4 - BITCLK low period; SS5 - BITCLK fall time; SS6 - BITCLK high to LRCLK high; SS7 - BITCLK high to LRCLK low; SS8 - LRCLK rise time; SS9 - LRCLK fall time; SS10 - BITCLK high to SDATA valid from high impedance; SS11 - BITCLK high to SDATA high/low; SS12 - BITCLK high to SDATA high impedance; SS13 - SDATA rise/fall time; SS14 - BITCLK high to LRCLK high; SS15 - BITCLK high to LRCLK low; SS16 - SDATA setup time before BITCLK high; SS17 - SDATA hold time after BITCLK high




28 – SPDIF - Sony-Philips Digital Interface Format Transmitter

The Sony-Philips Digital Interface Format (SPDIF) transmitter module (the connector CN23) transmits data according to the SPDIF digital audio interface standard (IEC-60958). Data samples are transmitted as blocks of 192 frames, each frame consisting of two 32-bit sub-frames. A 32-bit sub-frame is composed of a 4-bit preamble, a 24-bit data payload (that is, a left or right-channel PCM sample), and a 4-bit status field. The status fields are encoded according to the IEC-60958 consumer specification.

PWM Timing

29 – Analogue to Digital Conversion LRADC1-LRADC7 and HSADC

The ADC reference voltage is connected to the 3V3 supply. The ADCs have a 12 bit resolution producing conversion values of between 0 for 0V and 4095 for 3V3 with a tolerance of 5. Since the value at 0V may not be 0, it is important to take this into consideration when designing your analogue interface circuit if a zero value is important. The maximum sample rate is 428kHz and is available for processing according to the firmware configuration. Calibration values can be retained in the host or stored in the on board EEPROM. The high-speed ADC (HSADC) module is designed for driving the linear image scanner sensor. It can also support some other general user cases which need to sample analog source with up to 2 Msps data rate and then move the sample data to the external memory. The HSADC module integrates an 12-bit analog ADC module. This analog ADC module can support up to 2 Msps sample rate. In order to improve the flexibility, the high-speed ADC module can co-work with PWM module which can generate driving signals of external device such as the linear image scanner sensor. The PWM can also generate trigger signal which is synchronous with high-speed. 30 – Pulse Width Modulation PWM1 - PWM7

The PWM can be programmed to select one of two clock signals as its source frequency: xtal clock or hsadc clock. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse width modulator output (PWMO) external pin. PWM also supports MATT mode. In this mode, it can be programmed to select one of two clock signals as its source frequency, 24-MHz or 32-kHz crystal clock. For a 32-kHz source clock input, the PWM outputs the 32-kHz clock directly to PAD. The PWM2 is available for the user if the backlight brightness is then fixed at 100% using to relevant jumper link.

PWM Timing

Where: 1 - System CLK frequency; 2a - Clock high time; 2b - Clock low time; 3a - Clock fall time; 3b - Clock rise time; 4a - Output delay time; 4b - Output setup time.




31 – Battery Charging

The power supply is powered by a Li-ion battery or 5 V power source. The onboard trickle charging circuitry and a highly-efficient and comprehensive i.MX28 power supply allow direct connection of a small 3.6V rechargeable battery for the RTC backup or a large battery to power the whole module. Both options require software setup.

i.MX28 PMU is powered by a Li-ion battery or 5 V power source and generates five internal power rails through two separate supplies.

The battery charger is essentially a linear regulator that has current and voltage limits and it can fully charge a Li-ion battery with a 5 V supply. The PMU should be configured to use the 4P2 source for the DC-DC converter when a load is removed from a battery that is being charged. This allows the battery to reach its fully charged state even if the battery is loaded normally. The battery charger has a two-stage operation - constant current (only large battery) and constant voltage. In the constant current state, the charge current is set by the application and the battery voltage is set below 4.2 V. As the battery receives current, the battery voltage rises. When the battery voltage reaches 4.2 V, the battery charger hardware lowers the current while keeping the battery voltage at 4.2 V. This begins the constant voltage stage. The hardware continues to lower the current until an internal current sensor detects that the battery current has reached a pre-determined threshold which is set by the application. This ends the battery charging process.

Constant Current and Constant Voltage Operation




32 – Product Image

Front Side

Rear Side




33 – Packaging

Modules are packaged in single or dual antistatic carbon coated card sleeves dependent on connectors being fitted on user request. The sleeves are then packed in a sub box containing 5 or 10 modules and these are then dispatched in shipping boxes. Products may be packed in anti-static bubble bags when the selected connector or other sub-assembly does not fit the standard sleeves. 34 – Handling and Usage Precautions when used with a TFT

Please follow the appropriate product specification and other documents for proper usage, safe handling and operation standards for maximum performance. TFT panels are made of glass and contain liquid crystal materials

Please avoid breaking the TFT panel to prevent injury from sharp glass particles.

It is recommended to allow sufficient open space surrounding the TFT panel to avoid possible damage.

Please design the mounting of the TFT module to have within 0.5 mm warping tolerance to avoid any forces that may damage the display due to PCB distortion causing a breakdown of the electrical circuit leading to TFT module failure.

Conducting voltage

Avoid touching conductive electrical parts with other conductive materials because the TFT-module may be damaged.

Even when electric power is turned off, it may take more than one minute for the electrical current to discharge. Cable connection

Do not unplug the power and/or data cables of TFT modules during operation because unrecoverable damage may result.

Sending input signals to the TFT module during a power off condition sometimes causes I/O port damage.

It is recommended to use a 30 cm or shorter signal cable to prevent functional failures subject to port application. Electrostatic charge

TFT modules require electrostatic free packaging and protection from electrostatic charges during handling and usage. Structure

During operation, TFT panels and TFT modules generate heat. Please consider sufficient heat radiation dissipation.

We prefer to use UL grade materials or components in conjunction with TFT modules.

Wrap and twist motion causes stress and may break the TFT or TFT module components. Please adhere to allowances within 0.5mm at the point of attachment.

Power

Apply regulated power to the TFT module within the specified voltages to protect from failures.

A TFT module may consume an in rush current equal to twice the typical current at power-on due to capacitor charging. We recommend using a power supply capable of quick starting.

TFT-module needs a specified voltage at the point of connection. Please use an adequate power cable to avoid a decrease in voltage. We recommend the provision of a fuse since the onboard TFT module fuse is SMT soldered.

Operating consideration

The LED backlight will decrease in brightness during extended operation. If a fixed pattern illuminates on a TFT panel for an extended period, this will result in a retained ghost image. Please consider a screen safer to reduce this effect.

We recommend using a signal cable 30cm or less to avoid noise with a ferrite fitted to reduce emission. Storage and operating environment

Please use TFT-modules under the recommended specified environmental conditions. Salty, sulfur and dusty environments may damage the TFT module even during storage.

Disposal

When discarding TFTs or TFT modules, please adhere to governmental related laws or regulations. Others

Although the TFT modules are designed to be protected from electrical noise, please plan your circuitry to exclude as much noise as possible.

Do not reconstruct or repair the TFT module without our authorization. We cannot assure the quality or reliability of unauthorized repaired TFT modules.

Notice: ･We do not authorize the use of any patents that may be inherent in these specifications. ･ Neither whole nor partial copying of these specifications are permitted without our approval. If necessary, please ask for assistance from our sales management. ･ This product is not specifically designed for military, aerospace, medical or other life-critical applications. If you choose to use this product for these applications, please consult us prior to the project design phase.

Antistatic Sleeve or Bag Sub Box

Shipping Box




Features

* 4.3”, 5.0”, 5.6” & 7.0” TFT Options * 480x272, 640x480, 800x480 px * Up to 16 million colours * LED backlight converter * 4.5V - 5.5V PSU Modes * Internal Battery Charging * 450MHz iMX28 ARM9 CPU * 512MB RAM max * 4GB eMMC NAND * 8K EEPROM Memory * 4GB+ µSDHC Slot * 2x I2C 3V3/5V Logic * 2x SPI Interface 3V3 Logic * RS232 & RS485. RS422 Option * 3x Async 3V3 * 2x FlexCAN Interfaces * Up to 50 User Digital I/O * USB OTG Host/ Device * USB High-Speed Host * 10/100 Ethernet + Magnetics * Up to 8 ADCs (1x HSADC) * Up to 7 PWM Outputs * SAIF - Serial Audio Interface * SPDIF * Real Time Clock / Alarm * Linux / iDevOS / Windows CE

Electrical Characteristics

Section Parameter Symbol Min Typ Max Unit Condition

5V Input Power Supply

Supply Voltage Vcc1 4.5 5.0 12 VDC GND = 0V

Supply Current Icc1 150 800 mA Vcc1=5V – TFT backlight off

Icc2 40 50 70 mA Vcc1=5V – Reset LOW

3V3 Output Power Supply

Supply Voltage Vcc2 3.2 3.3 3.4 VDC GND = 0V

Supply Current Icc2 - - 200 mA Vcc1=5V

Data Interfaces and I/O Ports

Logic Input Low VIL 0 - 0.5 VDC VCC2=3V3 User I/O, SDHC, ADC Maximum sink current 10mA per port Total sink current 70mA

Logic Input High VIH 2.0 - Vcc2 VDC

Logic Output Low VOL 0 - 0.7 VDC

Logic Output High VOH 3.0 - 3.4 VDC

I2C1 @ 5V / 3V3

Logic Input Low VIL -0.5 - 1.5 VDC Jumper selectable Iol=6mA

Logic Input High VIH 0.7*(Vcc) - 5.5 VDC

Logic Output Low VOL - 0.1 0.2 VDC

RS485 interface

Diff drive output VOD 1.5 - 3.4 VDC RL=54Ω max Max input drive +/-15V Rx diff threshold VTH -0.2 - 0.2 VDC

RS232 interface (RX)

Logic Input Low VIL -15.0 - 0.6 VDC VCC2=3V3

Logic Input High VIH 2.0 - +15.0 VDC VCC2=3V3

RS232 interface (TX)

Logic Output Low VOL - -3.0 -2.0 VDC VCC2=3V3

Logic Output High VOH 4.0 7.0 - VDC VCC2=3V3

Pin Connector Assignment

Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function

1 SD-Det 15 P15 28 ENET-RXN 42 RS232CTS 56 VIN 69 IRQ 83 ADC6 97 3V3OUT

2 SD-D1 16 P16 29 ENET-TXP 43 RS232RTS 57 GND 70 I2C1-CK 84 ADC1 98 USBDP

3 SD-D0 17 P17 30 ENET-TXN 44 RS232TX 58 BL-PWM 71 I2C1-DA 85 ADC0 99 USBDM

4 SD-CK 18 P18 31 ENET-LED1 45 RS232RX 59 /SS2 72 VIN 86 GND 100 USBHM

5 SD-CD 19 P19 32 ENET-LED2 46 GND 60 /SS1 73 GND 87 HSADC 101 USBHP

6 SD-D3 20 P20 33 GND 47 3V3OUT 61 /SS0 74 SA-MCK 88 SPDIF 102 USBID

7 SD-D2 21 P21 34 ADC2 48 PSWITCH 62 MISO3 75 SA-LRCLK 89 SCK2 103 VIN/VDD

8 P8/GND 22 P22 35 ADC3 49 WDOG 63 MOSI3 76 SA-BITCK 90 MOSI2 104 GND

9 P9/3V3OUT 23 P23 36 ADC4 50 BATT 64 SCK3 77 SA-D0 91 MISO2 105 BATT

10 CAN1TX 24 3V3OUT 37 ADC5 51 /RESET 65 AS1-CTS 78 SA-D1 92 /SS3 106 GND

11 CAN1RX 25 GND 38 EN3V3 52 VIN/VDD 66 AS1-RTS 79 PWM0 93 I2C0-CK 107 GND

12 CAN0TX 26 ENET-CT 39 DIR-485 53 GND 67 AS1-TX 80 PWM1 94 I2C0-DA (76) PWM5

13 CAN0RX 27 ENET-RXP 40 RS485-A 54 BL-LED-K 68 AS1-RX 81 PWM3 95 AS2-TX (77) PWM6

14 P14 41 RS485-B 55 BL-LED-A 82 PWM4 96 AS2-RX (78) PWM7

PIN 86 PIN 53

PIN 33

QUICK REFERENCE DATASHEET

PIN 107




Environmental Characteristics

Parameters Value

Operating Temperature Range -20C to +70C

Storage Temperature Range -30C to +70C

Storage Humidity 30 to 80% RH @ 25C Non condensing

Vibration – non operating 10-55-10Hz, amplitude 1mm for 30mins XYZ

Shock – non operating 250m/s² 10ms XYZ

Printed Circuit Board 8 layer FR4 V0

Applicable Products

Part Number Ethernet LAN Switch RS232 / 485 5V I2C SD Slot eNAND DDR2

PN28-41A* NO NO YES YES 4GB+ x1 4GB 128MB


PN28L42A YES NO YES YES 4GB+ x1 4GB 256MB





Suffix A/B/C 20 mA/40 mA/ 120 mA current

OS Suffix iDevOS -iDev; Linux OS -LNX; Windows CE -CE6 * - Made to order

Mechanical Dimensions

Component Assignment

Product Image

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