ISUAL Sprite Imager Electronic Design Stewart Harris.

ISUAL Sprite Imager Electronic Design

Stewart Harris

NCKU UCB Tohoku Sprite Imager S. Harris

CDR 9 Jul 2001 2

Outline

• Imager Circuit and Electronics Design• Electronics Design and Fabrication Status


CDR 9 Jul 2001 3

Imager Electronics Locations

Daylight Sensor

Filter Wheel Motor

MCP HV Supply

Phosphor HV Supply

Front End Electronics

(FEC)

Electrical Board

Filter Wheel Position Sensor


CDR 9 Jul 2001 4

Imager Electrical Block Diagram

CCD

TEC

Intensifier

Filter Wheel Motor

Filter Wheel

Position Sensor

Day-Light

Sensor

Front End Electronics

Imager Electrical Board

Photocathode Power Supply

Motor Driver

Phosphor HVPS

MCP HVPS

J1

J3J4

J2

Heater and Thermistor Circuits

not shown

StimLED


CDR 9 Jul 2001 5

Imager Connector Locator

J1Imager

Electrical Board

J4Phosphor

High Voltage

J3MCP High Voltage

J2Front End

Electronics


CDR 9 Jul 2001 6

Image Intensifier Interface

Imager Electrical Board

J1 - 44 pin


Image Intensifier - 25 mm

MCP-Out-1kV

HV Supply

Phosphor (Anode -6kV) HV Supply

GATEFEC Connector

J4 - 9 pin J3 - 9 pin

MCP-In GND


CDR 9 Jul 2001 7

Imager Electrical Board Functions

• Connections– Thermistors

• TEC hot side

• Lens (front and rear)

• Filter Wheel

• Filter Motor

• Daylight Sensor

• Survival (spacecraft)

– Heater Circuits• Lens (front and rear)

• Filter Wheel

• Survival (spacecraft)

– Thermoelectric Cooler (TEC)• Power controlled from AEP

– Stim Source

• Active Electronics– Photocathode Power Supply

• On/off control

• Gate control from FEC

– Filter Wheel Motor Driver• Stepper motor (2 phases)

• Position indicators (2 bits)

Interface Ref Doc: 8439-A4F


CDR 9 Jul 2001 8

Motor Controller Schematic


CDR 9 Jul 2001 9



CDR 9 Jul 2001 10

Daylight Sensor Electronics

• Specifications– Purpose: Control HV Power Supplies

On/Off

– Number of Channels: 2

– Sensor: 2 x UDT PIN-44DPI (per Channel)

– Spectral band: 420 - 780 nm

– Field of View: 2π

– Threshold current: 4 nA (sum of 2 photodiodes) (1E6 photons/pixel/sec on Imager)

– Range of detection: 0.1 to 1000 nA

– Output: 0 to 5V


CDR 9 Jul 2001 11

Daylight Sensor Schematic

C827nF

+

-

U2B

AD822

5

67

-2V-AA

OUTPUT-A

Iref R1

50M

+5V-AA

R14

20.0K

+

-

U1B

AD8225

67

Q1

MAT02

2

1

3

6

5

7

C4220pF

+5V-AA

1.5V

R37

49.9

R11

20.0K

U3

AD584

8

65

7

4

321

V+

VBGSTB

CAP

CO

M

2.5V5V10

C227nF

D2

PIN-44DPI

12

3

R53.92K

C1227nF

D1

PIN-44DPI

12

3

C6 220pF

R161K @ 25C3500 ppm/C

C7 2.0nF

R1810.0K

R13

15.0K

R85.90K

+5V-AA

+

-

U2A

AD822

3

21

84

R17

10.0K

R3

2.00K

+

-

U1A

AD822

3

21

84

50 nAC127nF

C9

27nF

One Channel Shown Ref schematic: 8798-O9A


CDR 9 Jul 2001 12

Daylight Sensor Circuit Performance

10-2

10-1

100

101

102

103

104

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5Log Amp Performance -- 2x PIN-44DPI -- 24 May 2001

Current (nA)

Out

put

Vol

tage

(V

)


CDR 9 Jul 2001 13

Temperature Stability - Daylight Sensor Circuit

-80 -60 -40 -20 0 20 40 602

2.2

2.4

2.6

2.8

3

3.2

Log Amp Temperature Stability -- 21 May 2001

Temperature (deg C)

Out

put

Vol

tage

(V

)

12 nA

5 nA

1.5 nA


CDR 9 Jul 2001 14

Front End Electronics Interface

• Data[0..11]– 12 bits per pixel

• PixelClock (PIXCLK)

– pixel data strobe

• FrameValid (FRMV)

– indicates duration of frame

• LineValid (LINV)

– indicates duration of line

– used only during test

• Busy (BUSY)

– signals start of EXP

• Acquire (ACQ)

– enables modes

• Event Trigger (ETRIG)

– signals Spite Event

• CommandData (CDI)

– serial data interface for upload of camera parameters

• VoltageMonitor (MON)

– switched analog output

• Power– dc voltages

Images are transferred to the AEP in data frames,each frame is 128 lines x 512 pixels

Interface Ref Doc: 8652-X7A


CDR 9 Jul 2001 15

VoltageMonitor

Data9Data8Data7Data6Data5Data4Data3Data2

PixelClockFrameValid

Acquire

CommandDataCommandClockCommandStrobe

+5VA+12VA-5VA-12VA+29VAGND+5VDDGND

Reset Gate

Summing Gate

CR1 - Horizontal

CR2 - Horizontal

CR3 - Horizontal

CI1 - ImageArea

CI2 - ImageArea

CI3 - ImageArea

CS1 - Storage

CS2 - Storage

CS3 - Storage

Driver BoardAss'y 8744

RSTC

SUMGC

CR1C

CR2C

CR3C

CI1C

CI2C

CI3C

CS1C

CS2C

CS3C

Ass'y 8748Digital Board

ADCLK

ADSEL

DATE

Analog ProcessorBoard

Ass'y 8747

CRHI (+8.5)

CRLO (+3.5)

RSTHI (+14)

RSTLO (+4)

CISLO (-2.5)

CISHI (+10.5)

CISV+ (+17)

CRV+ (+15.5)

RSTV+ (+19)

CISV- (-3)

VNS (+26) / VPS (+1.5)

VDD (+20) / VOD (+15)

VCS (+2.5) / VSET (+5)

VCSET (-5) / VSS (GND)

CCDTEMP

VNS / VPS / VSS

VDD / VOD

VCS / VSET

CCDTEMP

VPH

IA1

VPH

IA0

Mo n

Sel3

N

Mo n

Sel3

Mo n

Sel2

Mo n

Sel1

Mo n

Sel0

Bias BoardAss'y 8746

Out

A

Out

B

ToAll

Boards

CCD BoardIA-D4

ImageIntensifier

Phosphor HVPS

MCP HVPSMCPAdjust

Photocathode PS

CI4 - ImageArea

CS4 - Storage

Ass'y 8742

CI4C

CS4C

PCGATE

Data0Data1

Data11Data10

+5VP+12VP-12VPCOM

CCD Temp

BusyEventTrig

PowerSupplyBoard

Ass'y 8768

Front End Electronics Block Diagram

J2


CDR 9 Jul 2001 16

CCD Bias Design

C3810nF

+28VA

+ C511.0uF50V

IN

ADJ

OUT1 3

2

U6LM117H

L7

Bead+12VA

C2527nF

R253.40K

D5

1N5711

+5V

+ C301.0uF35V

R21825

R45499

+ C351.0uF35V

C2610nF

26V

R38

10.0

BVNS

R19

10.0K

Bias BoardSchematic: 8561-O9

BVPS

C4510nF

+ C244.7uF10V

2.5V

R363.40K

+ C541.0uF50V

+C464.7uF

10V

R379.09K

R267.50K

+C374.7uF

10V

Q22N2907A

J71-31

IN

ADJ

OUT1 3

2

U15LM117H

R326.65K

+ C234.7uF10V

+ C521.0uF50V

+ C531.0uF50V

BVCS

R4614.3K

R30

10.0K

L11

Bead

R29

6.65K

BVSET

1.5V

R412.00K

R4728.0K


CDR 9 Jul 2001 17

Clock Driver Design

IN

ADJ

OUT1 3

2

U7LM117H

CRHI

15.5V

CRLO

Bias Board8561-O9

R1214.3K

C1227nF

L1

Bead

R157.50K

R1

10.0

Q3

2N2907A

C627nF

S1IN1D1

V+ VL

D4IN4

S4

D2IN2

S2

D3IN3

S3

V- GND

U7

DG613

132

13

14

11

7

16

9

86

15

10

4 512

JP1

+ C184.7uF10V

R44.75K

+ C101.0uF35V

CR1

C227nF

C2427nF

+ C52.2uF20V

JP2

3.5V

R582.5K

+ C234.7uF10V

C1100nF

50 V

L4

Bead

Driver Board8560-O9

+ C194.7uF10V

+5VA

+ C11.0uF35V

+5VA

8.5V

+ C32.2uF20V

C2027nF

R1825

CR1C

+ C134.7uF10V

+12VA

+ C112.2uF20V

R104.64K

JP4

JP3

CRV+

+ C194.7uF10V

+ C22.2uF20V


CDR 9 Jul 2001 18

MUX

Analog Data Chain

Correlated Double Sampling (CDS)

ADC

CCD

Correlated Double Sampling (CDS)

ADC

Preamp/Clamp

Preamp/Clamp

Buffer

RLOAD

Buffer

RLOAD

CCD Board8559-O9

Driver Board

8560-O9

Analog Processor Board8562-O9

RS-422 Drivers

OS1

OS2


CDR 9 Jul 2001 19

Preamp Design

R21

10.0K

R37

10.0K

-5V-AA

R6

100

R1710.0K

R3110.0

S1IN1D1

V+ VL

D4IN4

S4

D2IN2

S2

D3IN3

S3

V- GND

U4

DG613

132

13

14

11

7

16

9

86

15

104 5

12

HBLANK1

R1610.0K

+

-

U1

HS1135RH

3

265

8

74

R18

1.00K

Q2

2N2857

CCD Board8559-O9

R15

49.9

VDD

R19287

R14

100

C139

100nF100V

R53.01K R7

2.49K

OS1

-5V-AA

FROM CCD

Driver Board8560-O9

C14022pF

J73SMA

+5V-AA


CDR 9 Jul 2001 20

CDS Design

AD9240

ADC

1Input

Analog Processor Board8562-O9

-5V-AAR5

5.90K

+5V-AA

R7

165

R10182

+

-

U1

HS1135RH

3

265

8

74

R6

475

R4

40.2

R3

475

R3049.9

L150 ns

1 2

3

J83SMA R8

SAT

-5V-AA


CDR 9 Jul 2001 21

Digital Control

CPCLK

M8

M5

RMS1

CSTB

CR1CN

R43 10.0K

ETRIG

CCLK

CI1CN

CR2CN

CI3CN

M12

MCLK

CS2CN

POR

RVPH

IA0

FRMV

RDAT

E

PIXCLK

CI4CN

U1

A1280FP

12345678910111213141516171819202122232425262728293031323334353637383940414243

44454647484950515253545556575859606162636465666768697071727374757677787980818283848586

87888990919293949596979899

100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

MODEI/OI/OI/OI/OI/O

GNDI/OI/OI/OI/O

VCCI/OI/OI/OI/O

GNDI/OI/OI/OI/O

GNDVCC

VSV (VCC)I/OI/O

VCCI/OI/OI/OI/O

GNDI/OI/OI/OI/O

GNDI/OI/OI/OI/OI/OI/O

I/OI/OI/OI/OI/OI/OV

CCI/OI/OI/OI/O

GN

DI/OI/OI/OI/OI/OI/OI/OI/OI/OG

ND

VC

CI/OI/OI/OI/OI/OI/OI/OI/OG

NDI/OI/OI/OI/O

VC

CI/OI/OI/OI/OI/OI/O

I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OGNDI/OI/OI/OI/OGNDI/OI/OVKS (GND)VPP (VCC)GNDVCCVSV (VCC)I/OI/OVCCI/OI/OI/OI/OGNDI/OI/OI/OI/OGNDI/OI/OI/OI/OI/OI/O

I/O SD

II/O I/O I/O I/O V

CC

I/O I/O I/O I/O GN

DI/O I/O I/O I/O I/O I/O P

RA

I/O CLK

AV

CC

GN

DI/O C

LKB

I/O PR

BI/O I/O I/O I/O G

ND

I/O I/O I/O I/O VC

CI/O I/O I/O I/O D

CLK

I/O

HBLA

NK1N

LINVN

RMS3

N

+5VDF

CI2CN

M6

PSCL

K2

HBLA

NK2N

CS1CN

+5VD

CDAT

M4

Digital Board8563-O9

CS4CN

M7

RMS3

RMS0

M2

BUSY

ACQ

M3

RMS2

M1 PCGATEN

PSLI

MIT

N

CR3CN

U7D

54AC14

98

PSCL

K1

RVPH

IA1

M9

U8

24.0MHz

1

14

7

8

NC

VS

GND

FO


CDR 9 Jul 2001 22

Power Supply Design

PSCLK-

-12VP

Q8

IRHF7130

D

G

S

Q2

2N2907A

Q52N2222A

2

13

R8

3.48K

R2275.0K

Q6

2N2907A +12VP

PSLIMIT

L4

1 mH

R133.01K

R910.0K

+

C447uF50V

R12

10.0

D5

1N5806

R1775.0K

R2414.3K

-12VA

Q7

IRHF7130

D

G

S

R35.111W

Q11IRHF9130

D

G

S

R2310.0K

R11

10.0

Q92N2222A

2

13

+12VP

R710.0K

Q122N2222A

2

13

R1

5.111W

R141.00K

+ C91.0uF50V

C247pF

D1

1N4148

Q102N2907A

+12VP

Q4

IRHF9130D

GS

T11 4

2 3

R614.3K

L2

1 mH

+ C147uF50V

Q1

2N2907A

D2

1N5806

R2118.2K

R183.01K

R155.111W

Power Supply Board8750-O9

D8

1N5806

-12VP

+12VA

R16

5.111WR19

3.01K

+ C847uF50V

Q132N2907A

+28VA

Q3

IRHF9130

D

G

S

+ C333uF75V

D4

1N5806

PSCLK+

R41.00K

D7

1N4148

Q14IRHF7130

D

G

S

R209.09K

+ C547uF50V

R21.00K

D6

1N4148

R10

20.0

L1

1 mH

R5

3.48K

D3

1N5806


CDR 9 Jul 2001 23

Image Readout Order

CCD array is illustrated showing the order in which pixels are transferred from Imager to AEP

1

2

127

128

Line

1. Each cell represents one pixel

2. Since the CCD is read from two outputs, the image is split in the middle

1 3 509 511

513 515 1021 1023

24510

1024

512

65536

1022 514516

65534 65028 6502665535655336502765025

64513 64515 65021 65023 65024 65022 64516 64514


CDR 9 Jul 2001 24

Data Transfer Timing

Line Timing

Pixel Timing

Tframe = 9.6 ms

Tline = 75 s

Tpixel = 125 ns

N > 512

FRMV

LINV

PIXCLK

DATA[0..11]

LINE 1 LINE 2 LINE 128

T frame

lineT

LINV

PIXCLK

DATA[0..11] PIXEL 1 PIXEL 2 PIXEL N-1 PIXEL N

pixelT


CDR 9 Jul 2001 25

Imager Electronics Design Status

• Breadboard fabrication and testing complete• Detailed design Completed

– FEC Electronics Design Completed

– Imager Electrical Board Design Completed

– Daylight Sensor Design Completed


CDR 9 Jul 2001 26

FEC Breadboard

A breadboard version of the FEC electronics was built to test the design of clock drivers, preamps, correlated double sample (CDS) circuitry and 12-bit A/D conversion.


CDR 9 Jul 2001 27

Breadboard Camera Measurements

• Measured system gain 29 e-/ADU

• Measured readout noise < 50 e- rms

• CCD full well ~ 120,000 e-

• Dynamic range > 2400:1

• Operating Parameters Master clock: 22.5MHz

Pixel clock: 7.5 MHz

Line clock: 340 kHz


CDR 9 Jul 2001 28

Breadboard Camera Image


CDR 9 Jul 2001 29

ETU Imager Fabrication Status

• Assembly of ETU Imager– FEC PC board fabrication status:

• All boards assembled and tested

– Imager Electrical board fabrication status:• Board etch is in process

– Daylight Sensor board fabrication status:• Board is assembled and tested

– Mechanical parts fabrication status:• Machining/fabrication is in process

– Electrical / Electronic (EE) Parts status• see next page

– Optics Parts status• see next page


CDR 9 Jul 2001 30

EE Parts and Optics Status

EE Parts and Optics Ordered Delivered Ordered DeliveredMicrocircuits

CCD ü ü ü üA/D Converter ü ü ü 7/31/01Oscillator ü ü ü üAll others ü ü ü ü

Interconnection DevicesCCD pin contacts ü ü ü üHSP030M2G (pin contacts) ü ü ü üAll others ü ü ü ü

Discrete SemiconductorsAll devices ü ü ü ü

Passive DevicesInductors/Magnetics

Tape wound core (xfmr) ü ü ü üSpiradel Delay Lines ü ü ü üAll others ü ü ü ü

Capacitors ü ü ü üResistors ü ü ü ü

Optical ComponentsWindow, fused silica P P P PFilters (set of 6), 70 mm ü 7/601 ü 7/601Lens, 61.8 mm ü ü ü üImage Intensifier ü ü ü üFiber Optic Taper, 25 mm ü ü ü üMask Application on Taper ü 6/29/01 ü 6/29/01Fiber Optic Window, 5 mm ü ü ü ü

Revised : 6/21/01 ü : Completed P : Pending information

Engineering Test Unit Flight Unit


CDR 9 Jul 2001 31

The End

ISUAL Sprite Imager Electronic Design Stewart Harris.

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Transcript of ISUAL Sprite Imager Electronic Design Stewart Harris.