ISO-NET Hardware Based Job Queue Management for

Many Core Architecture

OBJECTIVE:

In this Project, I present Iso-Net, hardware- based conflict-free dynamic load distribution and balancing engine. For balanced distribution of workload based Job Queue Management for Many-Core Architectures.

INTRODUCTIONCOMPLEX and Monolithic Superscalar Microprocessor

designs have recently begun to give way to arrays of leaner and simpler processing cores working in unison to exploit thread-level parallelism. This paradigm shift has marked the genesis of the multicore era, the embodiment of which is the chip multiprocessor (CMP) .

The most popular programming model for multicore systems is multithreading, whereby a programmer can parallelize an application by spawning a separate thread for each parallel task.

Due to the small size of the task overhead of spawning the switching between Jobs and Thread become unwarranted whereas Thread comprises a set of instructions and states of execution of a program and Job is composed of set of data to be processed by Thread .

EXISTING SYSTEM:

• Fine-grained parallelism, a programmer can parallelize an application by spawning a separate thread for each parallel task.

• Job queue technique, it may be centralized, or distributed, and it may be implemented in hardware or software.

SOFTWARE TECHNIQUE: • All operations are orchestrated in software, with minimal reliance on

hardware support. Atomicity of operation is highly depends on software.

HARDWARE TECHNIQUE:• It aims to tackle this problem by essentially reducing the probability

of conflicts also scalability certainly improves.

BLOCK DIAGRAM:

BLOCK DESCRIPTION:

They are three job queues are assigned each queue is having specific operation that queue is connected with the balancer, that the balancer is used to give a instruction for processor to identify which queue is required to access first according to that instruction the processor will handle the queue than the final output is received from balancer.

DISADVANTAGES:

The thread creation comes at a cost and execution time of each thread is relatively short. Due to the small size of these tasks, the overhead of spawning new threads and switching between them become unwarranted.

The hardware’s role is usually limited, so the fundamental impediment to scalability faced by these techniques is the occurrence of conflicts.

Conflicts are still not completely eliminated and they begin to dominate performance when the number of processing elements increases to many core levels.

The execution driven simulators is that they become prohibitively slow as the number of simulated processing cores increases beyond one hundred. Therefore, it is practically impossible to simulate such systems.

PROPOSED SYSTEM:

• The IsoNet architecture is fully implemented in a hardware description language (HDL). It was designed to complete any job transfer within a single IsoNet clock cycle.

• It is then passed through a detailed application specific integrated circuit design flow using commercial standard-cell libraries in 45-nm VLSI technology.

• Load distribution and balancing modules, which can swiftly transfer jobs between any two cores, based on prevailing load conditions.

Overview of the enhanced IsoNet design that supports multiple job transfers per IsoNet cycle.

Description

To implement the local balancing approach , a local balancer must be added to the ISONET logic as shown.

The local balancer begins the job count from all the nearest MUX .

A comparator compares the job count and selects the smallest job count.

If the smallest job count is smaller than that of its own job count it accepts the requestor job count.

The highest job count is given neighbour MUX.

The requestor issues the request to the neighbour MUX which has the highest job count else the current node is selected as source or destination by the selected tree by the highest priority If the neighbor replies with a grant, the requester pops a job from the dual-clock stack and transfers it to the neighbor.

The Arbiter in the local balancer decides as to which request it should serve.

ADVANTAGES:

• IsoNet clock cycle is much longer than a CPU clock cycle.

• We use a trace-driven cycle-accurate simulator to compare Carbon and IsoNet for core counts.

• By exploiting a micro-network of load-balancing modules, the proposed mechanism is shown to effectively reinforce concurrent computation in many-core environments.

• The realization of IsoNet, a lightweight on-chip micro-network of load distribution and balancing modules.

• The single cycle implementation can be achieved with minimal hardware cost.

APPLICATIONS:

• It is used for processor based applications such as medical field.

• Technologies lead vehicles such as electric cars.

• Back-up power supplies for alarm and smaller computer systems.

• Electric wheelchairs.

• Marine applications.

• Mining-Calculate various skeleton parameters inc ash and calorific value to determine the grades of coal

Tools:

Xilinx ISE 9.1

References• Junghee Lee, Student Member, IEEE, Chrysostomos

Nicopoulos, Member, IEEE,Hyung Gyu Lee, Member, IEEE, Shreepad Panth, Student Member, IEEE,Sung Kyu Lim, Senior Member, IEEE, and Jongman Kim, Member, IEEE“IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013

• S. Kumar, C. Hughes, and A. Nguyen, “Carbon:Architectural support for fine-grained parallelism on chip multiprocessors,” in Proc. 34th Annu. Int. Symp. Comput. Arch., 2007, pp. 162–173.

• L. Soares, C. Menier, B. Raffin, and J. L. Roch, “Work stealing for timeconstrained octree exploration: Application to real-time 3D modeling,”in Proc. Eurograph. Symp. Parallel Graph. Visualizat., 2007, pp. 1–9.

References

• D. Sanchez, R. M. Yoo, and C. Kozyrakis, “Flexible architectural support for fine-grain scheduling,” in Proc. Int. Conf. Arch. Support Program. Lang. Operat. Syst., 2010, pp. 311–322.

• P. Dubey, “Recognition, mining and synthesis moves computers to the era of tera,” Technology@Intel Magazine, Feb. 2005.