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DATASHEET

40V Precision Instrumentation Amplifier withDifferential ADC DriverISL28617The ISL28617 is a high performance, differential input, differentialoutput instrumentation amplifier designed for precisionanalog-to-digital applications. It can operate over a supply range of 8V(4V) to 40V (20V) and features a differential input voltage rangeup to 34V. The output stage has rail-to-rail output drive capabilityoptimized for differential ADC driver applications. Its versatility andsmall package makes it suitable for a variety of general purposeapplications. Additional features not found in other instrumentationamplifiers enable high levels of DC precision and excellent ACperformance.

The gain of the ISL28617 can be programmed from 0.1 to10,000 via two external resistors, R IN and R FB. The gain accuracyis determined by the matching of R IN and R FB. The gain resistors

have Kelvin sensing, which removes gain error due to PC traceresistance. The input and output stages have individual powersupply pins, which enable input signals riding on a high commonmode voltage to be level shifted to a low voltage device, such asan A/D converter. The rail-to-rail output stage can be poweredfrom the same supplies as the ADC, which preserves the ADCmaximum input dynamic range and eliminates ADC inputoverdrive.

Related Literature AN1753 , ISL28617VYXXEV1Z Users Guide Evaluation board

with bulk metal foil resistors for high precision. See applicationnote for gain options and ordering information.

AN1748 , ISL28617SMXXEV1Z Users Guide Evaluation boardwith standard resistors for low cost, medium precision. Seeapplication note for gain options and ordering information.

Features Rail-to-rail differential output ADC driver

High voltage interface to low voltage circuits

Wide operating voltage range . . . . . . . . . . . . . . . 4V to 20V

Low input offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V

Excellent CMRR and PSRR . . . . . . . . . . . . . . . . . . . . . . . 120dB

Closed loop -3dB BW . . .0.3MHz (A V = 1k) to 5MHz (A V = 0.1)

Operating temperature range. . . . . . . . . . . . -40C to +125C

Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ld TSSOP

Applications Precision test and measurement

High voltage industrial process control

Signal conditioning amplifier for remote powered sensors

Weigh scales

ECG and biomedical sense amplifiers

0

20

40

60

80

100

120

140

C M R R ( d B )

FREQUENCY(Hz)1 10 100 1k 10k 100k 1M

A V = 0.1

A V = 100

A V = 1000

A V = 10

A V = 1

FIGURE 1. CMRR R F = 121k

R IN

+R IN

-R IN

IN+

+R IN

-R IN

IN-

+R FB

-R FB

+R FB

-R FB

VCC

VCO

GNDVEE

VEORFB

+VOUT

-VOUT

VCMO VREF

+5V

+5V

TO+20V

-5VTO

-20V

ISL28617

A-DR

CBRIDGE

VDD

GNDR

-VFB

+VFB CONVERTER

EXCITATION

FULL BRIDGE STRAIN GAUGE AMPLIFIER AND DIFFERENTIAL ADC DRIVER

+IN

-IN ISL26132

VREFISL21090

AV = R FB /R IN RANGE FROM 0.1 TO 10,000

FIGURE 2. BASIC APPLICATION CIRCUIT

SENSE

SENSE

SENSE

SENSE

November 17, 2014

FN6562.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013, 2014. All Rights ReservedIntersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.All other trademarks mentioned are the property of their respective owners.
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ISL28617(24 LD TSSOP)

TOP VIEW

1

2

3

4

24

23

22

21

5

6

7

20

19

18

8 17

NC

DNC

+R FB

IN+

IN-

DNC

+R IN

+R FB SENSE +R IN SENSE

-RFB SENSE

-R FB

-R IN SENSE

-R IN

GND V CMO

9

10

11

16

15

14

12 13

VCC VEE

VCO

+VFB

VEO

-VFB

+VOUT -VOUT

DNC

Pin DescriptionsPIN

NAME PIN NUMBERS DESCRIPTION

NC 1 No Internal Connection

DNC 2, 3, 22 For internal use; Do Not Connect.

+R FB 4 Feedback Resistor, R FB+ pin

+R FB SENSE 5 +R FB, Positive Sense pin connects to theresistor R FB+ terminal to form the R FB+Kelvin connection.

-RFB SENSE 6 -R FB, Negative Sense pin connects to theresistor R FB - terminal to form the R FB -Kelvin connection.

-RFB 7 Feedback Resistor, Negative Terminal.

GND 8 Ground Pin is capacitively coupled to theinternal ESD circuit and should beconnected to power supply common orsignal GND.

VCC 9 Positive Supply for Input Stage andFeedback Amp.

VCO 10 Positive Supply for Output Stage.+VFB 11 Positive Output Feedback

+VOUT 12 Positive Output

-VOUT 13 Negative Output

-VFB 14 Negative Output Feedback

VEO 15 Negative Supply for Output Stage.

VEE 16 Negative Supply fo r Input Stage andFeedback Amp.

VCMO 17 Output Common Mode Reference input.

-RIN 18 Input Resistor, Negative Terminal.

-RIN SENSE 19 -R IN, Negative Sense pin connects to theresistor R IN - terminal to form the R IN -

Kelvin connection.+R IN SENSE 20 +R IN, Positive Sense pin connects to the

resistor R IN+ terminal to form the R IN+Kelvin connection.

+R IN 21 Input Resis tor, Posit ive Terminal.

IN- 23 Negative Input

IN+ 24 Positive Input

Ordering InformationPART NUMBER(Notes 1 , 2 , 3 )

PARTMARKING

TEMP RANGE(C)

PACKAGE(Pb-Free)

PKG.DWG.

ISL28617FVZ 28617 FVZ -40 to +125 24 Ld TSSOP M24.173

NOTES:

1. Add -T* suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% mattetin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28617 . For more information on MSL please see tech brief TB363 .
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Absolute Maximum Ratings Thermal InformationMaximum Supply Voltage (V CC to V EE or GND) . . . . . . . . . . . . . . . . . . . . 42VMaximum Supply Voltage (V CO to V EO or GND) . . . . . . . . . . . . . . . . . . . . 42VMaximum Voltage (V CO to V CC) . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.5V, -40VMaximum Voltage (V EO to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V, +40VMaximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mAMax/Min Input Current for Input Voltage >V CC or

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VOH Output Voltage High, V + to VOUT VCC = +15V, V EE = -15V,VCO = +4V, V EO = -4VRIN = R F = 121k IOUT = 1.5mA

150 200 mV

200 mV

ISC Output Short Circuit Current R L = 0 to GND 45 mA

-20 20 mA

IERR Total Internal Offset Error Current ( Note 8 ) -17 5 17 nA

-90 90 nA

EG Gain Error ( Notes 9 , 10 ) VOUT = -10V to +10V, R F = 121k

0.003 %G = 1

G = 100 0.004 %

VOUT = -2.5V to +2.5V, R F = 30.1k

0.0005 %G = 1

OUTPUT COMMON MODE SPECIFICATIONS

VCMOCMIR Output Common Mode Control Input VoltageRange

VEE +3V V CC -3V V

VOSCM Output Common Mode Offset Voltage fromVCMO Input

-1.3 0.5 1.3 mV

-4.75 4.75 mV

IBVCMO Input Bias Current at V CMO Input -0.6 0.2 0.6 A

-1.75 1.75 A

POWER SUPPLY SPECIFICATIONS

ICC Supply Current, V CC to V EE RL = OPEN 2.05 2.2 mA

2.85 mA

ICO Supply Current, V CO to V EO RL = OPEN 2.25 2.6 mA

2.85 mA

VCC to VEE Input Supply Voltage Dual Supply 4 20 V

Single Supply 8 40 V

VCO to VEO Output Supply Voltage Dual Supply 1.5 20 V

Single Supply 3 40 V

PSRR V CC to V EE Power Supply Rejection Ratio V CC to V EE = 4V to 20V123 130 dB

G = 100118 dB

PSRR V CO to V EO Power Supply Rejection Ratio V CO to V EO = 4V to 20V 110 120 dB

110 dB

AC SPECIFICATIONS

e N Input Noise Voltage Density f = 1kHz 8.6 nV/ Hz

e Nrms Input rms Noise Voltage f = 0.1 to 10Hz 85 nVrms

iN Input Noise Current Density f = 1kHz 150 fA/ Hz

iNIERR Total Internal Noise Current Density f = 1kHz 2.6 pA/ Hz

iNIERR rms 0.1 to 10Hz Total Internal rms Noise Current f = 0.1 to 10Hz 4 pArms

Electrical Specifications VCC = V CO = 15V, V EE = V EO = -15V, V CM = 0V, R L = 10k RFB = R IN = 30.1k TA = +25C, unless otherwisespecified. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued)

PARAMETER DESCRIPTION CONDITIONSMIN

(Note 6 ) TYPMAX

(Note 6 ) UNIT
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Typical Performance CurvesVCC = VCO = 15V, V EE = VEO = -15V, V CM = 0V, R L = Open, unless otherwise specified.

FIGURE 3. I CC vs SUPPLY VOLTAGE (V CC - V EE ) FIGURE 4. I CO vs SUPPLY VOLTAGE ( V CO - V EO)

FIGURE 5. I ERR vs INPUT COMMON MODE VOLTAGE FIGURE 6. I ERR vs SUPPLY VOLTAGE (V CC - V EE )

FIGURE 7. V OSFB vs INPUT COMMON MODE VOLTAGE FIGURE 8. V OSFB vs SUPPLY VOLTAGE (V CC - V EE )

1

2

3

0 10 20 30 40 50

SUPPLY VOLTAGE (V CC - V EE )

S U P P L Y C U R R

E N T ( m A )

1

2

3

0 10 20 30 40 50

SUPPLY VOLTAGE (V CO - VEO )

S U P P L Y C U R R E N T ( m A )

-20

-15

-10

-5

0

5

10

15

20

-15 -10 -5 0 5 10 15

VCM (V)

I e r r

( n A )

-20

-10

0

10

20

0 5 10 15 20 25 30 35 40 45 50

VSUP (VCC - V EE )

I e r r

( n A )

-1000

-800-600

-400

-200

0

200

400

600

800

1000

-15 -10 -5 0 5 10 15VCM (V)

V O S F B

( m V )

-1000

-800-600

-400

-200

0

200

400

600

800

1000

0 5 10 15 20 25 30 35 40 45 50VSUP (VCC - V EE )

V O S F B

( m V )

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FIGURE 9. I OS vs SUPPLY VOLTAGE (V CC - V EE ) FIGURE 10. I OS vs SUPPLY VOLTAGE (V CC - V EE )

FIGURE 11. I B vs INPUT COMMON MODE VOLTAGE FIGURE 12. I B vs SUPPLY VOLTAGE (V CC - V EE)

FIGURE 13. V OS IN vs I NPUT COMMON MODE VOLTAGE FIGURE 14. V OS IN vs SUPPLY VOLTAGE (V CC - V EE )

Typical Performance CurvesVCC = VCO = 15V, V EE = VEO = -15V, V CM = 0V, R L = Open, unless otherwise specified. (Continued)

-1000

-800

-600

-400

-200

0

200

400

600

800

1000

0 5 10 15 20 25 30 35 40 45 50VSUP (VCC - VEE )

I O S

( p A

)

-1000

-800

-600

-400

-200

0

200

400

600

800

1000

0 5 10 15 20 25 30 35 40 45 50VSUP (VCC - VEE )

I O S

( p A )

-1000

-800

-600

-400

-200

0

200

400

600

800

1000

-15 -10 -5 0 5 10 15

VCM (V)

-IB

+IB

I B ( p A )

-1000

-800

-600

-400

-200

0

200

400

600

800

1000

0 5 10 15 20 25 30 35 40 45 50

VSUP (VCC - VEE )

I B ( p A )

-IB

+IB

-100-80

-60

-40

-20

0

20

40

60

80

100

-15 -10 -5 0 5 10 15

VCM (V)

V O S

I N ( m V )

-100

-80

-60

-40

-20

0

20

40

60

80

100

0 5 10 15 20 25 30 35 40 45 50

VSUP (VCC - VEE )

V O S

I N ( m V )

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FIGURE 15. IB VCMO vs V CMO INPUT VOLTAGE RANGE FIGURE 16. COMMON MODE RANGE vs OUTPUT VOLTAGE

FIGURE 17. COMMON MODE RANGE vs OUTPUT VOLTAGE FIGURE 18. CLOSED LOOP GAIN (R FB = 30.1k) vs FREQUENCY)

FIGURE 19. CLOSED LOOP GAIN (R FB = 121k) vs FREQUENCY FIGURE 20. POSITIVE PSRR V EE AND V CC (R F = 30.1k)


-5

-4

-3

-2

-1

0

1

2

3

4

5

-15 -10 -5 0 5 10 15VCMO (V)

I B V C M O

( m

A )

-15

-10

-5

0

5

10

15

-6 -4 -2 0 2 4 6VOUT+ TO VOUT- (V)

I N P U T V C

M (

V )

VCC = +10V; V EE = -10V

RFB = 120k; R IN = 120VCO = +5V; V EO = 0V

VCMO = 2.5V

-15

-10

-5

0

5

10

15

-3 -2 -1 0 1 2 3

VOUT+ TO VOUT- (V)

I N P U T V

C M (

V )

4-4

VCC = +10V; V EE = -10V

RFB = 30k; R IN = 30.1VCO = +3V; V EO = 0V

VCMO = 1.5V

-40

-20

0

20

40

60

80

10 100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

AV = 100

AV = 10

R IN = 301 R FB = 30.1k

AV = 1R IN = 30.1k, R FB = 30.1k G

A I N ( d B )

AV = 1000R IN = 30.1, R FB = 30.1k

R IN = 3.01k, R FB = 30.1k

R IN = 301k, R FB = 30.1k

AV = 0.1

-40

-20

0

20

40

60

80

FREQUENCY (Hz)

10 100 1k 10k 100k 1M 10M 100M

AV = 100

AV = 1000

AV = 10

RFB = 121k

AV = 1 G A I N ( d B )

AV = 0.1

R IN = 12.1k, R FB = 121k

R IN = 121k, R FB = 121k

R IN = 1.21k

R IN = 121, R FB = 121k

R IN = 1.21M, R FB = 121k0

20

40

60

80

100

120

140

160

1 10 100 1k 10k 100k 1M

P O S I T I V E P S R R ( d B )

FREQUENCY (Hz)

AV = 0.1

AV = 100

AV = 1000

AV = 10

AV = 1

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FIGURE 21. NEGATIVE PSRR V EE AND V CC (R F = 30.1k) FIGURE 22. POSITIVE PSRR V EE AND V CC (R F = 121k)

FIGURE 23. NEGATIVE PSRR V EE AND V CC (R F = 121k) FIGURE 24. POSITIVE PSRR V E0 AND V C0 (R F = 30.1k)

FIGURE 25. NEGATIVE PSRR V EO AND V CO (R F = 30.1k) FIGURE 26. POSITIVE PSRR V EO AND V CO (R F = 121k)


0

20

40

60

80

100

120

140

160

N E G A T I V E P S R R ( d B )

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 0.1

AV = 100

AV = 1000

AV = 10

AV = 1

0

20

40

60

80

100

120

140

160


FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 0.1

AV = 100

AV = 1000

AV = 10

AV = 1

0

20

40

60

80

100

120

140

160


FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 0.1

AV = 100

AV = 1000

AV = 10

AV = 1

0

20

40

60

80

100

120

140

160180

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M


AV = 0.1

AV = 100

AV = 1000

AV = 10AV = 1

0

2040

60

80

100

120

140

160

180


FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 0.1

AV = 100

AV = 1000

AV = 10AV = 1

0

20

40

60

80

100

120

140

160

180

200


FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 0.1

AV

= 100AV = 1000

AV = 10AV = 1
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FIGURE 27. NEGATIVE PSRR V E0 AND V CO (R F = 121k) FIGURE 28. CMRR RF = 30.1k

FIGURE 29. CMRR R F = 121k FIGURE 30. INPUT VOLTAGE AND CURRENT NOISE


0

20

40

60

80

100

120

140

160


FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 0.1

AV = 100

AV = 1000

AV = 10

AV = 1

0

20

40

60

80

100

120

140

C M R R R

F B = 3

0 . 1

k ( d B )

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 0.1

AV = 100

AV = 1000

AV = 10

AV = 1

0

20

40

60

80

100

120

140

C M R R R

F B =

1 2 1 k ( d B )

FREQUENCY (Hz)

1 10 100 1k 10k 100k 1M

AV = 0.1

AV = 100

AV = 1000

AV = 10

AV = 1

1

1

10

1000

0.1 1 10 100 1k 10k 100kFREQUENCY (Hz)

100

0.1

0.01

I N P U T N O I S E V O L T A G E ( n V / H

z ) I NP

UT N

OI S E

C URRE NT

( pA

/ Hz

)

e N

iN

10

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FIGURE 31. ISL28617 FUNCTIONAL BLOCK DIAGRAM

IN+

R IN

IN-

RFB

100A

+-

VCMO

VFB-

-VOUT

+-

+-

+-

VCC

VEE VEO

VCO

VFB+

+VOUT

100A

INPUT FEEDBACK OUTPUT

STAGESTAGESTAGE

+R INSENSE -R INSENSE

A1 A2 A3 A4

-RFB SENSE +R FB SENSE

Q1 Q2 Q3 Q4

I1 I2 I3 I4

0.1F

0.1F0.1F

0.1F

GND

GAIN RESISTORS AND

KELVIN CONNECTIONS

500

500

A5

+R IN -R IN +R FB -RFB

IS1 IS2 IS3 IS4

I1, I3I2, I4

+-A6

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Applications InformationGeneral Description section: contains the ISL28617 functionaland performance objectives and description of operation.

Designing with the ISL28617 section: contains the applicationcircuit design Equations and guidelines for achieving the desiredDC and AC performance levels.

Estimating Amplifier DC and Noise Performance section:provides Equations for predicting DC offset voltage and noise ofthe finished design.

General DescriptionThe ISL28617 Instrumentation Amplifier was developed toaccomplish the following:

Provide a fully differential, rail-to-rail output for optimallydriving ADCs.

Limit the output swing to prevent output overdrive.

Allow any gain, including attenuation.

Maximize gain accuracy by removing on-chip componenttolerances and external PC board parasitic resistance.

Enable user control of amplifier precision level with choice ofexternal resistor tolerance.

Maintain CMRR>100dB and remove CMRR sensitivity to gainresistor tolerance.

Provide a level shift interface from bipolar analog input signalsources to unipolar, and bipolar ADC output terminations.

Functional DescriptionFigure 31 shows the functional block diagram for the ISL28617.

Input GM

AmplifierThe input stage consists of high performance, wide bandamplifiers A1, A2, G M drive transistors Q1, Q2, and input gainresistor R IN. Current drive for Q1 and Q2 emitters are provided bymatched pair of 100A current sinks. A unity gain buffer fromeach input (IN+, IN-) to the terminals of the input resistor, R IN, isformed by the connection of the Kelvin resistor sense pins anddrive pins to the terminals of the input resistor, as shown inFigure 31 . In this configuration, the voltage across the inputresistor R IN is equal to the input differential voltage across IN+and IN-.

The input G M stage operates by creating a current difference inthe collector currents Q1 and Q2 in response to the voltagedifference between the IN+ and IN- pins. When the input voltageapplied to the IN+ and IN- pins is zero, the voltage across theterminals of the gain resistor R IN, is also zero. Since there is nocurrent flow through the gain resistor, the transistors Q1 and Q2collector currents I 1 and I 2 are equal.

A change in the input differential voltage causes an equivalentvoltage drop across the input gain resistor R IN, and the resultingcurrent flow through R IN, causes an imbalance in Q1 and Q2

collector currents I 1 , I2 , given by Equations 1 and 2 :

Feedback G M AmplifierThe feedback amplifiers A3 and A4 form a differential

transconductance amplifier identical to the input stage. Theinput terminals (V FB+ , VFB-) connect to the ISL28617 differentialoutput terminals (+V OUT, -VOUT), so that the output voltage alsoappears across the feedback gain resistor R FB.

Operation is the same as the input G M stage and the differentialcurrents I 3 and I 4 are given by Equations 3 and 4 :

Error Amplifier A5, Output Amplifier A6

(Figure 31 )Amplifiers A5 and A6 act together to form a high gain,differential I/O trans-impedance amplifier. Differential currentamplifier A5 sums the differential currents (I 1 +I3 and I 2 +I4 ) fromthe input and feedback G M amplifiers. From that summation, adifferential error voltage is sent to A6, which generates therail-to-rail differential output drive to the +V OUT and -V OUT pins.

The external connection of the output pins to the feedbackamplifier closes a servo loop where a change in the differentialinput voltage is converted into differential current imbalances atI1 and I 2 (Equations 1 and 2 ) at the summing node inputs to A5.Current I 1 sums with current I 3 from the feedback stage, and I 2 sums with I 4 . A5 senses the difference between current pairs I 1 ,I3

and I2

, I4

. A difference voltage is generated, amplified and fedback to the feedback amplifier, which creates correction currentsat I 3 and I 4 to match the currents at I 1 and I2 (Equations 3 and 4 ).

Therefore, at equilibrium:

Combining Equations 1 and 3 , (and their complements I 2 and I 4 ),and solving for V OUT as a function of V IN, R IN and R FB, yieldsEquation 6 :

Equation 6 can be rearranged to form the gain, see Equation 7 :

which is general form of the gain Equation for the ISL28617.

(EQ. 1)I1= 100A + (V IN+ - V IN- )/R IN

(EQ. 2)I2= 100A - (V IN+ - V IN- )/R IN

(EQ. 3)I3 = 100A - {(+V OUT) - (-V OUT)}/R FB

(EQ. 4)I4 =100A +{(+V OUT) - (-V OUT)}/R FB

(EQ. 5)I1 = I 3 and I 2 = I 4

(EQ. 6)VOUT = V IN*R FB /R IN ;Where V OUT = (+V OUT) - (-V OUT) and VIN = IN+ - IN-

(EQ. 7)Gain = V OUT /V IN = R FB /R IN

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Designing with the ISL28617To complete a working design, the following procedure isrecommended and explained in this section:

1. Define the output voltage swing

2. Set the feedback resistor value, R FB

3. Set the input gain resistor value, RIN

3. Set the V CO, VEO power supply voltages

4. Set the V CC and V EE supply voltages

The gain of the instrumentation amplifier is set by the resistorratio R FB /R IN (Equation 7 ), and the maximum output swing is setby the absolute value of the feedback resistor R FB (Equation 8 ).VCO and V EO supply power to the rail-to-rail output stage anddefine the maximum output voltage swing at the V OUT differential output pins. Power supply pins V CC and V EE power thefeedback amplifiers, which require an additional 3V beyond theVCO and V EO voltages to maintain linear operation of thefeedback G M stage.

Setting the Feedback Gain Resistor R FB(Figures 31 , 32 )Resistor R FB defines the maximum differential voltage at outputterminals +V OUT to -VOUT. External resistor R FB and the differential100A current sources define the maximum dynamic range ofthe feedback stage, which defines the maximum differentialoutput swing of the output stage. Overload circuitry allows>100A to flow through R FB to maintain feedback, but linearity isdegraded. Therefore, it is a good practice to keep the maximumlinear dynamic range to within 80% of the maximum I*R acrossthe resistor.

In cases where large pulse overshoot is expected, the maximumcurrent in Equation 8 could be reduced to 50% for additionalmargin (see AC Performance Considerations on page 16 ) Thepenalty for increasing the feedback resistor value is higher DCoffset voltage and noise.

Output voltages that exceed the maximum dynamic range of thefeedback amplifier can degrade phase margin and causeinstability. The plot in Figure 32 shows the maximum differentialoutput voltage swing vs resistor value for R FB and R IN using the80% and 50% current source levels.

Setting the Input Gain Resistor R IN (Figures 31 , 32 ) The input gain resistor R IN is scaled to the feedback resistoraccording to the gain Equation 9 :

The input G M stage uses the same differential current sourcearrangement as the feedback stage. Therefore, the amount ofoverdrive margin (50%, 80%) included in the calculation for R FB is also included in the calculation for R IN.

Input Stage Overdrive Considerations(Figure 33 )There are a few cases where the input stage can be overdriven,which must be considered in the application. An input signal thatexceeds the maximum dynamic range of the gain resistor R IN,calculated previously, can cause the ESD diodes to conduct.When this occurs, a low impedance path from the inputs to theinput gain resistor R IN will result in signal distortion.

High speed input signals that remain within the maximumdynamic range of the input stage can cause distortion if the inputslew rate exceeds the input stage slew rate (~4V/s). When theinput slews at a faster rate than the G M stage can follow, thevoltage difference appears across the input ESD diodes fromeach input and resistor R IN. When the voltage difference is largeenough to cause the diodes to conduct, the input terminals areshunted to R IN through the 500 input protection resistors,causing distortion during the rise and fall times of the transientpulse. The distortion will last until the resistor voltage catches upto the input voltage.

Setting the Power Supply VoltagesThe ISL28617 power supplies are partitioned so that the input stageand feedback stages are powered from a separate pair of supplypins (V CC, VEE) than the differential output stage (V CO, VEO). Thispartitioning provides the user with the ability to adapt the ISL28617to a wide variety of input signal power sources that would not bepossible if the supplies were strapped together internally (V CC = VCO and V EE = VEO). However, powering the input and output suppliesfrom unequal supplies has restrictions that are described in the nextsection.

(EQ. 8)VOUTDIFF = 80A * R FB

FIGURE 32. R FB , R IN vs. DYNAMIC RANGE

35

30

25

20

15

10

5

00 50 100 150 200 250 300 350 400

D Y N A M I C V O L T A G E R A N

G E ( V )

RFB , R IN VALUE (k )

VOUT (V) AT 80%

VOUT (V) AT 50%

(EQ. 9)RIN = R FB /Gain

IN+

R IN

IN-

100A100A

+-

+-

VEE

500

VCC

500

ESDPROTECTIONESDPROTECTION

FIGURE 33. INPUT STAGE ESD PROTECTION DIODES

A1 A2Q1 Q2

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Powering the Input and Feedback Stages(VCC, VEE)The input pins IN+, IN- cannot swing rail-to-rail, but have amaximum input voltage range given by Equation 10 :

This requires the sum of the common mode input voltage andthe differential input voltage to remain within 3V of either the V CC or VEE rail, otherwise distortion will result.

The feedback pins V FB+ and V FB - have the same input commonmode voltage constraint as the input pins IN+ and IN-. Themaximum input voltage range of the feedback pins is given byEquation 11 :

To maintain stability, it is critical to respect the 3V requirementin Equation 11 .

Powering the Rail-to-rail Output Stage(VCO , VEO)The output stage (A6) is of rail-to-rail design, and is powered by theVCO and V EO pins. The differential output pins +V OUT and -V OUT connect to the V FB+ and V FB - pins to close the output feedbackloop. The feedback stage is powered from V CC and V EE pins. TheVFB+ and V FB - have a common mode input range 3V below the V CC rail and 3V above the and V EE rail. If the output voltage exceeds thefeedback common mode input voltage, loop instability will result.Therefore, the voltages at the V OUT pins should always be 3Vaway from either rail, as shown in Equation 12 :

Rail-to-rail Differential ADC DriverThe differential output stage of ISL28617 is designed to drive thedifferential input stage of an ADC. In this configuration, the V COand V EO power supply pins connect directly to the ADC powersupply pins. This output swing arrangement is ideal for drivingrail-to-rail ADC drive without the possibility of over driving theADC input.

The output stage is capable of rail-to-rail operation when V CO andVEO are powered from a single supply or from split supplies. Ithas a single supply voltage range (V CO) from 3V to 15V (with V EO at GND), and a 1.5V to 15V split supply voltage range. Underall power supply conditions, V CC must be greater than V CO by 3V,

and V EE must be less than V EO by 3V to maintain the rail-to-railoutput drive capability.

The V CMO pin is an input to a very low bias current terminal, andsets the output common mode reference voltage when driving adifferential input ADC, such that the output would have a inputsignal span centered around an external DC reference voltageapplied to the V CMO pin.

Power Supply Voltages by ApplicationThe ISL28617 can be adapted to a wide variety ofinstrumentation amplifier applications where the signal source ispowered from supply voltages that are different from the supplyvoltages powering downstream circuits. The following examplesare included as a guide to the proper connection and voltagesapplied to the supply pins V CC, VEE, VCO and V EO.

There are a common set of requirements across all powerapplications:

1. A common ground connection from the input supplies, (V CC,VEE) to the output supplies (V CO, VEO) is required for allpowering options.

2. The signal input pins IN+ and IN- cannot float, and must havea DC return path to ground.

3. The input and output supplies cannot both be operated insingle supply mode due to the 3V feedback amplifiercommon mode headroom requirement in Equation 11 .

The following are typical power examples:

EXAMPLE 1: BIPOLAR INPUT TO SINGLE SUPPLYOUTPUTThe ISL28617 is configured as a 5V ADC driver in a high-gainsensor bridge amplifier powered from a 10V excitation source.In this application, the ISL28617 must extract the low-levelbipolar sensor signal and shift the level to the 0V to +5Vdifferential rail-to-rail signal needed by the ADC. The followingpowering option is recommended:

V CC = +10V, V EE = -10V

V CO = +5V, V EO = GND

V CMO = +2.5V

V CC and V EE power supply common connects to GND

EXAMPLE 2: HIGH VOLTAGE BIPOLAR I/O BUFFER

The ISL28617 is configured as a high impedance bufferinstrumentation amplifier in a 15V industrial sensor application. Inthis application, the ISL28617 must extract and amplify the highimpedance sensor signal and send it downstream to a differentialADC operating from 15V supplies. The following powering optionsare recommended:

1. Input and output supplies are strapped to the same supplies andrail-to-rail input to the ADC is not required.

- VCC = VCO = +15V

- VEE = VEO = -15V

- VCMO = GND

- VCC, VEE power supply common connects to GNDand V OUT = 12V

2. 15V Rail-to-rail output is required, then:

- VCC = +18V, V EE = -18V

- VCO = +15V, V EO= -15V

- VCMO = GND

- VCC and V EE power supply common connects to GND

The V CO and V EO power supply pins connect to the ADC (15V) powersupply pins. Rail-to-rail output swing requires that V CC = VCO +3V andVEE = VEO -3V, or 18V.

(EQ. 10)VEE+ 3V < (V CMIR IN + V IN) < V CC - 3V; where V IN = maximum differential voltage IN+ to IN-

(EQ. 11)VEE+ 3V < V CMIR FB < V CC - 3Vwhere V CMIR FB = (+V OUT - -V OUT) +V CMO

(EQ. 12)VEE+ 3V < V OUT < V CC - 3V; where V OUT = |+V OUT| or |-VOUT|

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EXAMPLE 3: GAINS LESS THAN 1

The ISL28617 is configured to a gain of 0.2V/V driving arail-to-rail 3V ADC. In this application, the maximum inputdynamic range is 15V.

- VCC = +18V, V EE = -18V

- VCO = +3V, V EO = GND

- VCMO = +1.5V

- VCC, VEE power supply common connects to GND

In this attenuator configuration, the input signal range is 15V,which requires an additional 3V of input overhead from theinput supplies. Thus, V CC and V EE = 18V.

AC Performance ConsiderationsThe ISL28617 closed loop frequency response i s formed by thefeedback G M amplifier and gain resistor R FB and has thecharacteristics of a current feedback amplifier. Therefore, the

-3dB gain does not significantly decrease at high gains as is thecase with the constant gain-bandwidth response of the classicvoltage feedback amplifier.

There are four behaviors of current feedback amplifiers thatmust be considered:

Frequency response increases with decreasing values of R FB.A comparison of the G = 100, -3db response ( Figures 18 , 19 )RFB at 30.1k vs 121k shows almost a 4X decrease from2MHz to 0.5MHz.

Gain peaking tends to increase with decreasing values of R FB.

Wide band applications at gains less than 1 ( Figures 18 , 19 )can have high gain peaking resulting in high levels ofovershoot with pulsed input signals.

Parasitic capacitance at the feedback resistor terminals(+R FB, -RFB) and the Kelvin sense terminals (+R FBSENSE,

-RFB

SENSE) will result in increasing levels of peaking andtransient response overshoot.

To minimize peaking external PC parasitic capacitance should beminimized as much as possible. The ISL28617 is designed to bestable with PC board parasitic capacitance up to 20pF andfeedback resistor values down to 30.1k . At gains less than 1,the maximum parasitic capacitance may have to be l imitedfurther to avoid additional compensation.

Uncorrected gain peaking and high overshoot in the feedbackstage can cause loss of feedback loop stability if the transientcauses the feedback voltage to exceed the common mode inputrange of the feedback amplifier or the maximum linear range ofthe feedback resistor R FB. Corrective actions include increasingthe size of the feedback resistor (see Figure 32 ) and rescalingthe input gain resistor R IN, or adding input frequencycompensation described in the next section.

The penalty of increasing the R FB (and R IN rescaling) is increasednoise, so this is generally not the corrective action of choice.

AC Compensation TechniquesThe input compensation with a low pass filter ( Figure 34 ) can bean effective way to block high frequency signals from thedifferential amplifier inputs. It does not change the gain peakingbehavior of the feedback loop, but it does block signals from

creating overdrive instability. This method is useful af ter othercorrective measures have been implemented, and when there islittle control over the input signal frequency content.

Input Common Mode RejectionConsiderationsThe ISL28617 is capable of a very high level (120dB) of CMRRperformance from DC to as high as 1kHz. ( Figure 1 ; CMRR vsFrequency). This high level of performance over frequency ismade possible by the high common mode input impedance(80G but requires careful attention to the matching of theIN+ and IN- external impedances to GND.

A mismatch in the series impedance in conjunction with parasiticcapacitance at the IN+ and IN- terminals ( Figure 34 ) will cause acommon mode amplitude imbalance that will show up as adifferential input signal, rapidly degrading CMRR as the commonmode frequency increases.

Maximum CMRR performance is achieved with at tention to

balancing external components and attention to PC layout.

Layout GuidelinesThe ISL28617 is a high precision device with wide band ACperformance. Maximizing DC precision requires attention to thelayout of the gain resistors. Achieving good AC response requiresattention to parasitic capacitance at the gain resistor terminals,and CMRR performance over frequency is ensured withsymmetrical component placement and layout of the inputdifferential signals to the IN+ and IN- terminals.

To ensure the highest DC precision, the location of the gainresistors and PC trace connections to the Kelvin connections aremost important. Proper Kelvin connections remove trace

resistance errors so that the amplifier gain accuracy, and gaintemperature coefficients are determined by the gain resistormatching tolerance. Interconnect constraints preclude mountingthe gain resistors next to each other, so they should be located oneither side of the ISL28617 and as close to the device aspossible. The Kelvin connections are formed at the junction ofthe sense pins ( RINSENSE, RFBSENSE) and the gain resistorcurrent drive terminals ( RIN, RFB) terminals. This junctionshould be made at the terminal pads directly under the ends ofeach resistor.

IN+

IN-

500

500 R/2

R/2C

GND

COMMONMODE ERROR

DIFFERENTIAL INPUT SIGNAL

FIGURE 34. INPUT DIFFERENTIAL LOW PASS FILTER ANDPARASITIC CAPACITANCE

TRACECAPACITANCE

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Reduced trace lengths that maintain DC accuracy are alsoimportant for minimizing the capacitance that can degrade ACstability. This is especially true at gains less than 1. Layouttechniques for precision applications using larger size precisiongain resistors at very low gains (G = 0.1V/V) include removing asection of the underlying PC ground plane directly under the gainresistor terminals and body.

Layout guidelines for high CMRR include matching trace lengthsand symmetrical component placement on the circuit thatconnects the signal source to the IN+ and IN- pins. This ensuresmatching of the IN+ and IN- input impedances ( Figure 34 ).

Power Supply DecouplingStandard power supply decoupling consists of a single 0.1F50V ceramic capacitor at the power supply terminals located asclose to the device as possible. In applications where the inputand output supplies are strapped to the same voltage (V EE = VEO,VCC = VCO) the connection point should be as close to the deviceas possible, with a single 0.1F 50V ceramic capacitor at the

junction. Applications using separate supplies require 0.1F 50Vceramic decoupling capacitors at each power supply terminal.

Estimating Amplifier DC andNoise PerformanceThe gain resistor ohmic values and ratios are all that is requiredto estimate DC offset and noise. The following sections illustratemethods to calculate DC offset and noise performance. Theseestimates are useful for optimizing resistor values for noise andDC offset.

Calculating DC Offset VoltageOutput offset voltage, like output noise, has several contributors.Also similar to output noise, the major offset contributor dependson the gain configuration. In high-gain, V

OS(I) dominates, while in

low-gain, offset due to I ERR dominates.

The summation of DC offsets to arrive at total DC offset error isperformed in two ways. Equation 13 is a simple addition of theDC offsets appearing at the output, and is useful when definingthe minimum to maximum range of of fset that can be expected.The drawback is that the result defines the corner of the cornerof the error box, and not a typical value given that these sourcesare uncorrelated.

Equation 14 expresses the total DC error as the rms, or squareroot of the sum of the squares to provide an estimate of a typicalvalue.

Equation 15 converts the output offset error range ( Equation 13 )to an input referred error range [V OS(RTI)] and enables acomparison with the DC component of the input signal.

Similarly, Equation 16 shows the typical DC offset value(Equation 14 ) referred to the input.

NOTE: These results are summarized in Table 1 .

Calculating Noise VoltageThe calculation of noise spectral density at the output [e N(RTO)]from all noise sources is given by Equations 17 and 18 :

converts the output noise to the input referred value whenevaluating the input signal to noise ratio.

Table 2 provides examples of the noise contribution of eachsource by circuit gain and output voltage span. In a high-gainconfiguration, the input noise is the dominant noise source. In alow-gain configuration, the noise voltage from the product of theinternal noise current, I N(err) , and the feedback resistor, R FB

dominates. The contribution of the internal noise current, I N(err)increases in proportion to R FB, but the corresponding increase inoutput voltage with R FB keeps the ratio of this noise voltage tooutput voltage constant.

(EQ. 13)VOS (RTO) = [(A V V OS(I) ) + (V OS(FB) ) + (I ERR R FB)]

(EQ. 14)VOS (RTO)TYP = [(A VV OS(I) )+(V OS(FB) )+(I ERRR FB)]

(EQ. 15)VOS (RTI) = [(V OS(I) ) + (V OS(FB)/ AV) + (I ERR R FB) / AV]

(EQ. 16)

VOS (RTI)TYP = [V OS(I) ) + (V OS(FB)/ AV) + (I ERR R FB) / AV)]

(EQ. 17)

e N(RTO) = [(A V e N(I)) + (2 A V i N(I) 500 ) + (A V) x (4kT R IN ) + (4kT R FB) + (R FB i N(IERR))+(e N(FB))]

(EQ. 18)e N(RTI) = e N(RTO)/A V

TABLE 1. COMPUTING TYPICAL OUTPUT OFFSET VOLTAGE RANGES

AV VO(LIN)

RIN(k )

RFB(k )

AV x VOS(I)(V)

(Note 11 )

VOS (FB)(V)

(Note 11 )

IERR

(5nA)x R FB(V)

(Note 11 )

VOS(RTO)(V)

Equation 13

VOS(RTI)(V)

Equation 15

TYPICALVOS (RTO)

(V)Equation 14

TYPICALVOS(RTI)

(V)Equation 16

1 2.5 30 30 30 400 150 580 428

1 10 120 120 15 400 600 1015 721

100 2.5 0.3 30 1500 400 150 2000 20 1560 15.6

100 10 1.2 120 1500 400 600 2500 25 1669 16.7

NOTE:11. Chosen for illustration purposes and does not reflect actual device performance.

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1 8

Intersil products are manufactured, assem bled and tested utilizing ISO9001 quality systems as notedin the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any timewithout notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to beaccurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of thirdparties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6562.2November 17, 2014

For additional products, see www.intersil.com/en/products.html


About IntersilIntersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's productsaddress some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective productinformation page found at www.intersil.com .

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask .

Reliability reports are also available from our website at www.intersil.com/support

TABLE 2. 1kHz INPUT NOISE AND THERMAL NOISE CONTRIBUTIONS

AV

RIN (k )

RFB(k )

AV x e N(I)(nV/ Hz)

2 x A V x iN(I)x 500

(nV/ Hz)

AV x (4kTx R IN)

(nV/ Hz) (4kT x R FB)

(nV/ Hz)RFB x iN(IERR )

(nV/ Hz)e N(FB)

(nV/ Hz)

e N (RTO)OUTPUT

REFERREDNOISE

(nV/ Hz)

e N (RTI)INPUT

REFERREDNOISE

(nV/ Hz)

1 30 30 8.6 0.15 22.3 22.3 78 8.6 86

1 120 120 8.6 0.15 44.6 44.6 300 8.6 307100 0.3 30 860 15 223 22.3 78 8.6 892 8.9

100 1.2 120 860 15 446 44.6 300 8.6 1015 10.15

NOTE:12. e N and i N values are chosen for illustration purposes and may not reflect actual device performance.

Revision HistoryThe revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure youhave the latest Rev.

DATE REVISION CHANGE

November 17, 2014 FN6562.2 Corrected Typo under Recommended Operating Conditions on page 4 from V E+ to V EO.Removed Important note ( All parameters having Min/Max specifications are guaranteed. Typ values are forinformation purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsedtests, therefore: T J = T C = T A) on page 4 as Note 6 covers this.Updated About Intersil verbiage.

October 17 , 2013 FN6562.1 Added a descript ion to the Related Literature on page 1 .Thermal Information on page 4 : Added theta jc (top) = 28C/W.Added two new graphs for common mode range v s output voltage (Figure 16 and 17 ).

May 25, 2012 FN6562.0 Initial release.
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Package Outline Drawing

M24.17324 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 1, 5/10

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

SIDE VIEW

END VIEW

Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

Dimension does not include interlead flash or protrusion. Interleadflash or protrusion shall not exceed 0.25 per side.

Dimensions are measured at datum plane H.

Dimensioning and tolerancing per ASME Y14.5M-1994.

Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.08mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead

is 0.07mm.

Dimension in ( ) are for reference only.

Conforms to JEDEC MO-153.

6.

3.

5.

4.

2.

1.

NOTES:

7.

5

SEATING PLANE

C

H

32

1

24

B

12

1 3

13

A

PLANEGAUGE

0.05 MIN0.15 MAX

0-80.60 0.15

0.90

1.00 REF

0.25

SEE DETAIL "X"

0.15

0.25

(0.65 TYP)

(5.65)

(0.35 TYP)

(1.45)

6.40

4.40 0.10

0.65

1.20 MAX

PIN #1I.D. MARK

7.80 0.10

+0.05-0.06

-0.06+0.05

-0.10+0.15

0.20 C B A

0.10 C

- 0.05

0.10 C B AM
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