ISHANI NARAHENPITA © 2020 ANULA...

ISHANI NARAHENPITA © 2020 ANULA VIDYALAYA 1

2020

ICT

Unit 4 - Uses operating systems to manage the

functionality of computers

Unit 4.4 Explores how combinational logic circuits are used in CPU

and sequential circuits in physical

Ishani Narahenpita (B.Sc. Sp. (Hon) IT, M.Sc. (IT)

UNIT 4.4


Half adder

The half adder adds two single binary digits. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition.

A→0

B→1 +

--- 1

A→0 B→0 + --- 0

A→0 B→1 + --- 1

A→1 B→0 + --- 1

A→1 B→1 + --- 10

INPUT OUTPUT

A B SUM SOP CARRY SOP

0 0 0 0

0 1 1 A’B 0

1 0 1 AB’ 0

1 1 0 1 A.B

SUM=A’B+AB’ →XOR

CARRY=A.B

Half adder logic diagram

Full adder The full adder adds two multiple binary digits. full-adder has three inputs and two outputs. The first two inputs are A and B and the third input is an input carry designated as Carry In. When a full adder logic is designed, we will be able to string eight of them together to create a 8- bit adder and cascade the carry bit from one adder to the next. The carry is designated as Carry Out and the sum is designated as Sum.

A→1011

B→0110

1 0 1 1 → 11

0 1 1 0 + → 6

Carry In 1 1 1 0

Sum 1 0 0 0 1 → 17

Carry Out 1 1 1 0

No 1

No 2


A B CarryIN SUM SOP CarryOUT SOP

0 0 0 0 0

0 0 1 1 A’B’C 0

0 1 0 1 A’BC’ 0

0 1 1 0 1 A’BC

1 0 0 1 AB’C’ 0

1 0 1 0 1 AB’C

1 1 0 0 1 ABC’

1 1 1 1 ABC 1 ABC

CarryIN 0 FIRST BIT 0 SECOND BIT 0








SUM= A’B’C + A’BC’ + AB’C’ + ABC → XOR

CarryOUT = A’BC + AB’C + ABC’ +ABC → AB + ACin + CinB

OR

Combination of two half adders

Full adder logic diagram


Adding multiple digit numbers using a full adder

1 0 1

1 0 1

Example 1

Second bits of number 1 and 2

First bits of number 1 and 2

Decimal Value

1 1 3

1 0 2

1 0 1 5 SUM

Full adder 1 represents

summation of first two

bits of two numbers


summation of second

two bits of two numbers


0 1 1

1 1 0

Example 2



Decimal Value

1 1 3

1 1 3

1 1 0 6 SUM


summation of first two

bits of two numbers


summation of second

two bits of two numbers


Example 03

0 1 1 1

1 1 1 0

Third bits of number 1 and 2



Decimal Value

1 1 1 7

1 1 1 7

1 1 1 0 14 SUM


summation of first two bits

of two numbers


summation of second two

bits of two numbers


summation of third two

bits of two numbers


Combinational vs Sequential circuits Combinational circuits: Output depends only on the input of that time, Sequential Circuit: Output depends

not only on the present inputs but also on the previous inputs and outputs. This type of circuit is required

to perform sequence of actions without getting any further inputs. Use for memory storage (SRAM)

No. Key Combinational Circuit Sequential Circuit 1 Definition Combinational Circuit is the type of

circuit in which output is independent of feedback of previous output and only relies on the input present at that particular instant.

On other hand Sequential circuit is the type of circuit where output not only relies on the current input but also depends on the previous output.

2 Feedback In Combinational circuit as output does not depend on the feedback, no feedback is required for its next output generation.

On other hand in case of Sequential circuit output relies on its previous feedback so output of previous input is being transferred as feedback used with input for next output generation.

3 Performance As the input of current instant is only required in case of Combinational circuit, it is faster and better in performance as compared to that of Sequential circuit.

On other hand Sequential circuit are comparatively slower and has low performance as compared to that of Combinational circuit.

4 Complexity No implementation of feedback makes the combinational circuit less complex as compared to sequential circuit.

However, on other hand implementation of feedback makes sequential circuit more complex as compared to combinational circuit.

5 Elementary Blocks

Elementary building blocks for combinational circuit are logic gates.

On other hand building blocks for sequential circuit are flip flops.

6 Operation Combinational circuit are mainly used for arithmetic as well as Boolean operations.

On other hand Sequential circuit is mainly used for storing data.

FLIP FLOPS Flip flops are actually an application of logic gates. With the help of Boolean logic, you can create memory

with them. Flip flops can also be considered as the most basic idea of a Random-Access Memory. When a

certain input value is given to them, they will be remembered.


LATCH FLIP FLOPS ▪ R-S (Reset Set) flip flop is the simplest flip flop of all and easiest to understand and RS Flip Flop is

considered as one of the most basic sequential logic circuits. The Flip Flop is a one-bit memory bi-

stable device.

▪ It has two inputs, one is called “SET” which will set the device (output = 1) and is labelled S and

another is known as “RESET” which will reset the device (output = 0) labelled as R. The RS stands for

SET/RESET.

▪ The flip-flop is reset back to its original state with the help of RESET input and the output is Q that

will be either at logic level “1” or logic”0”. It depends upon the set/reset condition of the flip-flop.

Flip flop word means that it can be “FLIPPED” into one logic state or “FLOPPED” back into another.

▪ A flip flop can be designed by using two NOR gates or two NAND gates.

▪ The flip-flop has two states which are shown in the below figure. When Q=1; and Q’=0; it is in the set

state. When Q=0 & Q’=1, it is in the clear state. The outputs of the flip flop Q & Q’ are complements

of each other and are referred to as the normal and complement outputs, respectively.

NOR SR Latch NAND SR Latch

NOR SR Latch Flip Flop A simple one bit RS Flip Flops are made by using two cross-coupled NOR gates connected in the same

configuration. The circuit will work similar to the NAND gate circuit. When 1 is applied to the inputs of the

flip flop, both the outputs go to 0, so both the outputs are complements of each other. In a normal operation,

this condition must be avoided by making sure that 1’s are not applied to both the inputs simultaneously.

Re-set Set Q’ Q Logical Meaning 1 0 0 0 0 NOT EXIST 2 0 0 0 1 Memory with Q = 1

3 0 0 1 0 Memory with Q = 0 4 0 0 1 1 NOT EXIST 5 0 1 0 0 NOT EXIST 6 0 1 0 1 SET Q to 1 7 0 1 1 0 NOT EXIST 8 0 1 1 1 NOT EXIST

9 1 0 0 0 NOT EXIST 10 1 0 0 1 NOT EXIST 11 1 0 1 0 RE-SET Q to 0 12 1 0 1 1 NOT EXIST


13 1 1 0 0 DOESNT PROVIDE EXPECTED OUTPUT

14 1 1 0 1 NOT EXIST 15 1 1 1 0 NOT EXIST 16 1 1 1 1 NOT EXIST

- Actual Outcome

1 2 3

R S Q’ Q R S Q’ Q R S Q’ Q

0 0 0 0 NOT EXIST 0 0 0 1 HOLD 0 0 1 0 HOLD

4 5 6


0 0 1 1 NOT EXIST 0 1 0 0 NOT EXIST 0 1 0 1 SET

7 8 9


0 1 1 0 NOT EXIST 0 1 1 1 NOT EXIST 1 0 0 0 NOT EXIST

10 11 12

0 Start

0 1

1

Start 0

Start 1

0 1

0

1 Start

1 0

Start 0

Start 0

1 0

1 1

0 1

1

0 Start

0 0

Start 1

Start 0

0

1 1

1 0

1

1 1

0 0

1 0

0 1



1 0 0 1 NOT EXIST 1 0 1 0 RE-SET 1 0 1 1 NOT EXIST

13 14 15

R S Q’ Q DOESN’T PROVIDE REQUIRED OUTPUT

R S Q’ Q R S Q’ Q

1 1 0 0 1 1 0 1 NOT EXIST 1 1 1 0 NOT EXIST

The Set State

By definition, a condition of Q=1 and not-Q=0 is set. flip-flop circuit is said to be “LATCHED” or “SET” with Q = 1 and

Ǭ = 0.

The Reset State

A condition of Q=0 and not-Q=1 is reset. flip-flop circuit is said to be “LATCHED” or “SET” with Q = 0 and Ǭ = 1.

Invalid State

For a NOR gate latch both input HIGH turns off both output LEDs. Having both S and R equal to 1 is called an invalid or

illegal state for the S-R NOR Latch.

16

R S Q’ Q

1 1 1 1 NOT EXIST

1 Start

1 Start 1

Start 1

1

0 0

0

0

0 1

0

1 1

0

1 1 0

0 Start

0 Start 0

Start 0

0

0 1

1

1

0

0

1 1

0

1 1 0 0

1

Start 1

1

1 1

0

0

1 0


Set Re-set Q Q’ Logical Meaning 1 0 0 1 0 Memory with Q = 1

0 1 Memory with Q = 0

2 1 0 1 0 SET Q to 1 3 0 1 0 1 RE-SET Q to 0

4 1 1 0 0 DOESNT PROVIDE EXPECTED OUTPUT

Timing diagram

SET

HO

LD

RE-

SET

HO

LD

0FF

SET

HO

LD

RE-

SET

OFF

RE-

SET

HO

LD

SET

OFF

SET

HO

LD

1 2 3 4 6 7 8 9 10 11 12 1 10 1 2

S 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0

R 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0

Q 1 1 0 0 0 1 1 0 0 0 0 1 0 1 1

0

Q’ 0 0 1 1 0 0 1 0 1 1 0 0 0 0

NAND SR Latch Flip Flop

OR

Re-set Set Q’ Q Logical Meaning 1 0 0 0 0 NOT EXIST 2 0 0 0 1 Memory with Q = 0 3 0 0 1 0 Memory with Q = 1 4 0 0 1 1 NOT EXIST 5 0 1 0 0 NOT EXIST 6 0 1 0 1 Set Q to 1

7 0 1 1 0 NOT EXIST 8 0 1 1 1 NOT EXIST 9 1 0 0 0 NOT EXIST 10 1 0 0 1 NOT EXIST 11 1 0 1 0 Re-set Q to 0 12 1 0 1 1 NOT EXIST 13 1 1 0 0 NOT EXIST

14 1 1 0 1 NOT EXIST

15 1 1 1 0 NOT EXIST 16 1 1 1 1 DOESNT PROVIDE EXPECTED OUTPUT


- Actual Outcome

1 2 3


0 0 0 0 NOT EXIST 0 0 0 1 Memory with Q = 0 0 0 1 0 Memory with Q = 1

4 5 6


0 0 1 1 NOT EXIST 0 1 0 0 NOT EXIST 0 1 0 1 Set Q to 1

7 8 9



0 Start

0 1

0 1

0 0

1

1

1 Start

0

0 0

0 1

1

1

0 Start

0

0 1

1 0

1

1

1 Start

0 0

0 0

1 1

1

1

0 Start

0

1

1 1

1 0

0

1

1 Start

0

1 0

0 1

0

1

0 Start

0

1

1 1

1 0

0

1

1 Start

0 0

1 0

1 1

0

1

0 Start

1 1

0 1

0 0

1

0


10 11 12


1 0 0 1 NOT EXIST 1 0 1 0 Reset Q to 0 1 0 1 1 NOT EXIST

13 14 15



The Set State

By definition, a condition of Q=1 and not-Q=0 is set. flip-flop circuit is said to be “LATCHED” or “SET” with Q = 1 and

Ǭ = 0.

The Reset State

A condition of Q=0 and not-Q=1 is reset. flip-flop circuit is said to be “LATCHED” or “SET” with Q = 0 and Ǭ = 1.

Invalid State

For a NAND gate latch both input HIGH turns ON both output LEDs. Having both S and R equal to 1 is called an invalid

or illegal state for the S-R NAND Latch.

16

R S Q’ Q DOESNT PROVIDE EXPECTING OUTPUT 1 1 1 1

1 Start

1 1

0 1

0 1

1

0

0 0 Start

1

0 1

1 0

1

0

1 Start

1

0 1

1 1

1

0

0

0 Start

1 1

1 1

0 0

0

0

1 1 Start

1 1

1 1

0 1

0

0

0 Start

1

1 1

1 0

0

0

1

1 Start

1

1 1

1 1

0

0


Timing diagram

NOR Latch Flip flop and NAND Latch flip flop using a simulator.

Re-set Set Q’ Q Logical Meaning 1 0 0 0 1 Memory with Q = 0 2 0 0 1 0 Memory with Q = 1 3 0 1 0 1 Set Q to 1 4 1 0 1 0 Set Q to 0 5 1 1 1 1 DOESNT PROVIDE EXPECTED OUTPUT

SET

HO

LD

RE-

SET

HO

LD

INV

ALI

D

SET

HO

LD

RE-

SET

INV

ALI

D

RE-

SET

HO

LD

SET

OFF

SET

HO

LD

1 2 3 4 6 7 8 9 10 11 12 1 10 1 2

S

R

Q

Q’

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