ISEA Script Lab Power Electronic Devices

Rheinisch-Westfälische Technische Hochschule Aachen · Institut für Stromrichtertechnik und Elektrische AntriebeUniversitätsprofessor Dr. ir. Rik W. De Doncker

RWTH Aachen University · Institute for Power Electronics and Electrical DrivesProfessor Dr. ir. Rik W. De Doncker

Student Laboratory:Power Electronic Components

October 14, 2010

Contents

1 Introduction 1

2 Thyristor 22.1 PNPN structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 Latching with open gate contact . . . . . . . . . . . . . . . . . . . . . . . . . 32.3 Two-transistor equivalent circuit diagram . . . . . . . . . . . . . . . . . . . . 52.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4.1 Latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.5 Device structure in student laboratory . . . . . . . . . . . . . . . . . . . . . 7

3 Basics and procedures for the manufacturing of semiconductor devices 93.1 Diffusion processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.2 Photolithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.3 Plasma etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.4 Oxide formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.5 Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.6 Annealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.7 Four-terminal sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Overview of the manufacturing process 18

5 FEM simulation 21

6 Clean Room 236.1 Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.2 Wafer Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.3 Safety instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 Experiment 1: Introduction into the properties and fabrication of GCTs 27

8 Experiment 2: Introduction into the device simulation tools 288.1 Introduction into the device simulation tools . . . . . . . . . . . . . . . . . . 28

8.1.1 Device Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9 Experiment 3: Device and Process simulation 369.1 Inspect, Tecplot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369.2 Process simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

ii

Contents iii

10 Experiment 4: Clean room and safety introductions, start of thyristor fabri-cation; substrate preparation and doping 40

11 Experiment 5: Four-point, diffusion depth, oxide layer growth and metalliza-tion 43

12 Experiment 6: Lithography, etching and measurement of the etch profile 45

13 Experiment 7: Visit Infineon, last experimental steps 46

14 Experiment 8: Device measurement 47

15 Experiment 9: Presentation 48

List of Figures 49

List of Tables 51

Bibliography 52

1 Introduction

This student laboratory will give an insight into the effort and challenges that exist inthe fabrication of semiconductor devices. Several productions steps like FEM simulations,high-temperature diffusion, photolithography, annealing and metallization are addressed.The goal is to fabricate a gate-commutated thyristor (GCT) and to show the technical andtime-consuming effort for the production of a rather trivial appearing device. The studentlaboratory includes an excursion to the production site of a semiconductor company.

The thyristor has been a long time the dominant device in power electronics and can alsobe fabricated without fine structures or high-precision photolithography. Especially for lowfrequencies in soft-switching components like for rectifier operating at 50 Hz thyristors aresuited. A further application field for thyristors is the power class with very high voltagesand currents, which is not reached by other devices yet (1.1).

Figure 1.1: Applications fields of power devices [ISEA]

1

2 Thyristor

2.1 PNPN structure

Figure 2.1: PNPN structure of a thyristor [ISEA]

2

2 Thyristor 3

The PNPN structure of a thyristor is shown in figure 2.1. J indicates the junction of twodifferent doped regions. At the junction is n = p (equilibrium condition). A positive voltagebetween anode and cathode in off state (no voltage is applied at the gate) is called forwardblocking voltage and a negative voltage as reverse blocking voltage. In the non-conductivestate, the thyristor can hold both voltages up to reaching the respective breakdown voltage.Figure 2.2 a) and b) show the respective space charge regions with the corresponding I-V -characteristics. The space charge region expands in reverse and blocking mode mainlyinto the low n-doped region. In conduction mode the I-V -characteristic of a thyristor islike that of a diode (figure 2.2 c). First it needs to be figured out how the device can bebrought into the conducting state. The structure of the junctions appears as that this willnot be possible. Because at least there is always one P-N junction, which is in reversemode. Thermally generated charge carriers can act in the thyristor structure (with opengate) as a base current in a NPN transistor. By this many free charge carriers are createdand the device is latched (conducting mode). This procedure corresponds in principle tothe intended latching through the gate contact. But with linear amplification factors thethyristor can not described in all the fields.

Figure 2.2: Space charge regions with the corresponding I-V-characteristics for a) reverse,b) blocking, c) conducting [ISEA]

2.2 Latching with open gate contact

First, the switching on of the thyristor with open gate contact will be considered. Afterapplying a voltage in forward direction a (low) current IA flows through the thyristor, which

2 Thyristor 4

is equal at each P-N junction, see figure 2.2.

IA = IJ1 = IJ2 = IJ3

In the highly P-doped region (anode side) the total current IA flows nearly as pure defectelectron flow. The asymmetrical P-N junction J1 is biased in forward direction. Thereforedefect electrons in the form of a diffusion current flow into the next N-region. There the holediffusion current is weakened by recombination with electrons from the strongly N-dopedarea (cathode side). Only one part

αP · IA = IJ2p

of the hole current reaches reversed biased P-N junction J2, that means that only one partof the current IJ2 = IJ2p + IJ2n is carried by defect electrons. The electron current I2n isthe portion of the total current. In the highly N-doped region of the cathode there is onlyelectron current, which diffuse toward the anode and recombine partly. Only the currentportion

αN · IA = IJ2n

reaches the transition J2.

The current balance on the central junction is

IA = αp · IA + αN · IA

This equation is not only formally correct. The space charge region in the thyristor withforward blocking voltage expands spatially. Junction J2 is biased in reverse mode. Chargecarriers, which have been generated in the space charge region can not be neglected andlead to the quiescent current portion IR2. This is added to IA, since the past considerationis valid only up to the borders of the space chare region.

IA = αP · IA + αN · IA + IR2

The total current is therefore

IA =IR2

1− (αP + αN)

2 Thyristor 5

As long as αN + αp < 1, which is the case for sufficient recombination, the current IA remainsfinite. For αN + αp → 1 the current results in IA →∞.

For αN + αP = 0,999 the current results in IA = 1000 IR2. For αN + αP > 1 the currentIA < I2p + I2n + IR2 and the current at junction J2 would be larger than the current throughthe outer electrodes. This condition can occur only transiently. A displacement current

|Iv| = A · εrε0 · dEdt

occurs and the space charge and the field strength at junction J2 gets reduced. The blockingP-N junction disappears and thus the thyristor is conducting.

Figure 2.3: Switching of the thyristor at sufficiently high reverse current in the forward mode[ISEA]

2.3 Two-transistor equivalent circuit diagram

The four layer structure can be replaced by two transistors (figure 2.4, right image) thathave a PNP and an NPN-layer sequence. The two outer areas are heavily doped, as shownin figure 2.1, therefore the junctions J1 and J3 show good emitter properties in forward biasof the respective carriers into the central base areas.

In the left image of figure 2.4 the turn-on sequence of the thyristor is shown. As soon theswitch in the control circuit is closed, a control current flows through the P-N junction J3.This junction is now more biased in forward direction and more electrons move from theN-emitter into the P-basis. They partly recombine with the holes of the base, which aresupplied by the base contact. One part of the electrons reaches the space charge regionof the N-collector, which is the base of the (upper) PNP transistor. By analogy the sameprocess occurs in the (upper) PNP transistor. Holes from the emitter of the PNP-transistor(anode of the thyristor) flow into the base. One part of the holes reaches the space chargeregion of the P-collector, which is the base of the NPN transistor. The positive feedback of

2 Thyristor 6

Figure 2.4: The four layer structure of the thyristor replaced by two transistors. Right imageshows the equivalent circuit diagram of a thyristor as a pair of tightly coupledbipolar junction transistors.[ISEA]

these effects leads to a reduction of the space charge region at J2 and an increase of chargecarriers in both base areas. Finally the current reaches a stationary level which is limitedby the resistance in the circuit. The feedback effect between the emitter junctions J1 andJ3 or rather the switching on of the thyristor with a sufficiently large reverse current at theP-N junction J2 can be initiated also without a control current. There is surplus of chargecarriers in the space charge region of J2 The charge carriers are separated by the field inthe space charge region and move into the middle areas.

It is:

I1 = IAαP + IR1 IR1, IR2 is the reverse current of the single transistors

I2 = (IA + IG)αN + IR2

I1 + I2 = IA(αN + αP ) + IGαN + IR1 + IR2 with IR1 + iR2 = IR it follows

IA = IA(αN + αP ) + IGαN + IR transformed it follows

IA =IGαN + IR

1− (αN + αP )

As explained before, the gain factors αN and αP are influencing the latching properties. Bothfactors can be adjusted by the doping and the dimensions of the layers during the fabricationof the device. If the sum of these factors is above one, then the device is permanently turnedon.

2 Thyristor 7

2.4 Summary

2.4.1 Latching

The most common latching of a thyristor is the injection of a gate current IG. For the safeuse a minimum current IG min and a minimum voltage VG min have to be supplied by a controldevice, assuming a positive anode-cathode voltage. In turned off state the NPN transistorblocks due to a negative or neutral base voltage. To turn on, a positive gate current hasto be applied. The NPN gets a positive base current, thus the collector-emitter is of lowresistance and the transistor is switched to "LOW". The voltage on the collector-emitterpath decreases. Due to the circuit the VBE PNP voltage is larger and the PNP transistorswitches to "LOW". The supplied current Ic NPN now supplies the base current for the NPNtransistor. Once the latching process is initiated, the base of NPN-transistor theoreticallycan be left in high resistance, since the turn on effect is self-reinforced by the negativefeedback. Usually small positive gate currents are used in order to ensure constant engagingat low loads.

2.5 Device structure in student laboratory

A bipolar device must have two characteristics, high blocking voltage and current gain,which are not compatible at first glance. By the choice of the dimensions a N−P −N−−Pstructure can be created which solves this conflict.

The four-layer semiconductor structure of thyristors can be described by the layer sequenceshown figure 2.5 including the contacts. The base contact of the NPN transistor is the gatecontact of the whole structure and its emitter is the cathode. The collector of the NPNtransistor is in the N-doped substrate, which is at the same time the base contact of thePNP transistor. The collector and emitter of the PNP transistor are the gate and the anodeof the whole structure respectively.

2 Thyristor 8

Figure 2.5: Structure of four-layer sequence of a thyristor including the contacts

The used Si wafers have a thickness of 525 µm (semi standard) and are phosphorus doped(N-type) with a donor concentration of 1·1014 cm−3. Depending on the intended deviceproperties and by taking into account the occurring strain by doping, the depths of layerscan be varied. In this case the thicknesses are:

N-doped cathode layer: ≈ 3-4 µm

P-doped gate layer: ≈ 40 µm

P-doped anode layer: ≈ 40 µm

3 Basics and procedures for themanufacturing of semiconductor devices

3.1 Diffusion processes

For a better understanding of the distribution of impurities in semiconductors a brief physicaldescription of the diffusion process is given here. In principle there are three differentmethods of doping semiconductors: diffusion, ion implantation and epitaxy. For thyristormanufacturing diffusion is preferred because of its simple handling. The term "diffusion"describes the process of balancing the differences in concentration. In order to diffusedopants into a silicon (Si) crystal, a high concentration of impurities is generated outsideof the Si. The diffusion takes place automatically because of the concentration difference.At room temperature this balancing process is very slow and can be speed up at highertemperatures. The diffusion is thus a process that should be carried out at the beginning ofthe device fabrication to prevent later the destruction of any temperature-sensitive structureon the wafer like the metallic contacts. The diffusion process creates an over the space ofsome monolayer spread P-N junction. Gaussian profile can be created with the help of thediffusion in which the maximum doping concentration is at the surface. The process of thediffusion is described by Fick’s first and second law. It is sufficient to consider Fick’s firstlaw one-dimensional, since it is assumed that the diffusion from the wafer surface into thewafer occurs one-dimensional:

J = −DdNdx

J is the diffusion flux in mol/m−2s, N the concentration in cm−3 and D is the diffusioncoefficient in m2/s, which is in solids depending on the direction, except in cubic and diamondlattice structures.

The law describes the proportionality of the current density J to the concentration gradientdNdx

. The Fick’s second law of diffusion describes the relationship between the temporal andspatial changes in the concentration N and follows from the continuity equation

dNdt

= −dJdx

as well as from Fick’s first law to:

9

3 Basics and procedures for the manufacturing of semiconductor devices 10

dNdt

= Dd2N

d2x

For different boundary value problems and initial value problems different solutions of Fick’ssecond law can be found. In general two cases are distinguished: the diffusion from an infiniteand from a finite (dopant) source. Doping is achieved by diffusion of atoms from the surfaceinto the layer. If the doping level on the surface does not change, then the source for dopingis infinite. The solution of Fick’s second law is a complementary error function:

N(x,t) = N0 · erfcx

2√D(T ) · t

(3.1)

With:

N0 surface concentrationx doping depthD(T ) dconstant, depending on the temperature and the dopantt diffusion time

For the diffusion from the gas phase and with a sufficiently thick doping layer on the sub-strate surface an infinite source is assumed. A semiconductor surface that is exposed to ionimplantation where a thin layer with a limited number of ions or atoms is created on thesurface corresponds to diffusion from a finite source. The solution of Fick’s second law leadsafter approximation to a Gaussian profile:

N(x,t) =Q√

πD(T ) · t· e−

x2

4D(T )·t (3.2)

With: Q = N0 · d

d initial thickness of source layer on surfacex doping depthD(T ) diffusion constant, depending on the temperature and the dopantt diffusion time

The surface concentration decreases with the diffusion length and the total concentrationof impurities remains constant over the substrate thickness. In figure 3.1, the impurityconcentration N is shown normalized to the surface concentration according to the Gaussianprofile.


Figure 3.1: Diffusion behavior for infinite (left) and finite (right) dopant source [Zim]

3.2 Photolithography

The photolithography is a transferring process, in which the structures of a mask (like inleft image of figure 3.2) are mapped onto a photoresist. For the processing of semiconductordevices defined areas on the surface have to be protected by photoresist from processeslike etching or deposition of a material. A light-sensitive photoresist is deposited onto awafer. This is done by dropping some droplets of photoresist onto the wafer surface. Thewafer is placed in a so-called spin-coater, where by fast rotation the photoresist is spreadhomogenously. In a photolithography system it is exposed to light through a mask and thendeveloped. There are positive and negative resists. The chemical bonds of the positive resistare cracked during the exposure and therefore the solubility in a developer is increased. Incontrast, the molecular chains crosslink in a negative resist by exposing to light. Here itis difficult to remove the exposed areas by the developer. In the right image of figure 3.3the difference between positive and negative photoresist is shown after development. The(photo)mask is usually made of a chromium layer which is deposited on a quartz substrate.For the relatively rough structure of a thyristor, however, it is sufficient to use a foil-printedmask fixed on glass. The structures of the foil mask have to be in a very homogeneousblack. For this a laser printer with a resolution of 25,000 dpi is necessary. For comparisonstandard office printer have a maximum resolution of 1,200 dpi, as shown in figure 3.2(left). There are three different exposure methods: contact, proximity and projection. Thesimplest exposure system is contact lithography. Here the mask is in direct contact with thephotoresist and therefore the highest resolution is possible. In the proximity method thereis small gap between mask and substrate of 10 µm to 50 µm. The advantage is that themask keeps clean but the disadvantage is a lower resolution. In the projection lithographythere is also a gap between wafer and mask, but here the pattern of the mask is projectedby lenses onto the surface. The advantage here is that the pattern of a small mask like for


Figure 3.2: Photomask for thyristor process (right) and difference of positive and negativeresist (right) [Zim]

a certain device can be projected many times onto a wafer.

3.3 Plasma etching

Plasma is an ionized gas consisting of neutral as well as from excited atoms or molecules,ions and electrons. It can be generated in a high frequency field (usually 13.56 MHz) andexhibits a characteristic color depending on the used gas.

Plasma etching is a chemical, physical or combined etching process. In the chemical dryetching with plasma, gaseous reaction products are generated which lead to a high selectivitywith isotropic etching profiles. In the physical process a bombardment of the substratesurface with inert ion takes place which beats out physically material. Due to the defineddirection of the bombardment of almost perpendicular to the surface the etching profilesis anisotropic. The etching method in this student laboratory is the chemical dry etchingprocess. The used process gases are sulfur hexafluoride (SF6) and oxygen (O2), which getcracked in plasma to free fluoride radicals F* and SFx ions.

In the chemical etching process fluorine radicals attack the surface and form gaseous Sitetrafluoride SiF4.

Characteristic for this process is the formation of a SiOxFy mixed oxide, which coversthe inner side wall and the bottom of the etched valley. This passivative oxide creates aprotection against the fluoride radicals. Due to the vertical ion bombardment the protectiveoxide layer on the bottom is removed whereas the cover remains at the side walls. By thiscondition the fluoride radicals etch only the bottom and the side walls keep protected theby the oxide layer. This creates a highly anisotropic etching profile (figure 3.3).


In the plasma the following reaction take place:

SF6 → SF∗5 + F∗

SF6 → SF∗4 + 2F∗

SF6 + e− → SF∗5 + F−

SF6 + e− → SF−5 + F∗

SF6 + 2e− → SF4 + 2F−

O2 → 2O∗

SF6 + O∗ → SOF4 + F∗

Table 3.1: Chemical reaction during the etching process

Figure 3.3: Etching process by SF6 and O2 [Zim]

3.4 Oxide formation

Silicon dioxide (SiO2) is the native oxide of Si and it is process compatible with the Sitechnology. It has a very high specific resistance of around 1014 to 1016 Ωcm at room tem-perature. There are two procedures to form SiH4 on Si: deposition and thermal oxidation.During the deposition gases like silane (SiH4) and O2 are led onto the substrate at tem-peratures of around 300 °C to 800 °C. The gases get cracked and the oxide is formed onthe surface. The benefits of the deposition in comparison to oxidation are the constantdeposition rate and the low process temperatures. For the thermal oxidation temperaturesover 1000 °C are necessary. Here the Si substrate acts as supplier of the Si. This is a trans-formation process of the Si surface in an O2 environment to SiH4. With increasing thicknessof the SiH4, the oxygen has to diffuse through the already formed oxide to the interface.There is a distinction between dry and wet oxidation. In the dry oxidation of Si the waferreacts with O2 to SiH4. In the wet oxidation of Si, water vapor is flowing on the Si surface.


At high temperatures, water cracks into pure hydrogen (H2) and in an OH-group. Thisdiffuses much faster through the already formed oxide due to the smaller size in comparisonto the O2 molecule in the dry oxidation process. Therefore, the wet oxidation has up tothree times higher growth rate than the dry oxidation. The oxide layer of the dry oxidationis however a denser oxide, which is resulting in higher breakdown field strengths.

3.5 Metallization

There are two families of deposition processes described in the literature, the chemical andphysical deposition techniques. These methods are used for the reproducible productionof layers with no or only defined amount of impurities for variety of applications. Singlecrystalline or polycrystalline films can be used as insulator, passivation, conductive layer orsemiconductor heterojunction (deposition of a semiconductor onto one of different material,such as Si-Ge).

The process step of metallization, necessary in this student laboratory, is performed by amethod belonging to the physical vapor deposition (PVD). These procedures include themolecular beam epitaxy (molecular beam epitaxy, MBE), the evaporation and the sputter-ing. The MBE requires ultra-high vacuum and is for pure metal coating unprofitable andcostly.

In the process of evaporation the material that is deposited on the wafer is heated in amelting crucible, boat or filament until it evaporates and the metal vapor condensates onthe substrate. A variant of this process is that an electron beam is used to vaporize the targetmaterial. Because of the low deposition rate and the poor edge coverage, this procedureis primarily used for the complete wafer surface metallization, such as the back side ofwafers.

In the method of sputtering, which is used in this laboratory, ions hit out particles fromthe target (here: aluminum (Al)) and they condensate similar to the evaporation processon the substrate. As actinometric gas (gas which is ionized and passes its energy troughcollision) argon and helium is used. The ionization of gases is done by plasma. Plasma canbe generated by electromagnetic fields and electrostatic excitation and the charge carriersin it are increasing avalanche. The plasma is thus a formation of electron gas and ion gas.Since the charge carriers are generated in spatially close to each other, plasma is quasi-neutral. Plasma is the ionized state of matter and, in addition to solid, liquid and gaseousit is regarded as the fourth state. The most common occurrence in space is plasma. Ineveryday life for example we find plasma in fluorescent lamps.

3.6 Annealing

There are two kinds of metallic contacts on semiconductors: Schottky contacts and ohmiccontacts. Besides on heavily doped layers, as deposited metal contacts show usually Schottky


behavior and without thermal annealing the contact show rectifying properties as a P-Njunction. In order to create an ohmic contact the metal-semiconductor layer needs to beannealed. Here Al is used as metal contact. The wafers are heated up with at 5 °C/min to470 °C and remained at this temperature for 60 min. After this the temperature is cooleddown with 5 °C/min. By slow cooling down process internal stresses and defects of thecrystal structure, caused by previous processes can be healed.

3.7 Four-terminal sensing

The created doping concentration can be measured by using the so-called four-terminalsensing (also 4-wire sensing or 4-point probes method). In figure 3.4 the principle of thismeasurement is outlined. In this method, the resistance of a sample is measured by a sensorhead with four probe tips which is placed on the surface. The four probe tips are arrangedin series with a constant distance s of usually 0.5 to 1.5 mm. By the two outer contactsa low current is supplied in the range some milliampere, to keep the heating and thus achange in the electrical layer properties as small as possible. With the inner contacts, thevoltage drop is measured. From these values, the sheet resistance is determined, by takingthe potential lines in the semiconductor and the sample geometry into account.

Figure 3.4: Principle of the four-terminal sensing [Zim]

It is differentiated whether the sample thickness d is big or small in comparison to the probetip spacing s. In our case d « s and thus the equipotential regions are concentric cylindersperpendicular to the surface. The current paths are approximately perpendicular to theseplanes and thus, the current density can be taken as


J =I

2πrd

where r corresponds to the radius of each traversed region. For the electric field it follows:

E = ρ · J

The voltage between the points 2 and 3 is calculated with the path integral of the electricfield strength E. The factor 2 takes into account the incoming and outgoing electric field.

V23 = 2 ·ˆ 3

2

Eds = 2 ·ˆ 3

2

(ρI

2πd

1

r)dr (3.3)

= 2 ·ρI

2πd

ˆ 2s

s

1

rdr =

ρI

πd(ln 2s− ln 2) =

ρI

πdln 2 (3.4)

(3.5)

This gives the sheet resistance as:

Rs =ρ

d=V23

I·π

ln 2

From the sheet resistance the carrier concentration can be concluded by means of the so-called "Irvine Curves". In Figure 3.5 different Si Irvine curves are shown. The graphs arefor N and P doped material and the doping type, with infinite and finite doping source. Theabscissa shows the ohmic resistance multiplied by the junction depth xj in µm.


Figure 3.5: Irvine curves for different dopants and doping profiles

4 Overview of the manufacturing process

The target of this student laboratory is to fabricate a Si-based layer structure which corre-sponds to the four-layer structure of the thyristor. Si substrates are the base material forthe thyristor. In this case, they have a polished, shinny and a matte, non-polished side,which is very helpful to distinguish later on in the process. The doping is done using afurnace. For this a special substrate carrier called boat is used, which is load with the waferand the source discs as shown in figure 4.1. The boat is made from quartz or from Si.

Figure 4.1: Fully loaded wafer boat without source discs (left) and schematic side view ofwafer boat with Si-wafers and source disks (middle and right)

The principle process of the p-type doping with boron is that first a thin layer of siliconboride (SiB) is grow on the wafer. This is used in the further process as a finite dopingsource in the diffusion process. In this laboratory the p-doping of the gate and anode areaare fabricated first, followed by the cathode area. For resulting in different p-doping levelsof the gate and anode area, they have to be processed in two different steps or the side ofthe wafer with the expected higher doping level has to be processed again as described inthe following.

After loading the wafer boat with substrates and source disks, here boron nitride (BN) asshown in figure 4.1 (middle and right) into the furnace, in a first step the boron nitridediscs are oxidized in an O2/N2 atmosphere at 700 °C to B2O3. The generated oxide depositson the Si surface. Here, the Si-surface pointing to the BN disk will be coated. For thedeposition on a single side, a dummy wafer can be used to shield one side or two Si-waferscan be placed with the sides to each other that should remain uncoated (figure 4.1 right).The created oxide on the Si-wafer is reduced with 2 H2 in the gas phase from B2O3 toHBO2, which is a boron glass. This H2 step defines the intended amount of B on theSi-surface and therefore the doping concentration in the Si. The HBO2 on the Si-surfaceis formed in a N2 environment for 20 min at 750°C to a thin SiB and SiO2 film. This

18


SiB layer is the source that provides the impurities at the Si/SiB interface [RUG75]. Thecreated glasses are removed with hydrofluoric acid (HF), but SiB can not be etched withHF, but it must be removed, since it serves as impurity source and would result in a toohigh doping concentration. An additional temperature step ("Low Temperature Oxidation"- LTO) is necessary. The boron and a thin layer of Si underneath are oxidized for onehour at 850 °C in an O2 atmosphere and can be then etched with HF later on. Thereby aspecific doping concentration can be achieved. Since the desired concentration has now beenreached, the boron atoms are driven into the substrate by diffusion. As explained before,the doping depth can be managed by temperature and time. In this laboratory the wafersare heated up in the furnace to 1200 °C. After each process step a standard cleaning has tobe performed. By the described steps the wafer will have a P-N junction with a depth of40 µm for the P-layer at both sides, as shown in the left image of figure 4.2. As mentionedbefore the two sides can be doped with different doping levels. If a heavily doped anodearea is requested (for example for electrical contact issues), the process is similar to that ofthe gate area, since it is the same doping type but differ in the concentration. Here the H2

step to form a boron glass is not used and therefore more material is left on the Si-surfaceto achieve a higher p-type doping concentration.

The n-type doping of the cathode is reached by phosphorus diffusion. The source discs areof cerium pentaphosphate (SiP2O7), which is a layer on a chemically inert substrate. Thediffusion process is similar to that of the anode and gate, but here no oxidation step of thesource material is required. At diffusion temperatures the active component SiP2O7 cracksin SiO2, which remains on the source disk and P2O5-gas, which adsorbs and reacts on theSi-wafer. Depending on the desired doping concentration the diffusion process takes placeat 975 °C to 1025 °C for 20-80 minutes in presence of the source discs. The result of thisdiffusion processes is the desired four-layer structure of the thyristor (figure 4.2 right).

Figure 4.2: P-N junction (left) and four-layer structure (right) after diffusion process


To create the aimed device from the described four-layered structure some process steps,such as lithography, etching, metallization and oxidation are necessary. These steps willtransfer 3D-structures with defined areas of metallization and oxidization to the structure.A complete overview of the steps is shown in figure 4.3.

Figure 4.3: Fabrication steps of a GCT [Zim]

5 FEM simulation

The used software is the FEM simulation program TCAD 8.0 (Technology Computer AidedDesign) from Integrated Systems Engineering (ISE), which is now owned by Synopsys Inc.It consists of several sub-programs which can be all controlled with the main interfaceGENESISe. With the help of scripts easily simulations with automated pass through ofparameters can be realized. In the following the used subroutines are described briefly. ButTCAD has much more features than presented here.

MDrawWith the help of MDraw the geometric dimensions with the corresponding connections, thedoping profile as well as the sizes of the grid that represent the finite elements are defined.Here a graphic tools or a script can be used.

DessisDessis is the current FEM simulation program. It enables to record currents and voltagesor other parts of a network at defined times. The graphical evaluation of the electric circuitand of the points to be measured is done text-based. The disadvantage is that there is nodebugging tool and no automatic syntax control available. Therefore is not guaranteed, ifthe simulation is successful or if it must be repeated.

Further the script offers the possibility to significantly influence the physical and mathe-matical context such as:

• Temperature

• Maximum electron saturation

• Band gap energy difference

• Recombinationeffects

• Carrier lifetime

• Number of iterations

The device is built up in two dimensions. Dessis assumes a depth of 1 µm and converts thesimulation results by using an AreaFactor. The AreaFactor is defined as follows:

AreaFactor = Area Of SemiconductorWidth Of Semiconductor·1µm

21

5 FEM simulation 22

InspectWith this tool, the simulation results at defined contacts can be shown as graphics in acoordinate system. This is also possible in-situ during the simulation.

LigamentLigament is a tool which allows simulating the manufacturing processes for semiconductorssuch as diffusion processes and etching processes. It is used to determine the requireddiffusion times and temperatures. The scripts provided with Ligament are translated andsimulated with the subroutine Dios.

TecplotTecplot is a visualization program which shows the characteristics of different device pa-rameters. Depending on the content of the loaded input data, diffusion profiles, potentialprofiles, field strength curves, etc. can be shown in cross sections of the device.

6 Clean Room

The central laboratory of technology belongs to the Chair of Electromagnetic Theory (ITHE),the Institute of Materials in Electrical Engineering (IWE 1) and the Institute for PowerElectronics and Electric Drives (ISEA). To work in a clean room certain rules must beconsidered.

In order to keep a constant level of cleanliness in the clean room, it is necessary to wear cleanroom suits. These are used primarily to protect the cleanroom from contamination. Thesuit may be in one piece or consist of several separate garments worn tightly together, likegloves, caps and overshoes. The clean room area is entered through a so-called air shower.Two doors are passed to get into the clean room where only one door is allowed to be openat one time. The area between these doors is usually around 1 m2. As soon the door fromthe grey room is closed, the door to the clean room is first looked and is set free to open aftera several time (10 sec to 30 sec). Within this time air is blown from the side and taken awayfrom the top. By this possible particles on the clothes can be removed. Clean rooms aredivided into classes. These classes represent the average density of particles per m−3. Forexample, "class 1" clean rooms (1 partikel/m3) have the highest level. Standard cleanroomclasses are "class 1000" cleanroom and "class 100" cleanroom.

6.1 Preparation

The ISEA is using three rooms in the laboratory. They are needed for wet chemical cleaning,for plasma etching and the furnace processes. Because it is not an industrially used clean-room, here in this clean room at the beginning of the work it is to ensure that the valvesfor DI-water and the required gases and acids for cleaning of the substrates are opened.

6.2 Wafer Cleaning

The processing of semiconductors requires perfect cleaned wafer surfaces, to guarantee re-producible results and device performance. Impurities that are not removed will diffuse deepinto the Si wafer in the many fabrication steps, since some of them occur at high temper-atures. This leads to unwanted doping types and concentrations. Therefore sophisticatedcleaning procedures have been developed. For the cleaning procedure additional protectiveclothing is necessary. As acids like HF, hydrochloric acid (HCl) and sulfuric acid (H2SO4)are used for the wet chemical cleaning.

23

6 Clean Room 24

Since 1971, the so-called "RCA Clean" became a standard wet chemical cleaning process,which is named after the company "Radio Corporation of America" [MOK06]. This methodconsists of two different processes, the "RCA 1" and the "RCA 2". For heavily contaminatedwafers the so-called "Piranha-etch" is done first. In the following the different etch stepsare described briefly [MOK06]] [SPA06b].

Piranha etching

With this acid mixture organic contaminations can be removed. For this the Si wafer willbe left ten minutes in this solution. This mixture consists of:

H2O2(25%) : H2SO4(97%)1 : 2

RCA 1

These etch step removes also mainly organic contaminants. It consists of H2O2, ammoniumhydroxide (NH4OH) and DI-water and is used in the following ratio:

H2O2(25 %) : NH4OH(25 %) : H2O1 : 1 : 2

The H2O2 oxidizes the wafer surface and the particles on it, by this the adhesion forcesdecrease between particles and wafer. The particles move into solution and the wafer surfaceis protected by the oxide layer from recontamination. At the same time, the ammoniumhydroxide etches the wafer surface and undercuts the particles [ASS07]. The duration ofthis cleaning step is ten minutes.

RCA 2

In combination with H2O2 hydrochloric acid (HCl) is a very effective solution for the removalof metallic contaminations. It is used the following ratio:

HCl(30 %) : H2O2(25 %) : H2O1 : 1 : 2

HF-Dip

Since by H2O2, which is used in all described cleaning steps, SiO2 is formed on the wafer,it must be removed by using HF. The duration of this process depends on the thickness ofthe oxide layer. The etching speed of 5% HF (5% HF in DI water) is about 50 nm/minat room temperature [BOG67]. The SiO2 is thereby converted into a soluble complex salt[RUG75]:

6 Clean Room 25

SiO2 + 6HF → H2SiF6 + 2H2O

Since SiO2 is strongly hydrophilic, but pure Si in contrary hydrophobic, this behavior canbe used as an indicator for a successful cleaning.

For the processing of the PNPN structure in this student laboratory always the same clean-ing procedure is used between each fabrication step. The acid mixtures and etch durationare used as following:

1. Piranha etching2. Rinsing with DI-water3. HF dip for 3 min4. Rinsing with DI-water5. RCA 1 cleaning6. Rinsing with DI-water7. HF dip for 3 min8. Rinsing with DI-water9. RCA 2 cleaning10. Rinsing with DI-water11. HF dip for 3 min12. Rinsing with DI-water

6.3 Safety instructions

The work with acids requires special attention. In direct contact with the skin they lead toburning of the skin or even eating through. Here especially the dangers of HF are described.This acid etches locally at the area of touch. It penetrates the skin very quickly andcause serious etching of the deeper skin. Here especially the binding with magnesium andcalcium ions is very critical. Without calcium the local nerves are not able to transmit anyinformation. Therefore no pain is felt at all and the symptoms may get visual hours later(Figure 6.1). This results in acute life-threatening metabolic disorder or liver and kidneyfailure. The lethal dose for humans is 70 - 140 mg/kg body weight.

Road map for first aid:

1. Emergency Service Request

2. Pay attention to self-protection (protective clothing, acid-proof gloves)

3. Move injured person from area of danger

4. Remove contaminated clothing

5. Wash/rinse affected area with a lot of water

6. Person with breathlessness to lie with upper body in higher position

6 Clean Room 26

7. Initiate resuscitation at apnea

Figure 6.1: Acid burn with HF

7 Experiment 1: Introduction into theproperties and fabrication of GCTs

The student laboratory starts with an introduction into the properties and fabrication ofGCTs which will be performed interactive. The participating students have to be preparedby having an overview about this device and its fabrication by using the chapters 1 to 6.The fundamental basics of GCTs and the fabrications steps are discussed briefly includingthe introduction into the simulation and the clean room. To have a better overview realdevices and their housing are presented to understand the device properties and especiallyits fabrication.

27

8 Experiment 2: Introduction into the devicesimulation tools

In the following the work with TCAD 8 is described. These instructions will be needed forthe device simulation.

Figure 8.1: Crosssection of the Simulated GCT

In the simulation with TCAD only a section of the whole device is simulated. This sectionincludes the used dimensions and doping concentrations is shown in Figure 8.2. The useddopants are phosphorus for the n-doping and boron for the p-doping.

8.1 Introduction into the device simulation tools

To start TCAD 8, a X-Win32 server needs to be started. The UNIX server can be foundunder Start\Progamme im ISEA\Tools\X-Win32\X-Win32.

28

8 Experiment 2: Introduction into the device simulation tools 29

TCAD is located under Start\Progamme im ISEA\Elektrotechnik\TCAD 8\GENESISe.First, create a folder with your group number in the directory: Desktop\My Computer\X:\Sim\5001_Thyristorbau_bn \IHR GRUPPENORDNER. Then start TCAD. After aloading time a folder tree can be seen, select than the created folder.

GENESISeGENESISe is the main interface to access the various subroutines. The geometric dimen-sions, connections and doping profiles are recorded in a text file using MDraw. To workwith the programs a new project must be created. Create additionally a folder and label itwith your group name. The project needs to be activated for editing. For this select it andthen click on the Activate-Button, see Figure 8.2.

Figure 8.2: Creation of a project in TCAD

MDrawTo start MDraw, open the Toolbox and drag MDraw into the left part of this window(Figure 8.3). Do the same with Dessis. Select the MDraw icon and click in the menu barEdit\input\preferences. Change the setting "Excecution Mode" in "‘Start in batch mode".Run MDraw by clicking in the menu bar Edit\input\Boundary. If the Unix Sever is notactive, then MDraw can not be started. If the server runs a window will appear asking for aconnection to a host, in this case select "Immer so verfahren and click Ja". Afterwards thegraphical interface of MDraw will be started. With MDraw the two-dimensional side profilewill be created and then converted into three-dimensional with a depth of 1 µm. It can not


simulate rotation symmetric components. On the left side there is a bar which provides thedifferent tools. In the downer part there are tools to change the graphical appearance. Hereoptions are presented with which various profile levels or an auxiliary grid can be shownor hide. The two lowest points Doping and Boundary offer the possibility to distinguishbetween the doping/diffusion tools and the geometric tools.

Figure 8.3: To start MDraw it has to be introduced into the simulated process

BoundaryThe geometric dimensions will be developed graphically and then stored in a text file. Fora very precise description of the dimensions there is in the tool bar the button "exactCoordinates". By this the exact coordinates of a point can be typed in. With the helpof "Add Rectangle", "Add Point" and "Move Point", the device can be represented as inFigure 8.4. In Boundary mode also the connection points like anode, cathode and basecan be defined. To set a contact it must be first defined in the toolbar in the window"Contacts" and then selected. With "Set/Unset Contacts" the contact point is set to thedefined place.

DopingThe assignment of doping concentrations to the device can be performed in the "Dopingmode". In Table 8.1 the individual functions of the tools are listed up.

SubstrateFirst the substrate must be doped using the "Add Constant P". tool. For this the completearea of the side profile has to be selected. After this a window like in Figure 8.5 appears.


Gate -175 µm

Kathode

Anode- 325 µm

10µm

515 µm

205 µm

Figure 8.4: The shape and dimensions of the structure to be created

Tool EffectAdd Constant P. Generates homogenous dopingAdd Analytic P. To position the deposited impuritiesAdd Refinement Here the grid size will be determined

Build Mesh Creates the doping profile and shows it a graphic

Table 8.1: Tool overview in Doping-mode.

The donor concentration of the base material is around 1 · 1014cm−3. In the menu barunder View\List of Profiles the properties can be seen and edited subsequently. Also thecoordinates need to be corrected.

Gate, anode and cathodeSince the doping profiles of anode, cathode and gate are defined by high-temperature pro-cesses, they have not homogeneous concentrations (see Chapter 3). Create with the com-mand Add Analytic P. first the anode contact. Pull the vector arrow over anode contact.Correct the settings if necessary in the appearing window. Take from Figure 8.1 the dopingdepths and concentrations. Add after that the cathode and gate area (see chapter 2.5).After the doping profiles have been created, a grid has to be defined for each region. Usefor this the command "Add Refinement". Under View\List of Refinements, it is possible tocarry out subsequent changes. You can change the duration and the accuracy of the FEMsimulation. The smaller/finer the grid is selected, the longer the calculation takes and alsomore precise the results are.

Build MeshWith the button Build Mesh the grid is generated and displayed. Doping concentrationsare associated with different colors. Under "Functions" in the menu bar different views


Figure 8.5: Setting of the substrate background carrier concentration

are available. In addition further display options are in the toolbar. Figure 8.1 shows thefinished device in BoronActiveConcentration.

8.1.1 Device Simulation

By using the basics of the previous chapters (5 and 8.2) set the spatial points and theimpurity concentration of the thyristor. In order to understand the electrical behavior atheoretical electric circuit will be established in Dessis and simulated with DUT (DeviceUnder Test). Basic functions of Matlab are used for a better evaluation of the simulationresults in the second part of the experiment.

8.1.1.1 Structure of the network

Dessis offers the Mixed-Mode. There it is possible to place the physical semiconductor devicesimulation on FEM-basis into a circuit of ideal devices, which are defined by analyticalequations. In Figure 8.6 the power supply on the left hand side reflects the low voltagesource. When DUT is running, the current of the power source flows directly through it.While switching it off the current commutated to the diode D and continues to chargefirst the capacitor CCl which is preloaded by nominal voltage with a constant current andlinear voltage increase according to Ic = C · dUc

dt. The capacity was set to 24 nF. When

the capacitor voltage reaches the voltage Vblock, the diode DCl starts to conduct. Since theinternal resistance of the ideal voltage source, the voltage will not rise further. The voltagesource has to be adjusted to the desired maximum voltage magnification. Here a Vblock


value of 1.2 kV is used. Before the actual switching procedure and for a proper working thecapacitor must be preloaded (here: 1 kV). This is done by turning on the current sourcefirst (here: 400 A) while the GCT is switched off. If the voltage source is also turned on,the capacitor voltage starts rising and after charging the capacitor the GCT is turned on.The capacitor voltage remains constant now and after settling all levels (around 20 µs),the actual turn off sequence can be carried out. The contacting of the gate is as shown inFigure 8.6 with a 2 Ohm resistance RG to limit the current during power up. When turningon the other hand, this resistance is bridged through the diode DG, because then the voltagesource VG is switched to -20 V and the current direction points out of the gate.

Figure 8.6: External circuit of the DUT during the simulation

Task 1. To characterize the device, build up the virtual test bench shown in Figure 8.6. Inthe file "des.cmd" there is the section "Solve" in which the static, transient and quasitran-sient operations can be solved. In the following the necessary commands are presented.

Most important commands are summarized here. They are sufficient to meet the tasks. Inaddition there is a manual under Start\Progamme im ISEA\Elektrotechnik\TCAD 8\OnlineManuals Manuals available.

Set (n0=0): This forces the potential of a node n0 to 0 V.

unset (n0): Cancels the Set command.

Vsource_pset V_0 (n1 gr) pwl=(0 0): Creates an ideal voltage source with thename of V_O from input node n1 to the grounding point gr. The parameters pwl will bedescribed in the next.

Isource_pset I_0 (gr n1) pwl=(0 0): Produces an ideal current source with thename I_0 from input node grto the grounding point n1. The parameters pwl will bedescribed in the next.


pwl = (0 01e-6 5002e-6 10003e-6 5004e-6 0)

Table 8.2: Example Code

Resistor_pset R (n2 n3) resistance=1: Creates resistance R with value of 1 Ωbetween points n2 and n3

Diode_pset D1 (n1 n2): Creates diode D1 with the anode n1 and the cathode n2.

Capacitor_pset C (n1 n2) capacitance=1e-6: Creates ideal capacitor C with 1µFbetween nodes n1 and n2.

# Comments: Include line comments

Transient ( InitialTime=0 FinalTime=1000 InitialStep=10MinStep=1MaxStep=5) statement: Since a transient (time-dependent) simulation is performed, the calculationmust be based on cycle time.

Figure 8.7: Generated curve with code from Table 8.2

With the parameter pwl (piece-wise-linear) of the voltage and current source it is possibleto define time-dependent constant voltages/currents. Referring to a voltage source theexample code in Table 8.2 generates the curve shown in Figure 8.7. For clarity, as shownin the example Table 8.1, the times (the first parameter) and the voltages/currents shouldbe below each other. The first value indicates the time and the "e-6" for the order of


magnitude "·10−6" (=µs). The second value gives the voltage in volts or the current inamperes, depending on which source is implemented.

Tasks

1. The thyristor should have an area of 1 cm2. Calculate the "Area Factor" and paste itinto the "des.cmd" file.

2. What are the tasks of the various devices of the test bench (the capacitor CCL andthe diode DCL were introduced on basis of numerical convergence problems, so theyare negligible)?

3. How should be the time characteristics of the source in order to get a useful measure-ment of the device?

4. Program the network according Figure 8.6! The nodes and names of the componentsare defined and should be used.

5. Write a reasonable Solve -section!

6. Start the simulation!

9 Experiment 3: Device and Processsimulation

9.1 Inspect, Tecplot

InspectInspect can be find in the main interface of GENESISe symbolized by an oscilloscope. Whilethe simulation data is recorded and therefore already available, the data can be accessedthrough Family Editor. In Figure 9.1 the main window of Family Editor is shown. On theright side, the various stages of the simulation are shown and on the left side the results of thesimulation. With the left mouse button the icons can be dragged into the programs Inspectand Tecplot. These will then run with the loaded data. Inspect plots the data. For thisvariables can be addressed to the X-axis and to the Y-axis. The operation is intuitive. Moreinformation can be found under Start\Progamme im ISEA\Elektrotechnik\TCAD 8\OnlineManuals - Inspect.

TecplotTo work with Tecplot the command Plot ( Time = ( 400e-6)) has to be added in the Solvesection of the Dessis-file for a plot of all points in the Plot section at 400 µs. In Tecplotthree dimensional data can be displayed, e.g. E-fields or thermodynamic stresses.

Tasks

Create by using Matlab, Tecplot and Inspect the following graphs:

1. Current and voltage behavior during switching on/off (Inspect)

2. Energy losses during switching on/off (Inspect)

3. Electric field strengths in the device, at constant current (Tecplot)

4. Recombination effects/lifetime of charge carriers (Inspect)

5. Carrier concentrations as function of the current (Inspect)

6. Current density in the device (Tecplot)

36

9 Experiment 3: Device and Process simulation 37

Figure 9.1: Main window of Family Editor

9.2 Process simulation

GENSESISe offers the possibility to simulate furnace processes and to create new furnaceprocesses by using the simulation results. The goal of this experiment is not to create acomplete program but to give a brief insight into the principles of the program and showhow furnace processes will be developed.

Ligament and Dios Open in GENESISe the program folder Ofenprozesssimulation_bn.To see the progress in Ligament add in ISE Tool Flow Editor the program Ligament. Tostart click on Edit\Input\Commands.

Ligament provides a clear arranged graphical interface to create a script, which includesfurnace process operations. This script is passed to Dios, which simulates the processes. InFigure 9.2 the graphical user interface of Ligament is shown. For comparison: In Dessis the


script must be written itself, otherwise the operation of the simulation programs is the same.It is also possible to write the script directly in Dios, or rewrite without using ligament.

Figure 9.2: Furnace process simulation in Ligament

TecplotTecplot is a visualization program which illustrates additionally the data obtained by thesimulation. Depending on the content of the loaded input data, diffusion profiles, potentialprofiles, field strength curves, etc. can be shown as cross sections of the device. To open,click in the interface of Genesis on Tecplot and to download the simulated results from Diosclick on Datei\Importieren. Select the DF-ISE Loader and load the files n1_dio.dat.gr andn1_dio.grd.gr. Figure 9.3 shows simulated doping profile of the device in two dimensions.The doping level is represented by the color. By a cut at any X position of the devicethe doping profile is shown as a graph. It is necessary that the X-position is within thedevice, in this case between 0 µm and 10 µm. For the cut, go to Tools \ISE TCAD Tools.Under Utilities\x-Normal Cut the X position for the cut has to be given. In addition, underVariables the types of impurities can be changed.


Figure 9.3: Doping profile simulated by Tecplot.

Tasks

1. Calculate with the help of Ligament and Dios the diffusion times t1473k at 1200 °Cto achieve, at the desired depth of the gate. Compare t1473k with diffusion times at1000 °C and 1350 °C.

2. What problems occur at 1350 °C?

10 Experiment 4: Clean room and safetyintroductions, start of thyristorfabrication; substrate preparation anddoping

The Central Laboratory is located in the Otto-Blumenthal Str. 3 next to the Walter Schot-tky Haus. Here all the experimental work will be done. First there will be an introductioninto the safety and behavior in a clean room. At the beginning you will receive a batch card.This is a kind of schedule including all fabrication steps. In this card the process status ofeach step has to be documented.

For different deposition/diffusion processes (Chapter 3.1 and 4) there are specific boats used.Table 10.1 shows for which process which boat is used:

identifier boot name process nameWQE03312204-001 BN - HT bn-depo.prz

Reaktiv.przWQE03312204-002 phosphorus ph-depo.przWQE03312204-004 BN-975 depo_975.prz

LTO&DIFF.przLTO.prz

Table 10.1: List of available boats for the different diffusions processes.

40

10 Experiment 4: Clean room and safety introductions, start of thyristor fabrication;substrate preparation and doping 41

In Figure 10.1 the junction depths are shown as a function of the deposition temperatures.There have been various measurements performed and then extrapolated with Matlab. Thetemperature was varied, therefore the diffusion process for all deposition temperatures isthe same.

20

25

30

35

40

45

50

55

60

800 900 1000 1100 1200 1300Temperature in °C

Junc

tion

Dep

th in

µm

MeasuredModelPolynomisch (Measured)

Figure 10.1: Junction depth as function of deposition temperature

The graph in Figure 10.2 shows the boron concentration of the anode as a function of thedeposition temperature. It was measured after the diffusion, without changing the diffusionprocess. This graph results from the measurement of the sheet resistance and from thedirect comparison with the Irvine curves.

RemarkTake into account that the diffusion process is variable. Furthermore, it can be assumedthat the surface concentration is independent of the diffusion process.

10 Experiment 4: Clean room and safety introductions, start of thyristor fabrication;substrate preparation and doping 42

1,00E+17

1,00E+18

1,00E+19

1,00E+20

800 850 900 950 1000 1050 1100 1150 1200 1250 1300Deposition Temperature in °C

Surf

ace

Con

cent

ratio

n in

cm

^-3

Figure 10.2: Surface concentration as function of deposition temperature after diffusion

Tasks:

1. Perform a standard cleaning according to the batch card.

2. Determine from the Figures 10.1 and 10.1 the required deposition temperature. Con-sider the remark!

3. Perform the gate and anode deposition.

11 Experiment 5: Four-point, diffusion depth,oxide layer growth and metallization

At least one of the doped samples needs to be characterized before continuing with thefabrication. It is import to measure the sheet resistance of the doped layer and to verify ifthe doping depth is in a sufficient range.

The measurement of the sheet resistance is done by the method of the four-terminal sensingaccording Chapter 3.7. For the determination of the doping depth the wafer has to be cutfirst into pieces. The sample that will be measured is then fixed on a customized mount(see Figure 11.1, left). This mount holds the sample surface 3-4° tilted and is placed in thepolishing tool shown in the right image of Figure 11.1.

Figure 11.1: Customized sample mount with sample (left) and polishing tool (right).

The oxide layer (insulating layer) is very important to separate the gate and the anode area.The oxide layer is deposited on the whole substrate (see Figure 4.3, starting at number 4).Afterwards it is patterned that and covered completely with aluminum. Because it take toolong if the whole work is done in here, the etching and cleaning step between the oxide layerand the metallization is not done here.

Tasks

1. Measure the sheet resistance of the gate of one wafer and determine the doping level!

2. Perform a standard cleaning for the remaining wafer.

3. What happens to the wafer if they have not been processed for a longer time?

43

11 Experiment 5: Four-point, diffusion depth, oxide layer growth and metallization 44

4. Dice a wafer and wafer dummy into equal squares!

5. Prepare the pieces for the polishing process!

6. Grind the pieces of the wafer/dummy wafer!

7. Treat the polished surfaces with HF under UV light! What change occurs on polishedsurface?

8. Describe the principles of the oxide layer growth!

12 Experiment 6: Lithography, etching andmeasurement of the etch profile

In order to reach each contact area of the device, some material needs to be removed. Forthe gate contact it is necessary to get direct access to the p-type doped area. In chapter 3.2and 3.3 the patterning of a wafer is described. Subject of this experiments is the fabricationof the contact area of the gate and the subsequent verification.

1. Prepare the substrates by chemical cleaning!

2. Describe how to achieve a pattern on a wafer!

3. Create the pattern based on a mask onto the wafer (coating, photolithography, plasmaetching (pumpdown takes long?))!

4. Measure the etched profile (tool for measurement will be introduced). (Tencor)

5. Create you own mask and verify it according to instructions, that will be given.

45

13 Experiment 7: Visit Infineon, lastexperimental steps

To have a better insight into the industrial production of GCTs and to process steps notavailable at the institute, an industrial production site will be visited.

46

14 Experiment 8: Device measurement

To have a better insight into the industrial production of GCTs and to have access to processsteps not available at the institute, an industrial production site will be visited.

1. Record with an oscilloscope the characteristic of the thyristor with a maximum currentof 20 A and a maximum voltage of 100 V.

2. What are the differences in comparison to the simulated results?

47

15 Experiment 9: Presentation

This student laboratory will be finished with a presentation prepared by each group. Thegroups will be informed about topic of the presentation.

48

List of Figures

1.1 Applications fields of power devices [ISEA] . . . . . . . . . . . . . . . . . . . 1

2.1 PNPN structure of a thyristor [ISEA] . . . . . . . . . . . . . . . . . . . . . . 22.2 Space charge regions with the corresponding I-V-characteristics for a) reverse,

b) blocking, c) conducting [ISEA] . . . . . . . . . . . . . . . . . . . . . . . . 32.3 Switching of the thyristor at sufficiently high reverse current in the forward

mode [ISEA] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.4 The four layer structure of the thyristor replaced by two transistors. Right

image shows the equivalent circuit diagram of a thyristor as a pair of tightlycoupled bipolar junction transistors.[ISEA] . . . . . . . . . . . . . . . . . . . 6

2.5 Structure of four-layer sequence of a thyristor including the contacts . . . . . 8

3.1 Diffusion behavior for infinite (left) and finite (right) dopant source [Zim] . . 113.2 Photomask for thyristor process (right) and difference of positive and negative

resist (right) [Zim] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.3 Etching process by SF6 and O2 [Zim] . . . . . . . . . . . . . . . . . . . . . . 133.4 Principle of the four-terminal sensing [Zim] . . . . . . . . . . . . . . . . . . . 153.5 Irvine curves for different dopants and doping profiles . . . . . . . . . . . . . 17

4.1 Fully loaded wafer boat without source discs (left) and schematic side viewof wafer boat with Si-wafers and source disks (middle and right) . . . . . . . 18

4.2 P-N junction (left) and four-layer structure (right) after diffusion process . . 194.3 Fabrication steps of a GCT [Zim] . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 Acid burn with HF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.1 Crosssection of the Simulated GCT . . . . . . . . . . . . . . . . . . . . . . . 288.2 Creation of a project in TCAD . . . . . . . . . . . . . . . . . . . . . . . . . 298.3 To start MDraw it has to be introduced into the simulated process . . . . . . 308.4 The shape and dimensions of the structure to be created . . . . . . . . . . . 318.5 Setting of the substrate background carrier concentration . . . . . . . . . . . 328.6 External circuit of the DUT during the simulation . . . . . . . . . . . . . . . 338.7 Generated curve with code from Table 8.2 . . . . . . . . . . . . . . . . . . . 34

9.1 Main window of Family Editor . . . . . . . . . . . . . . . . . . . . . . . . . . 379.2 Furnace process simulation in Ligament . . . . . . . . . . . . . . . . . . . . . 389.3 Doping profile simulated by Tecplot. . . . . . . . . . . . . . . . . . . . . . . 39

10.1 Junction depth as function of deposition temperature . . . . . . . . . . . . . 41

49

List of Figures 50

10.2 Surface concentration as function of deposition temperature after diffusion . 42

11.1 Customized sample mount with sample (left) and polishing tool (right). . . . 43

List of Tables

3.1 Chemical reaction during the etching process . . . . . . . . . . . . . . . . . . 13

8.1 Tool overview in Doping-mode. . . . . . . . . . . . . . . . . . . . . . . . . . 318.2 Example Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.1 List of available boats for the different diffusions processes. . . . . . . . . . . 40

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Bibliography

[MiCh1] MicroChemicals: Lithographie, Theorie und Anwendung von Fotolacken,Entwicklern, Ätzchemikalien und Lösemitteln., MicroChemicals GMBH, Ulm,Deutschland, 2007

[GUVV] Bayrische Gemeindenfallversicherungsverband Höchste Vorsicht beimUmgang mit Flusssäure!, http : //www.bayerguvv.de/download/uva10117.pdf

[Vollmer] Dr. Michael Vollmer: Flusssäure - Fluorwasserstoff!,http : //www1.tu− darmstadt.de/pvw/deziv/a/info/vollmer.ppt

[MiCh2] MicroChemicals: Substratreinigung und Haftvermittlung,http : //www.microchemicals.com/technische_infos/substrat_reinigung_haftung_fotolack.pdf

[Lutz] Josef Lutz: Halbleiter- Leistungsbauelemente, Springer Verlag, Berlin 2006,Deutschland

[ISEA] ISEA: Bauelemente Nachdruck zum Vorlesungsskript aus dem Sommersemester2005, ISEA, Aachen, Juni 2007

[Zim] Jella Zimmermann: Design, Simulation und Prozessaufbau einerDUAL-GCT Struktur, ISEA Diplomarbeit, Aachen, März 2009

[Bra] Michael Bragard: Entwurf und Realisierung eines DUAL-GCTHochleistunghalbleiters, ISEA, Aachen, Oktober 2006

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