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ISE 11 In-Depth Tutorial www.xilinx.com

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.

THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHERWARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANYWARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTYRIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTALDAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in theUnited States and other countries. All other trademarks are the property of their respective owners.

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Preface

About This Tutorial

About the In-Depth Tutorial

This tutorial gives a description of the features an d add itions to Xilinx ISE 11. The

primary focus of this tutorial is to show the relationship am ong th e design entry tools,

Xilinx and third-party tools, and the design implementation tools.

This guide is a learning tool for designers w ho are unfamiliar with th e featu res of the ISE

software or those w anting to refresh their skills and know ledge.

You m ay choose to follow one of the th ree tutorial flows available in this documen t. For

information abou t the tutor ial flows, see Tutorial Flows.

Tutorial Contents

This guide covers the following top ics.

Chapter 1, Over view of ISE, introduces you to the ISE primary u ser interface,

Project Navigator, and th e synthesis tools available for your d esign.

Chapter 2, H DL-Based Design, guides you through a typical HDL-based d esign

procedure using a design of a runn ers stopw atch. This chapter also shows h ow to useISE accessories su ch as CORE Generator, and ISE Text Editor.

Chapter 3, Schematic-Based Design, explains m any different facets of a schem atic-

based ISE design flow u sing a design of a runn er s stopw atch. This chapter also

show s how to u se ISE accessories such as CORE Generator, and ISE Text Editor.

Chapter 4, Behav ioral Simu lation, explains h ow to simulate a d esign before design

implementation to v erify that th e logic that you have created is correct.

Chapter 5, Design Implementation, describes how to Translate, Map , Place, Route,

and generate a Bit file for designs.

Chapter 6, Timing Simu lation, explains how to perform a timing simu lation u sing

the block and routing d elay information from th e routed design to give an accurate

assessment of the behavior of the circuit un der w orst-case conditions.

Chapter 7, iMPACT Tutorial explains how to program a d evice with a new ly

created design u sing the IMPACT configurat ion tool.

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Preface: About This TutorialR

Tutorial Flows

This docum ent contains three tu torial flows. In this section, the three tutor ial flows are

outlined and briefly d escribed, in order to h elp you determine w hich sequence of chapters

applies to your needs. The tutorial flows include:

HD L Design Flow

Schematic Design Flow

Implementation-only Flow

HDL Design Flow

The HD L Design flow is as follows:

Chapter 2, H DL-Based Design

Chapter 4, Behavioral Simu lation

Note that although behavioral simulation is optional, it is strongly recommended in

this tu torial flow.

Chapter 5, Design Implementation

Chapter 6, Timing Simu lation

Note that although timing simulation is optional, it is strongly recommen ded in this

tutor ial flow.

Chapter 7, iMPACT Tutorial

Schematic Design Flow

The Schem atic Design flow is as follows:

Chapter 3, Schem atic-Based Design

Chapter 4, Behavioral Simu lation

Note that although behavioral simulation is optional, it is strongly recommended inthis tu torial flow.


Chapter 6,Timing Simu lation

Note that although timing simulation is optional, it is strongly recommen ded .


Implementation-only Flow

The Implemen tation-only flow is as follow s:


Chapter 6, Timing Simu lationNote that although timing simulation is optional, it is strongly recommen ded in this

tutor ial flow.


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Additional Resources

To find ad ditional d ocumen tation, see the Xilinx w ebsite at:

http:/ / ww w.xilinx.com/ literature.

To search the Answ er Database of silicon, software, and IP questions and answ ers, or to

create a technical supp ort WebCase, see the Xilinx website at:

http:/ / www.xilinx.com/ support.
http://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=xilinx+literaturehttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=supporthttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=supporthttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=supporthttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=xilinx+literature

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Preface: About This Tutorial

About the In-Depth Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Tutorial Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Tutorial Flow s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4HDL Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Schematic Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Implementation-only Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Addi tional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 1: Overview of ISE

Overview of ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Project N avigator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Design Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Sources View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Processes View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Files Pan el . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Libraries Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Console Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Errors Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Warnings Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Error Navigation to Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Error Navigation to Answ er Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Design Summary & Report Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Using Project Revision Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17ISE Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Making a Copy of a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Using th e Project Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Using P roject Archives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Creating an Archive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Restoring an Archive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Chapter 2: HDL-Based Design

Overview of HD L-Based Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Required Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Optional Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

VHDL or Verilog? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Installing the Tutorial Pr oject Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Starting the ISE Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Creating a N ew Pro ject . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Creating a New Project: Using the New Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . 21

Stopping the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

D esign D escription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table of Contents

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Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

D esign Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Adding Source Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Checking the Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Correcting HDL Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Creating an HDL-Based Mod ule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Using the N ew Source Wizard an d ISE Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Using the Language Temp lates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Add ing a Langua ge Template to Your File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Creating a CORE Generator Modu le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Creating a CORE Generator Mod ule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Instantiating the CORE Generator Modu le in the HDL Code. . . . . . . . . . . . . . . . . . . . . 34

Creating a DCM Mod ule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Using the Clocking Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Instantiating the dcm1 Macro - VHDL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Instantiating the dcm1 Macro - Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Synthesizing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Synthesizing the Design using XST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Entering Synthesis Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Synthesizing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

The RTL / Technology Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Synthesizing the Design u sing Synplify/ Synp lify Pro . . . . . . . . . . . . . . . . . . . . . . . . . 43

Examining Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Synthesizing the Design Using Precision Synth esis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Entering Synthesis Options th rough ISE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

The RTL/ Technology Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Chapter 3: Schematic-Based Design

Overview of Schematic-Based Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Required Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Installing the Tutorial Pr oject Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Starting the ISE Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Creating a N ew Pro ject . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Creating a New Project: Using New Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Stopping the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

D esign D escription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

D esign Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Opening the Schematic File in th e Xilinx Schematic Editor . . . . . . . . . . . . . . . . . . . . . . 53

Manipulating the Window View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Creating a Schematic-Based Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Defining the tim e_cnt Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Adding I/ O Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Add ing Schematic Comp onents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Correcting Mistakes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Drawing Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Add ing Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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Add ing Bus Taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Adding Net Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Checking the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Saving the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Creating and Placing the time_cnt Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Creating the time_cnt symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Placing the time_cnt Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Creating a CORE Generator Modu le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Creating a CORE Generator Mod ule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Creating a DCM Mod ule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Using the Clocking Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Creating th e d cm1 Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Creating an HDL-Based Mod ule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Using the N ew Source Wizard an d ISE Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Using the Language Temp lates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Add ing a Langua ge Template to Your File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Creating Schem atic Sym bols for HDL modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Placing the statmach, timer_preset, dcm1 and debounce Symbols . . . . . . . . . . . . . . . 72

Changing Instance Nam es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Hierarchy Push/ Pop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Specifying Device Inp uts/ Outp uts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Adding Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Adding I/ O Markers and Net Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Assigning Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Completing the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Chapter 4: Behavioral Simulation

Overview of Behavioral Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

ModelSim Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79ModelSim PE and SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

ModelSim Xilinx Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

ISim Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Required Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Design Files (VHDL, Verilog, or Schem atic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Test Bench File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Xilinx Simu lation Librar ies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Xilinx Simulation Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Updating the Xilinx Simulation Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Mapping Simulation Libraries in the Modelsim.ini File . . . . . . . . . . . . . . . . . . . . . . . . . 81

Adding an HD L Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Adding Tutor ial Test Bench File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

VHDL Simu lation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Verilog Simu lation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Behavioral Simulation Using ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Locating th e Simu lation Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Specifying Simu lation Prop erties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Add ing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Adding Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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Saving the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Behavioral Simulation Using ISim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Locating th e Simu lation Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Specifying Simu lation Prop erties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Add ing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Chapter 5: Design Implementation

Overview of D esign Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Continuing from Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Starting from Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Specifying Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Creating Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Translating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Using the Constraints Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Assigning I/O Locations Using PlanAhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Mapping the D esign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Using Timing Analysis to Evaluate Block De lays After Mapping . . . . . . . . . . . . 109Estima ting Timing Goals with the 50/ 50 Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Report Paths in Timing Constraints Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Placing and Routing the D esign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Using FPGA Editor to Verify the Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Evaluating Post-Layout Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114Viewing th e Post-Place & Route Static Timing Report . . . . . . . . . . . . . . . . . . . . . . . . . 114

Analyzing the Design using PlanAhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Creating Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Creating a PROM File with iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Command Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Chapter 6: Timing Simulation

Overview of Timing Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Required Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Required Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Specifying a Simu lator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Timing Simulation Using M odelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Specifying Simu lation Process Prop erties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Add ing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Adding Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Saving the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Timing Simulation Using Xilinx ISim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Specifying Simu lation Process Prop erties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

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Performing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Add ing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Viewing Full Signal Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Rerunning Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Analyzing the Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Chapter 7: iMPACT TutorialD evice Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

D ownload Cable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Parallel Cable IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Platform Cable USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

MultiPRO Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Configuration Mode Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Generating th e Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Connecting the Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Starting the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Opening iMPACT from Project Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Opening iMPACT stand-alone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Creating a iMPACT New Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Using Boundary Scan Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Specifying Boun dar y Scan Configur ation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Assigning Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Saving the Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Editing Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Performing Bound ary Scan Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Trouble shooting Boundary Scan Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144Verifying Cable Conn ection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Verifying Chain Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Creating an SVF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Setting up Boundary Scan Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

JTAG chain setu p for SVF generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Manu al JTAG chain setup for SVF generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Writing to th e SVF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Stop Writing to the SVF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Playing back th e SVF or XSVF file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Other Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Slave Serial Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

SelectMAP Configur ation Mod e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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Chapter 1

Overview of ISE

This chap ter includes th e following sections:

Overv iew o f ISE

Using Project Revision Man agemen t Features

Overview of ISEISE controls all aspects of the d esign flow. Throu gh the P roject Navigat or interface, you can

access all of the d esign entry and design imp lementation tools. You can also access the files

and docum ents associated with you r p roject.

Project Navigator Interface

The Project Navigator Interface, by defau lt, is divided in to four pan el subwindow s, as seen

in Figure 1-1. On th e top left is the Design, Files and Libraries pan els which include d isplay

and access to the sou rce files in th e project, as well as access to run ning processes for the

currently selected source. At the bottom of the Project Navigator is the Con sole, Errors and

Warnings pan els which display statu s messages, errors, and wa rnings. To the right is a

multi-document interface (MDI) window referred to as the Workspace. It enables you toview d esign reports, text files, schematics, and simu lation waveform s. Each wind ow m ay

be resized, u nd ocked from Project N avigator, moved to a n ew location within th e main

Project Navigator w indow, tiled, layered, or closed. Panels may be opened or closed by

using theView -> Panels -> * men u selections. The default layout can always be

restored by selecting View > Restore Default Layout. These wind ows are d iscussed in

more d etail in the following sections.

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Design Panel

Sources View

The Sources view displays the project name, the target device, and user documents anddesign source files associated w ith the selected Design View. The Design View (Sources

for) drop-down list at the top of the Sources tab allows you to view on ly those source files

associated w ith the selected Design View, such as Synth esis/ Implem entation or

Simulation.

Each file in a Design View has an associated icon. The icon ind icates the file type (H DL file,

schematic, core, or text file, for examp le). For a com plete list of possible source typ es and

Figure 1-1: Project Navigator

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Overview of ISER

their associated icons, see the ISE Help. Select Help > ISE Help Contents, select the

Index tab and search for Source file types.

If a file contains lower levels of hierarchy, the icon h as a + to th e left of the nam e. You can

expand the hierarchy by clicking th e +. You can open a file for editing by d oub le-clicking

on the filenam e.

Processes View

The Processes view is context sensitive and it changes based up on the source type selected

in the Sour ces tab and the Top-Level Source in your project. From the Processes tab, you

can run the functions necessary to define, run and analyze your design. The Processes tab

prov ides access to the following functions:

Des ign Summary/Reports

Provides access to design reports, messages, and sum mar y of results data . Message

filtering can also be performed .

Design Utilities

Provides access to sym bol generation, instantiation templates, viewing comm and line

history, and simu lation library comp ilation.

User Constraints

Provides access to editing location and timing constraints.

Synthesis

Provides access to Check Syntax, Synthesis, View RTL or Technology Schematic, and

synth esis reports. Available processes vary dep end ing on the synth esis tools you use.

Implement Design

Provides access to imp lementation tools, and p ost-imp lementation an alysis tools.

Generate Programming File

Provides access to bitstream gen eration.

Configure Target D evice

Provides access to configuration tools for creating p rogram ming files and

programm ing the device.

The Processes tab incorporates dep end ency managemen t technology. The tools keep track

of which processes have been run and wh ich p rocesses need to be run. Grap hical status

indicators d isplay the state of the flow at an y given time. When you select a process in the

flow, the software automatically runs the processes necessary to get to the desired step . For

example, when you run the Implement Design process, Project N avigator also runs the

Synthesis process because implementation is dependent on up-to-date synthesis results.

To view a runn ing log of comman d line argum ents used on the current p roject, expand

Design Utilities and select View Command Line Log File. See the Comman d Line

Implementation section ofChapter 5, Design Implementationfor further details.

Files Panel

The Files panel p rovides a flat sortable list of all the sou rce files in the project. Files can be

sorted by any of the colum ns in the view. Properties for each file can be viewed and

mod ified by right-clicking on the file and selecting Source Properties.

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Libraries Panel

The Libraries tab allows you to m anage HDL libraries and their associated H DL source

files. You can create, view, and edit libraries an d their associated sou rces.

Console Panel

The Console provides all standa rd ou tpu t from processes run from Project Navigator. It

disp lays errors, warn ings, and information m essages. Errors are signified by a red (X) next

to the message, wh ile warnings have a yellow exclamation m ark (!).

Errors Panel

Displays only error m essages. Other console messages are filtered out.

Warnings Panel

Displays only warning messages. Other console messages are filtered ou t.

Error Navigation to Source

You can n avigate from a synth esis error or w arning message in the Console, Errors or

Warnings pa nel to th e location of the error in a source HDL file. To d o so, select the error or

warning m essage, right-click the mouse, and selectGo to Source from the right-click

menu .The H DL source file opens an d th e cursor moves to the line with the error.

Error Navigation to Answer Record

You can n avigate from an error or wa rning m essage in the Console, Errors or Warnings

panel to relevant Answer Records on the http:/ / www.xilinx.com/ support website. To

nav igate to the Answ er Record (s), select the error or wa rning m essage, right-click themouse, and select Go to Answer Record from the right-click menu . The default web

browser opens and displays all Answer Records ap plicable to this message.

Workspace

The Workspace is wh ere design ed itors, viewers, and an alysis tools will open. These

include ISE Text Editor, Schematic Editor, Timing Constraint Editor, Design Summ ary &

Report Viewer, RTL and Technology Viewers, and Timing Analyzer.

Other tools such as PlanAh ead for I/ O plann ing and floorplanning, ISE Simulator (ISim),

3rd par ty Text Editors, XPow er Analyzer, and iMPACT open in separat e wind ows outside

the main Project Navigator environment w hen invoked.

Design Summary & Report Viewer

The Design Sum mar y prov ides a sum mar y of key design data , as well as access to all of the

messages and d etailed reports from the synthesis and imp lementation tools. The sum mary

lists high-level informa tion abou t your project, includ ing overview information, a d evice

utilization sum mary, performan ce data gath ered from the Place & Route (PAR) report,

constraints information, and summ ary information from all reports w ith links to the
http://www.xilinx.com/supporthttp://www.xilinx.com/support

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Using Project Revision Management FeaturesR

individ ua l repor ts. Messaging features such as message filtering, tagging, and incremen tal

messaging are also available from t his view.

Using Project Revision Management Features

ISE Project File

The ISE project file (.xise extension ) is an XML file tha t conta ins all sou rce-relevant data

for the p roject as follows:

ISE software version information

List of sour ce files contained in the p roject

Source settings, including design and process properties

The ISE project file d oes not contain the following:

Process status information

Command history

Constraints d ata

Note: A .gise and .ise file also exist, which contain generated data, such as process status. You

should not need to directly interact with these file.

The ISE project file includ es the following characteristics, which are compatible with

source control environments:

Contains all of the necessary sou rce settings an d inp ut d ata for the project.

Can be open ed in Project Nav igator in a read-only state.

Only u pd ated or m od ified if a source-level chan ge is mad e to the project. Can be kep t in a d irectory separate from the generated ou tpu t d irectory (working

directory).

Note: A sourcelevel change is a change to a property or the addition or removal of a source file.

Changes to the contents of a source file or changes to the state of an implementation run are not

considered source-level changes and do not result in an update to the project file.

Making a Copy of a Project

You can create a cop y of a p roject, Project > Copy Project, to experimen t with d ifferent

source options and implementations. Depend ing on your needs, the d esign source files for

the copied p roject and th eir location can vary a s follows:

Design sou rce files can be left in th eir existing location, and the copied project

then p oints to these files.

Design source files, includ ing generated files, can be copied and p laced in a

specified directory.

Design sou rce files, exclud ing gener ated files, can be copied and placed in a

specified directory.

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Preface:R

Using the Project Browser

The Project Browser, accessible by selecting Project > Project Browser, provides a

convenient w ay to compare, view, and open p rojects as follows:

Comp are key characteristics between m ultiple projects.

View Design Sum mar y and Reports for a selected project before open ing the full

project.

Open a selected project in the current Project Navigator session.

Open a selected p roject in a new Project Navigator session.

Using Project Archives

You can also archive th e entire p roject into a sing le compressed file. This allows for easier

transfer over email and stor age of num erous p rojects in a limited space.

Creating an Archive

To create an archive:

1. Select Project > Archive.

2. In the Create Zip Archive dialog box, enter the archive name and location.

Note: The archive contains all of the files in the project directory along with project settings. Remote

sources are included in the archive under a folder named remote_sources. For more information, see

the ISE Help.

Restoring an Archive

You cannot restore an a rchived file directly into Project N avigator. The com pressed file can

be extracted with any ZIP u tility and you can then op en the extracted file in Project

Navigator.

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R

Chapter 2

HDL-Based Design

This chap ter includes th e following sections:

Over view of HDL-Based Design

Getting Started

Design Description

Design Entry

Synthesizing the Design

Overview of HDL-Based Design

This chapter guides you through a typical HDL-based d esign p rocedu re using a design of

a run ner s stopwatch. The design example used in this tutorial demonstrates many d evice

features, software features, and d esign flow p ractices you can app ly to your own design.

This design targets a Spartan -3A device; how ever, all of the pr inciples and flows tau ght

are ap plicable to any Xilinx dev ice family, unless otherw ise noted.

The design is composed of HDL elemen ts and two cores. You can syn thesize the design

using Xilinx Syn thesis Technology (XST), Synp lify/ Synp lify Pro, or Precision.

This chap ter is the first chap ter in the HD L Design Flow. After the d esign is successfully

defined, you will perform behavioral simu lation (Chap ter 4, Behavioral Simulation), run

imp lementation w ith the Xilinx Imp lementation Tools (Chap ter 5, Design

Implementation), perform tim ing simulation (Chap ter 6, Timing Simulation), and

configure and d own load to the Spartan-3A demo board (Chapter 7, iMPACT Tutorial).

Getting Started

The following sections describe the basic requirem ents for running th e tutorial.

Required SoftwareTo p erform this tutorial, you mu st have th e following software and software comp onents

installed:

Xilinx Series ISE 11.x

Spartan-3A libraries and device files

Note: For detailed software installation instructions, refer to the ISE Design Suite: Installation,

Licensing and Release Notes.

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Chapter 2: HDL-Based DesignR

This tutorial assum es that the softwa re is installed in the d efault location

c:\ xilinx\ 11.1\ ISE. If you have installed the software in a d ifferent location, substitute you r

installation path for c:\ xilinx\ 11.1\ ISEin the procedu res that follow.

Optional Software Requirements

The following third-party synthesis tools are incorporated into this tutorial, and may beused in p lace of the Xilinx Synthesis Tool (XST):

Synplicity Synp lify/ Synplify C-2009.3 (or above)

Mentor Precision Synthesis 2009a.76 (or above)

The following th ird-party sim ulation tool is optional for this tutorial, and m ay be used in

place of the ISE Simu lator:

ModelSim XE/ SE/ PE 6.4b or new er

VHDL or Verilog?

This tutorial supp orts both VHDL an d Verilog d esigns, and app lies to both designs

simu ltaneously, noting d ifferences where app licable. You w ill need to decide w hich HDL

language you w ould like to work through for the tutorial, and dow nload the app ropriate

files for tha t language. XST can synth esize a mixed-languag e design. H owever, this tutorial

does not go over the m ixed langu age feature.

Installing the Tutorial Project Files

The Stopwatch tutorial projects can be downloaded from

http:/ / ww w.xilinx.com/ support/ techsup/ tutorials/ tutorials11.htm. Download either

the VH DL or th e Verilog design flow project files.

After you have d ownloaded the tutorial project files from the web, u nzip the tutorial

projects into th e c:\xilinx\11.1\ISE\ISEexamples directory, replacing any existing

files in that directory.

When you u nzip th e tutorial project files into c:\xilinx\11.1\ISE\ISEexamples , the

directory wtut_vhd (for a VH DL design flow) or wtut_ver (for a Verilog d esign flow ) is

created within c:\xilinx\11.1\ISE\ISEexamples , and the tu torial files are copied

into the n ewly-created d irectory.

The following tab le lists the locations of tu torial source files.

Note: Do not overwrite any files in the solution directories.

Table 2-1: Tutorial Directories

Directory Description

wtut_vhd Incomplete VHDL Source Files

wtut_ver Incomplete Verilog Source Files

wtut_vhd\wtut_vhd_comple

ted

Comp leted VHD L Source Files

wtut_ver\wtut_ver_comple

ted

Completed Verilog Source Files
http://www.xilinx.com/support/techsup/tutorials/tutorials10.htmhttp://www.xilinx.com/support/techsup/tutorials/tutorials10.htm

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Getting StartedR

The completed directories contain th e finished HD L source files.

This tutorial assumes that the files are unzipp ed u nd er

c:\xilinx\11.1\ISE\ISEexamples , but you can u nzip th e source files into any

directory with read -write perm issions. If you un zip the files into a different location,

substitu te your p roject path for in the p rocedur es that follow.

Starting the ISE Software

To start ISE:

Double-click the ISE Project Navigator icon on your desktop or select Start >All

Programs >Xilinx ISE Design Suite 11> ISE > Project Navigator.

Creating a New Project

Creating a New Project: Using the New Project Wizard

1. From Project Navigator, select File>New Project.

The New Project Wizard ap pears.

2. In the Project Location field, browse to c:\xilinx\11.1\ISE\ISEexamples or to

the d irectory in wh ich you in stalled th e project.

3. Type wtut_vhd or wtut_ver in the Project Nam e field.

4. Verify that HDL is selected as the Top-Level Source Type an d clickNext.

Figure 2-1: Project Navigator Desktop Icon

Figure 2-2: New Project Wizard - Create New Project

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The New Project Wizard - Device Properties window appears.

5. Select the following values in the New Project Wizard - Device Properties window :

Product Category: All

Family: Spartan3A and Spartan3AN

Device: XC3S700A

Package: FG484

Speed: -4

Synthesis Tool: XST (VHDL/Verilog)

Simulator: ISim (VHDL/Verilog)

Preferred Language: VHDL or Verilog depending on preference. This willdeterm ine the default langu age for all processes that generate HDL files.

Other p roperties can be left at their defau lt values.

6. Click Next, then Next, and then clickAdd Source in the N ew Project Wizard - Add

Existing Sources wind ow.

7. Brow se to c:\xilinx\11.1\ISE\ISEexamples\wtut_vhd or

c:\xilinx\11.1\ISE\ISEexamples\wtut_ver.

8. Select the following files (.vhd files for VHDL design en try or .v files forVerilog

design en try) and clickOpen.

clk_div_262k

lcd_control

statmach

stopwatch

Figure 2-3: New Project Wizard - Device Properties

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Design DescriptionR

Figure 2-4: New Project Wizard - Adding Source Files Dialog

9. Click Next, then Finish to complete the N ew Project Wizard .

10. In the Add ing Source Files dialog box, verify that all add ed H DL files are associated

with All, and th at they are associated with the work library, then clickOK.

Figure 2-5: Adding Source Files... View Association Selection

Stopping the Tutorial

You m ay stop th e tutorial at any time and save your w ork by selecting File >Save All.

Design Description

The design used in this tutorial is a hierarchical, HDL-based d esign, which means that the

top-level design file is an HDL file that references several other low er-level macros. The

lower-level macros are either H DL modules or IP modu les.

The design begins as an u nfinished d esign. Throughou t the tu torial, you w ill comp lete the

design by generating some of the m odu les from scratch an d by completing others from

existing files. When the design is comp lete, you will simulate it to verify the d esigns

functionality.

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In the run ner s stopwatch d esign, there are five external inpu ts and four external outp ut

buses. The system clock is an externally generated signal. The following list sum mar izes

the input an d ou tput signals of the design.

Inputs

The following are input signals for the tutorial stopwatch design.

strtstop

Starts and stop s the stopw atch. This is an active low signal wh ich acts like the

start/ stop bu tton on a runn ers stopw atch.

reset

Puts th e stopw atch in clocking m ode and resets the time to 0:00:00.

clk

Externally gener ated system clock.

mode

Toggles between clocking and timer mod es. This inpu t is only fun ctional while the

clock or timer is not counting.

lap_load

This is a dual function signal. In clocking m ode it d isplays the curren t clock value in

the Lap display area. In timer mod e it loads the p re assigned valu es from the ROM to

the timer display wh en the timer is not coun ting.

Outputs

The following are ou tpu ts signals for the design.

lcd_e, lcd_rs, lcd_rw

These outputs are the control signals for the LCD d isplay of the Spartan-3A dem oboard used to display the stopwatch times.

sf_d[7:0]

Provides the data valu es for the LCD display.

Functional Blocks

The completed design consists of the following functional blocks.

clk_div_262k

Macro which divides a clock frequency by 262,144. Converts 26.2144 MHz clock into

100 Hz 50% duty cycle clock.

dcm1

Clocking Wizard m acro with interna l feedback, frequen cy controlled ou tpu t, and

du ty-cycle correction. The CLKFX_OUT outp ut converts the 50 MHz clock of the

Spartan-3A dem o board to 26.2144 MHz.

debounce

Schem atic mod ule imp lementing a simp listic debou nce circuit for the strtstop, m ode,

and lap_load inp ut signals.

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Design EntryR

lcd_control

Module controlling the initialization of and outp ut to the LCD d isplay.

statmach

State machine HDL module which controls the state of the stopwatch.

timer_preset

CORE Generato r 64x20 ROM. This m acro contains 64 preset times from 0:00:00 to

9:59:99 which can be load ed into the timer.

time_cnt

Up/ dow n coun ter mod ule wh ich coun ts between 0:00:00 to 9:59:99 decimal. This

macro has five 4-bit outp uts, wh ich represent th e digits of the stopw atch time.

Design Entry

For this hierarchical design, you will examine H DL files, correct syntax errors, create an

HDL m acro, and add a CORE Generator and a Clocking mod ule. You will create and u se

each type of design macro. All procedures u sed in the tu torial can be used later for you rown designs.

With the wtut_vhd.ise or wtut_ver.ise project open in P roject Navigator, the

Hierarchy view in th e Design tab displays all of the sou rce files currently ad ded to the

project, with the associated entity or mod ule nam es (see Figure 2-6).

Instantiated compon ents with no en tity or m odu le declaration are d isplayed w ith a red

question mark.

Adding Source Files

HD L files mu st be add ed to the project before they can be syn thesized. Three HDL files

have already been add ed to this project. An ad ditional file must be add ed.

1. Select Project > Add Source.

2. Select time_cnt.vhd or time_cnt.v from the p roject directory and clickOpen.

3. In the Adding Source Files dialog box, verify thattime_cnt is associated w ith All

and that the associated library is work,and clickOK.

Figure 2-6: Sources Tab Showing Completed Design

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The red qu estion-mark (?) for time_cntshould change to show the VHD file icon.

Each source Design unit is represented under the sources tab using the following syntax: - - * - ().

*VHDL only

Checking the Syntax

To check the syntax of sou rce files:

1. Select stopwatch.vhd or stopwatch.v in the Sources tab.

When you select the H DL file, the Processes tab d isplays all processes available for th is

file.

2. In the Processes tab, click the + next to Synthesize to expand the p rocess hierarchy.

3. Double-click Check Syntax in the Synthesize hierarchy.

Note: Check Syntax is not available when Synplify is selected as the synthesis tool.

Correcting HDL Errors

The time_cnt mod ule contains a syntax error that mu st be corrected. The red x beside

the Check Syntax process ind icates an error was found du ring the analysis. In the Console

tab, Project Navigator rep orts errors with a red (X) and w arnings with a yellow (!).

To d isplay the error in th e sou rce file:

1. Click the file name in the error message in the Console or Errors tab. The source code

comes up in the m ain display tab, with an yellow arrow icon next to the line w ith the

error.

2. Correct any errors in the HDL source file. The comm ents above the error explain this

simple fix.

3. Select File > Save to save the file.

4. Re-analyze the file by selecting the HDL file and right-clicking on the Check Syntax

process and selecting Rerun

Creating an HDL-Based Module

Next you w ill create a modu le from H DL code. With ISE, you can easily create modu les

from H DL code using the ISE Text Editor. The HDL code is then connected to your top-

level HDL d esign throu gh instantiation an d is comp iled w ith the rest of the design.

You w ill author a new HDL m odu le. This macro w ill be used to debou nce the strtstop,

mod e and lap_load inp uts.

Using the New Source Wizard and ISE Text Editor

In this section, you create a file using the N ew Source wizard , specifying the nam e and

por ts of the comp onent. The resu lting H DL file is then m odified in th e ISE Text Editor.

Figure 2-7: time_cnt.vhd File in Sources Tab

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Design EntryR

To create the source file:

1. Select Project > New Source.

The dialog box New Source Wizard open s in wh ich you specify the typ e of source you

wan t to create.

2. Select VHDL Module or Verilog Module.

3. In the File Name field, type debounce.

4. Click Next.

Figure 2-8: New Source Wizard

5. Enter two input ports named sig_in and clk and an output port named sig_out for the

debouncecomp onent in this way:

a. In the first three Port Name fields type sig_in, clkan d sig_out.

b. Set the Direction field to in for sig_in and clk and to out for sig_ou t.c. Leave the Bus designation boxes unchecked.

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6. Click Next to complete the Wizard session.

A d escription of the modu le displays.

7. Click Finish to op en the emp ty H DL file in the ISE Text Editor.

The VHDL file and Verilog file are d isplayed below.

Figure 2-9: New Source Wizard for Verilog

Figure 2-10: VHDL File in ISE Text Editor

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Design EntryR

In the ISE Text Editor, the po rts are already declared in the H DL file, and som e of the basic

file structure is already in p lace. Keywords are d isplayed in blue, comm ents in green, and

values are black. The file is color-coded to enhance readability and help you recognize

typograp hical errors.

Using the Language Templates

The ISE Language Temp lates includ e HDL constructs and synth esis temp lates whichrepresent comm only used logic componen ts, such as coun ters, D flip-flops, mu ltiplexers,

and pr imitives. You w ill use the Deboun ce Circuit temp late for this exercise.

Note: You can add your own templates to the Language Templates for components or constructs

that you use often.

To invoke the Language Temp lates and select the template for this tuto rial:

1. From Project Navigator, select Edit>Language Templates.

Each H DL langu age in the Language Temp lates is divided into five sections: Common

Constru cts, Device Macro Instantiation, Dev ice Primitive Instan tiation, Simu lation

Constru cts, Synthesis Constructs and User Temp lates. To expand the view of any of

these sections, click the + next to the section. Click any of the listed tem plates to view

the temp late contents in the right p ane.

2. Under either the VHDL or Verilog hierarchy, expand the Synthesis Constructs

hierarchy, expand the Coding Examples hierarchy, expand the Misc hierarchy, and

select the tem plate called Debounce Circuit (VHDL) or One Shot, Debounce Circuit(Verilog). Use the approp riate template for the language you are u sing.

Upon selection, the HDL code for a debounce circuit is displayed in th e right pan e.

Figure 2-11: Verilog File in ISE Text Editor

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Adding a Language Template to Your File

You w ill now u se Use in File method for add ing temp lates to your H DL file. Refer to

Working with Langu age Temp lates in the ISE Help for add itional usability options,

including drag and d rop options.

To add the temp late to your H DL file:

1. Open or br ing forward the debounce.v or debounce.vhd source file. Position the

cursor und er the architecture begin statement in the VHDL file, or und er the m odu le

and pin declarations in t he Verilog file.

2. Return to the Language Templates window, right-click on the Debounce Circuittemplate in the template index, and select Use In File.

Figure 2-13: Selecting Language Template to Use in File

3. Close the Language Templates window.

Figure 2-12: Language Templates

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Design EntryR

4. Open the debounce.v or debounce.vhd source file to verify that th e Language

Template w as p roperly inserted.

5. (Verilog only) Comp lete the Verilog mod ule by doing the following:

a. Remove the reset logic (not used in this design) by deleting the three lines

beginning with if and end ing with else.

b. Change to qin all six locations.

Note: You can select Edit -> Find & Replace to facilitate this. The Find fields appear at the bottom

of the Text Editor.

c. Change to clk; to sig_in; and to sig_out.

6. (VHDL only) Complete the VHDL module by doing the following:

a. Move the line beginning with the word signalso that it is between the

architecturean d beginkeywords.

b. Remove the reset logic (not used in this design) by deleting the five lines beginning

with if (... and end ing with else, and delete one of the end if;

lines.

c. Use Edit > Find & Replace to change to clk; D_IN to sig_in; and

Q_OUT to sig_out.You n ow have comp lete and functional H DL code.

7. Save the file by selecting File>Save.

8. Select one of the debounce instances in the Sources tab.

9. In the Processes tab, double-clickCheck Syntax. Verify that th e syntax check passes

successfully. Correct any errors as necessary.

10. Close the ISE Text Editor.

Creating a CORE Generator Module

CORE Generator is a graphical interactive design tool that enables you to create high-level

mod ules such as memory elements, math fun ctions and commun ications and IO interfacecores. You can custom ize and p re-optimize the mod ules to take advan tage of the inherent

architectural features of the Xilinx FPGA architectures, such as Fast Carry Logic, SRL16s,

and distributed an d block RAM.

In this section, you will create a CORE Generator m odu le called timer_preset. The

mod ule will be used to store a set of 64 values to load into the timer.

Creating a CORE Generator Module

To create a CORE Generator m odu le:

1. In Project Navigator, select Project>New Source.

2. Select IP (CORE Generator & Architecture Wizard).

3. Type timer_preset in the File name field.

4. Click Next.

5. Expand the IP tree selector to locate Memories & Storage Elements >RAMs &

ROMs.

6. Select Distributed Memory Generator, then clickNext and clickFinish to open the

Distributed Memory Generator customization GUI. This customization GUI enables

you to custom ize the memory to th e design specifications.

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Figure 2-14: New Source Wizard - New IP Module

7. Fill in the Distributed Memory Generator customization GUI with the following

settings:

Component Name: timer_preset - Defines the name of the m odu le. Depth: 64 - Defines the nu mber of values to be stored

Data Width: 20 - Defines the width of the outpu t bus.

Memory Type: ROM

8. Click Next.

9. Leave Inpu t and output options as Non Registered; ClickNext.

Figure 2-15: CORE Generator - Distributed Memory Generator Customization GUI

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Design EntryR


10. Specify the Coefficients File: Click th e Browse button and select

definition1_times.coe located in the p roject d irectory.

11. Check that only the following pins are used (used pins are highlighted on the symbolon th e left side of the custom ization GUI):

a[5:0]

spo[19:0]

12. ClickGenerate.


The mod ule is created and au tomatically added to the project library.

Note: A number of files are added to the ipcore_dir sub-directory of the project directory. Some of

these files are: timer_preset.vho or timer_preset.veo

These are the instan tiation temp lates used to incorporat e the CORE Generator

mod ule into your source HDL.

timer_preset.vhd or timer_preset.v

These are HDL wrap per files for the core and are used only for simu lation.

timer_preset.ngc

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This file is the netlist that is used d ur ing the Translate phase of implemen tation.

timer_preset.xco

This file stores the configu ration informa tion for the timer_preset mod ule and is

used as the project sou rce in the ISE project.

timer_preset.mif

This file provides the initialization values of the ROM for simulation.

Instantiating the CORE Generator Module in the HDL Code

Next, instantiate the CORE Generator mod ule in the HD L code u sing either a VHDL flow

or a Verilog flow.

VHDL Flow

To instantiate the CORE Generator mod ule using a VHDL flow:

1. In Project Navigator, double-clickstopwatch.vhd to op en the file in ISE Text Editor.

2. Place your cursor after the line that states:

-- Insert CORE Generator ROM component declaration here

3. Select Edit > Insert File, then select ipcore_dir/timer_preset.vho and clickOpen.

The VHDL temp late file for the CO RE Generator instantiation is inserted .

4. Highlight the inserted code from

-- Begin Cut here for INSTANTIATION Template ----

to

--INST_TAG_END ------ END INSTANTIATION Template -----

5. Select Edit> Cut.

6. Place the cursor after the line that states:--Insert CORE Generator ROM Instantiation here

7. Select Edit> Paste to place the core instantiation.

8. Change the instance name from your_instance_name to t_preset.

Figure 2-18: VHDL Component Declaration for CORE Generator Module

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Design EntryR

9. Edit this instantiated code to connect the signals in the Stopw atch design to the ports

of the CORE Generator modu le as shown below.

10. The inserted code oftimer_preset.vho contains several lines of comm ented text

for instru ction and legal documen tation. Delete these comm ented lines if desired.

11. Save the design using File> Save, and close the ISE Text Editor.

Verilog Flow

To instantiate the CORE Generator m odule u sing a Verilog flow:

1. In Project Navigator, double-clickstopwatch.v to op en th e file in the ISE Text Editor.

2. Place your cursor after the line that states:

//Place the Coregen module instantiation for timer_preset here

3. Select Edit> Insert File, and select ipcore_dir/timer_preset.veo.

4. The inser ted code of timer_preset.veo contains several lines of comm ented text

for instru ction and legal documen tation. Delete these comm ented lines if desired.

5. Change the instance name from YourInstanceName to t_preset.

6. Edit this code to connect the signals in the Stopw atch design to the ports of the CORE

Generator modu le as shown below.

7. Save the design using File>Save and close stopwatch.v in the ISE Text Ed itor.

The core modu le should now app ear beneath the Stopw atch modu le in the h ierarchy.

Creating a DCM ModuleThe Clocking Wizard , a par t of the Xilinx Architecture Wizard, enables you to grap hically

select Digital Clock Manager (DCM) features th at you wish to u se. In th is section you will

create a basic DCM mod ule with CLK0 feedback and du ty-cycle correction.

Using the Clocking Wizard

To create the dcm1 module:

Figure 2-19: VHDL Component Instantiation of CORE Generator Module

Figure 2-20: Verilog Component Instantiation of the CORE Generator Module

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1. In Project Navigator, select Project>New Source.

2. In the New Source dialog box, select IP (CoreGen & Architecture Wizard) source and

type dcm1 for the file nam e.

3. Click Next.

4. In the Select IP dialog box, select FPGA Features and Design> Clocking>Spartan-

3E, Spartan-3A >Single DCM SP.

Figure 2-21: Selecting Single DCM IP Type

5. Click Next, then Finish. The Clocking Wizard is laun ched.

6. Verify t ha t RST, CLK0 an d LOCKED ports are selected.

7. Select CLKFX port.

8. Type 50 and select MHz for the Input Clock Frequency.

9. Verify the following settings:

Phase Shift: NONE

CLKIN Source: External, Single

Feedback Source: Internal

Feedback Value: 1X

Use Duty Cycle Correction: Selected

10. Click the Advanced button.

11. Select Wait for DCM lock before DONE Signal goes high.

12. ClickOK.

13. ClickNext, and then clickNext again.

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Design EntryR

14. Select Use output frequency and type 26.2144 in the box and select MHz.

15. ClickNext, and then clickFinish.

Thedcm1.xaw file is add ed to the list of project sou rce files in th e Sources tab.

Instantiating the dcm1 Macro - VHDL Design

Next, you will instantiate the d cm1 macro for your VHDL or Verilog design. To instantiate

the dcm1 macro for the VHDL design:

1. In Project Navigator, in the Sources tab, select dcm1.xaw.

2. In the Processes tab, right-clickView HDL Instantiation Template and select ProcessProperties.

3. Choose VHDL for the HDL Instantiation Temp late Target Langu age value and clickOK.

4. In the Processes tab, double-clickView HDL Instantiation Template.

5. Highlight the component declaration template in the newly opened H DL Instantiation

Temp late (dcm1.vhi), show n below.

6. Select Edit>Copy.

7. Place the cursor in the stopwatch.vhd file in a section labeled

-- Insert dcm1 component declaration here.

8. Select Edit > Paste to paste the comp onent d eclaration.

26.2144Mhz( ) 218

100Hz=

Figure 2-22: VHDL DCM Component Declaration

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9. Highlight the instantiation template in the newly opened HDL Instantiation Template,

shown below.

10. Select Edit>Copy.

11. Place the cursor in the stopwatch.vhd file below the line labeled

-- Insert dcm1 instantiation here.

12. Select Edit > Paste to paste the instantiation template.

13. Make the necessary changes as shown in the figure below.

14. Select File>Save to save the stopwatch.vhd file.

The dcm1 mod ule should now ap pear beneath the stopw atch mod ule in the design

hierarchy.

Instantiating the dcm1 Macro - Verilog

To instan tiate the dcm1 macro for you r Verilog design:

1. In Project Navigator, in the Sources tab, select dcm1.xaw.

2. In the Processes tab, double-clickView HDL Instantiation Template.

Figure 2-23: VHDL DCM Component Instantiation

Figure 2-24: VHDL Instantiation for dcm1

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Synthesizing the DesignR

3. From the newly opened HDL Instantiation Template (dcm1.tfi), copy t he

instantiation template, shown below.

4. Paste the instantiation template into the section in stopwatch.v labeled

//Insert dcm1 instantiation here.

5. Make the necessary changes as shown in the figure below.

Figure 2-26: Verilog Instantiation for dcm1

6. Select File>Save to save the stopwatch.v file.

The dcm1 mod ule should now ap pear beneath the stopw atch mod ule in the designhierarchy.


So far you have been u sing XST (the Xilinx syn thesis tool) for syntax checking. N ext, you

will synth esize the design u sing either XST, Synp lify/ Synplify Pro or Precision. The

synth esis tool uses the designs HDL code and generates a sup por ted netlist type (EDIF or

NGC) for the Xilinx imp lementation too ls. The synthesis tool performs th ree general steps

(although a ll synthesis tools fur ther break d own these general steps) to create the netlist:

Analyze / Check Syntax

Checks the syntax of the source code.

Compile

Translates and optim izes the HDL code into a set of components th at the synthesis tool

can recognize.

Map

Translates the comp onen ts from th e compile stage into the target technologys

primitive comp onents.

Figure 2-25: dcm1 Macro and Instantiation Templates

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The synthesis tool can be changed at any time d uring the design flow. To change the

synth esis tool:

1. Select the targeted part in the Sources tab.

2. Right-click and select Design Properties.

3. In the Design Properties dialog box, click on the Synthesis Tool value and use the pu ll-

dow n arrow to select the desired synth esis tool from the list.Note: If you do not see your synthesis tool among the options in the list, you may not have the

software installed or may not have it configured in ISE. The Synthesis tools are configured in the

Preferences dialog box (Edit>Preferences, expand ISE General, then click Integrated Tools).

Note: Changing the design flow results in the deletion of implementation data. You have not yet

created any implementation data in this tutorial. For projects that contain implementation data, Xilinx

recommends that you make a copy of the project using File > Copy Project if you would like to make

a backup of the project before continuing.

Synthesizing the Design using XST

Now that you have created an d an alyzed the design, the next step is to synthesize the

design. During synthesis, the HDL files are translated into gates and optimized for the

target architecture.

Processes ava ilable for syn thesis u sing XST are as follows:

View RTL Schematic

Generates a schematic view o f your RTL netlist.

View Technology Schematic

Generates a schem atic view o f your Technology n etlist.

Check Syntax

Verifies that th e HDL code is entered prop erly.

Generate Post-Synthesis Simulation Model

Creates HDL simulation models based on the synthesis netlist.

Entering Synthesis Options

Synthesis options enable you to m od ify the behavior of the synthesis tool to make

optimizations according to th e needs of the d esign. One comm only used option is to

control synthesis to make optimizations based on area or speed. Other options include

controlling the maximu m fanou t of a flip-flop ou tpu t or setting the desired frequency of

the design.

To enter syn thesis options:

1. Select stopwatch.vhd (or stopwatch.v) in the Sources view.

2. In the Processes view, right-click the Synthesize process and select ProcessProperties.

3. Ensure that the Property display level option is set to Advanced. This will allow youto view to the full set of process properties ava ilable.

4. Under the Synthesis Options tab, set the Netlist Hierarchy p roperty to a value of

Rebuilt.

5. Click OK.

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Now you are ready to synth esize your d esign. To take the HDL code and generate a

compatible netlist:

1. Select stopwatch.vhd (or stopwatch.v).

2. Double-click the Synthesize process in th e Processes view.

The RTL / Technology Viewer

XST can generate a schem atic representation of the HDL code tha t you h ave entered . A

schematic view of the code h elps you an alyze your d esign by displaying a grap hical

connection between the variou s compon ents that XST has inferred. There are two form s of

the schematic representation:

RTL View - Pre-optim ization of the HDL code.

Technology View - Post-synthesis view of the H DL design map ped to the target

technology.

To view a schem atic representa tion of your H DL code:

1. In the Processes tab, click the + next to Synthesize to expand the p rocess hierarchy.

2. Double-click View RTL Schematic or View Technology Schematic.

3. If the Set RTL/ Tech Viewer Startup Mod e dialog appears, select Start with theExplorer Wizard.

4. In the Create RTL Schematic start page, select the clk_divider an d debounce

components from the Available Elements list, then click the Add -> button to move theselected items to the Selected Elemen ts list.

5. Click Create Schematic.

Figure 2-27: Create RTL Schematic start page

The RTL Viewer allows you to select the p ortions of the d esign to d isplay as schematic.

When th e schem atic is displayed, double-click on the symbol to pu sh into the schematic

and view the various d esign elements and connectivity. Right-click the schematic to view

the various operations that can be performed in the schematic viewer.

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Figure 2-28: RTL Schematic

You h ave comp leted XST synthesis. An N GC file now exists for the Stopwatch design.

To continue with th e HDL flow:

Go to Chap ter 4, Behavioral Simulation, to perform a pre-synthesis simulation of

this design.

OR

Proceed to Chapter 5, Design Implementation,to place and route the d esign.

Note: For more information about XST constraints, options, reports, or running XST from the

command line, see the XST User Guide. This guide is available in the collection of software manuals

and is accessible from ISE by selecting Help>Software Manuals, or from the web athttp:/ / ww w.xilinx.com/ support/ software_manuals.htm.

Synthesizing the Design using Synplify/Synplify Pro

Now that you h ave entered an d an alyzed the design, the next step is to synthesize the

design. In this step, the HDL files are translated into ga tes and op timized to the target

architecture. To access Synp lifys RTL viewer an d constraints ed itor you mu st run Synp lify

outside of ISE.

To synth esize the design , set the global synthesis options:

1. Select stopwatch.vhd (or stopwatch.v).

2. In the Processes tab, right-click the Synthesize process and select Process

Properties.

3. Ch eck th e Write Vendor Constraint File box.

4. Click OK to accept th ese values.

5. Double-click the Synthesize process to run synthesis.

Note: This step can also be done by selecting stopwatch.vhd (or stopwatch.v), clicking

Synthesize in the Processes tab, and selecting Process>Run.

Processes available in Synp lify and Synp lify Pro synthesis includ e:

View Synthesis Report

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Lists the synthesis optimizations that w ere performed on the d esign an d gives a brief

timing and mapp ing report.

View RTL Schematic

Accessible from the Launch Tools hierarchy, this process d isplays Synp lify or Synplify

Pro with a schematic view of your H DL code

View Technology SchematicAccessible from the Launch Tools hierarchy, this process d isplays Synp lify or Synplify

Pro with a schematic view of your HDL code m apped to the p rimitives associated with

the target technology.

Examining Synthesis Results

To v iew overall synth esis results, dou ble-clickView Synthesis Report under theSynthesize process. The report consists of the following fou r sections:

Comp iler Report

Mapp er Report

Timing Report

Resource Utilization

Compiler Report

The compiler report lists each H DL file that w as compiled, names w hich file is the top

level, and disp lays the syntax checking result for each file that w as compiled. The report

also lists FSM extractions, inferred mem ory, warn ings on latches, u

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