CONSTANT TRANSCONDUCTANCE BIAS CIRCUIT WITH AN ON-CHIP RESISTOR

Nema Talebbeydokhti, Pavan Kumar Hanumolu, Peter Kurahashi and Un-Ku Moon

School of Electrical Engineering and Computer ScienceOregon State University, Corvallis, OR 97331

ABSTRACTA method to generate stable transconductance (gm)without using precise external components is pre-sented. The off-chip resistor in a conventionalconstant-gm bias circuit is replaced with a variableon-chip resistor. A MOSFET biased in triode regionis used as a variable resistor. The resistance of theMOSFET is tuned by a background tuning scheme toachieve the stable transconductance that is immuneto process, voltage and temperature variation. Thetransconductance generated by the constant-gm biascircuit designed in 0.18m CMOS process with 1.5Vsupply displays less than 1% variation for a 20%change in power supply voltage and less than 1.5%variation for a 60C change in temperature. Thewhole circuit draws approximately 850A from a1.5V supply.

I. INTRODUCTION

Constant transconductance (gm) bias circuits arewidely used in many analog integrated circuit appli-cations, such as low-noise amplifiers (LNA) [1] andGm C filters [2]. The constant transconductanceis converted to a fixed current by using a voltageprovided by a band-gap reference. If the transcon-ductance and the reference voltage are process, volt-age and temperature (PVT) independent then, natu-rally, the current generated using these parameters isalso PVT independent and hence can be used as amaster bias current on a large analog chip. Thereare several ways of implementing constant-gm biascircuits. Of them resistor-referred constant-gm biascircuit shown in Fig. 1 is the most commonly used.Assuming square-law devices and neglecting channel-length modulation and body effect, this bias circuitprovides a gm that is inversely proportional to resistorR. In practice to achieve constant gm, a precise off-chip resistor is used.

M4

M1

M3

M2

R CP

CC

Y

X

Off-chip

Fig. 1. A simple constant-gm bias circuit.

This simple implementation has three major draw-backs. First, this circuit is sensitive to power supplyvariation. In the presence of supply noise, node X andnode Y vary differently leading to current variation inthe two branches due to channel-length modulation ofM1 and M2. This leads to gm variation with changesin supply voltage. Second, the stability is degraded bythe large parasitic capacitor CP associated with thepad and the off-chip resistor. Analysis in [3] showsthat a large compensation capacitor CC of the orderof CP is needed to make the circuit stable. Finally,the need for external components increases the overallcost of the system.

In this paper, we present an alternate constant-gmbias circuit that uses an on-chip resistor and is lesssusceptible to power supply variation. We will focuson the tuning scheme that enables the use of an on-chip resistor to obtain constant gm. This paper isorganized as follows. The constant gm bias circuitis presented in Section II. The tuning scheme used toachieve a constant transconductance with an on-chipresistor is discussed in Section III and the simula-

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tion results are presented in Section IV. Finally, theimportant results are summarized in Section V.

II. CONSTANT GM BIAS CIRCUIT

The bias circuit used in this design is shown inFig. 2. The active current mirror formed by M3 and

+

M5 M3

M2M1

M7

M4

M6

Vctrl

Cc

Mres

Start-up

Fig. 2. An improved constant-gm bias circuit.

M4 in Fig. 1 is replaced by cascoded current sources(M3, M4, M6 and M7) and the precise off-chipresistor R is replaced by an on-chip MOS transistorMres biased in triode region. The cascode transistorsM6, M7 are biased by a separate bias branch, whilethe current source transistors M3, M4 are self-biasedusing an opamp in negative feedback. Additionally,this feedback forces the drain voltages of M1, M2 tobe equal thus obviating the need for cascoding M1and M2. The feedback loop is compensated using thecapacitor Cc. The power supply noise immunity isimproved due to the increased output impedance ofthe cascoded current sources.

Most of the self-biased circuits are susceptible tothe lock-up state. In the bias circuit shown in Fig. 2,the condition in which all the transistors are OFF isa stable state. In order to avoid this undesired state, asimple start-up circuit consisting of two inverters andtransistor M5 is added. In the lock state, M5 injectsa small current into the source of M6 to start-up thecircuit. The inverters are designed to pull-up the gate

of M5 to VDD thereby disabling the start-up circuitduring normal operation.

As mentioned earlier, the off-chip resistor is re-placed by a MOS transistor Mres. The resistance ofa MOS transistor biased in triode region varies bymore than 20% with PVT changes resulting in anunacceptable variation of the transconductance of thebias circuit. In the following section, we present abackground tuning scheme that maintains a constantgm by continuously tuning the ON resistance ofMres.

III. TUNING SCHEME

The tuning of a resistor to a specific value is acommon problem in many classes of analog circuits.For example, resistors in continuous-time filters aretuned to achieve accurate bandwidth of the filter in thepresence of PVT variation [4]. It is very desirable thatthe tuning be done in background without interruptingthe tuned block. Many of such background tun-ing techniques are based on master-slave approachshown in Fig. 3. In this method, a master consistingof PVT invariant reference tunes the PVT variantslave. For example, in [5] the MOS resistor of theconstant-gm bias circuit (slave) is tuned by a phaselocked-loop (PLL) (master) consisting of gm lockedoscillator. However, this design requires a full PLLresulting in a large area and power overhead. In thispaper, we present a simple but effective alternativescheme to tune the resistor.

VrefCOMPAREMASTER

Vctrl

M4

M1

M3

M2

R

SLAVE

Fig. 3. Concept of master-slave tuning.

The master tuning block is shown in Fig. 4 [6]in which a switched-capacitor (SC) resistor is usedas the reference element. It consists of an integrator

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Vref

+

M1res1C2

RLP

CLP

VctrlC1

SLAVEMres

2

12

Ripple filter

Fig. 4. Time constant matching tuning scheme.

with two separate branches, a replica resistor (M1res)branch and a SC resistor branch. The negative feed-back generates the control voltage (Vctrl) that forcesthe error current generated due to mismatch betweenthe time constants of the two branches. In other wordsthe following equality is achieved in steady state.

RM1resC2 =1

FCKC1C2 (1)

The ripple-pole filter at the output of the integra-tor is used to suppress the ripple generated due tothe sampling nature of the tuning circuit. Since theclock frequency FCK and the on-chip capacitor ratioC1C2

can be defined accurately, this tuning schemeachieves a precise time constant RM1resC2. Therefore,by matching M1res and Mres a stable and PVT invari-ant transconductance can be achieved. Note that theabsolute accuracy of the transconductance is limitedby the absolute accuracy of the on-chip capacitor C1.

By driving the gate of the variable resistor Mreswith Vctrl and forcing the reference voltage in thetuning circuit to be equal to the VDS of Mres, theON resistance of the master and slave (M1res andMres) can be accurately matched. The complete biascircuit along with the reference generation branchis shown in Fig. 5. The reference generation circuitconsists of a replica branch biased with twice thecurrent in Mres to support the two branches of thetuning circuit. By symmetry, Vref is equal to VX .One problem with this simple reference generation isclock feed-through from the tuning circuit into theconstant-gm bias circuit through the gate-to-sourcecapacitance (Cgs) of M8. First order passive low-passfilter consisting of RCF and CCF is used to suppressthe clock feed through.

Vref

M8

M9

M10

+

M5 M3

M2M1

M7

M4

M6

Vctrl

Cc

Mres

Start-up

RCF

CCF

Reference Generation

VX

Fig. 5. Complete constant-gm circuit with referencegeneration.

Stability is a major concern in any feedback sys-tem. Since the reference voltage in the constant-gm bias circuit is generated by the tuning circuit, itis important to prevent interaction between the twocircuits. The bandwidth of the tuning circuit is chosenmuch smaller than the constant-gm bias circuit. Thischoice allows complete settling of the bias circuitbefore the tuning circuit makes the subsequent updateof Vctrl.

IV. SIMULATION RESULTS

The constant-gm bias circuit along with the tuningcircuit is implemented in 0.18m CMOS processoperating with 1.5V supply voltage. Fig. 6 depictsthe control voltage settling transient of the tuningcircuit. As mentioned earlier, a smaller bandwidth ofthe tuning circuit compared to that of the bias circuitleads to settling of the control voltage with out anyovershoot. A supply voltage variation of 20% ledto less than 1% variation in the transconductance.The dependence of the transconductance on the tem-perature is illustrated in Fig. 7. The transconductancevaries by less than 1.5% for a 60C variation intemperature.

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0 0.5 1 1.5 2 2.5 30.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Co

ntr

ol V

olt

age

[V]

Time [Sec]

Fig. 6. Control voltage settling.

20 30 40 50 60 70 801.5

1

0.5

0

0.5

1

1.5

Temperature [C]

gm

var

iati

on

[%

]

Fig. 7. Gm variation with temperature.

V. CONCLUSION

We presented a constant-gm bias circuit along witha tuning circuit that obviates the need for an off-chipresistor. With an on-chip resistor, the problems asso-ciated with the external resistor such as stability andadditional cost are eliminated. A master-slave tuningcircuit based on time-constants matching is used toachieve stable transconductance that is immune toprocess, voltage and temperature variation. The biascircuit designed in 0.18m CMOS process has lessthan 1% and 1.5% variation of transconductancewith 20% supply voltage variation and 60C temper-ature variation respectively.

VI. REFERENCES[1] T. Lee, The design of CMOS radio-frequency

integrated circuits, Cambridge University Press,2004

[2] J. Chen, B. Shi, Novel constant transconduc-tance references and the comparisons with thetraditional approach, in Proc. Southwest Symp.Mixed-Signal Design conf., pp. 104-107, Feb.2003.

[3] S. Nicolson, P. Khoman, Improvements in bi-asing and compensation of CMOS opamps, inProc. ISCAS, Vol. 1, pp. 23-26, May 2004.

[4] Y. Tsividis, M. Banu, and J. Khoury,Continuous-time MOSFET-C filters inVLSI, IEEE J. Solid-State Circuits, vol. 21,no. 1, pp. 15-30, Feb. 1986.

[5] A. McLaran, K. Martin, Generation of accurateon-chip time constants and stable transconduc-tances, IEEE J. Solid-State Circuits, vol. 36,no. 4, pp. 691-695, April. 2001.

[6] T. Viswanathan, S. Murtuza, V. Syed, J. Berry,and M. Staszel, Switched-capacitor frequencycontrol loop, IEEE J. Solid-State Circuits, vol.4, pp. 775-778, Aug. 1982.

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