iPORT™ NTx-GigE Embedded Video Interface · The NTx-GigE Embedded Video Interface interacts...

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PLEORA TECHNOLOGIES INC.

iPORT™ NTx-GigE Embedded Video Interface

User Guide

Copyright © 2013 Pleora Technologies Inc.

These products are not intended for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Pleora Technologies Inc. (Pleora) customers using or selling these products for use in such applications do so at their own risk and agree to indemnify Pleora for any damages resulting from such improper use or sale.

Trademarks

PureGEV, eBUS, iPORT, vDisplay, AutoGEV, AutoGen, and all product logos are trademarks of Pleora Technologies. Third party copyrights and trademarks are the property of their respective owners.

Notice of Rights

All information provided in this manual is believed to be accurate and reliable. No responsibility is assumed by Pleora for its use. Pleora reserves the right to make changes to this information without notice. Redistribution of this manual in whole or in part, by any means, is prohibited without obtaining prior permission from Pleora.

Document NumberEX001-015-0002, Version 3.0, 12/19/13

Table of Contents
About this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
What this Guide Provides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

About the iPORT NTx-GigE Embedded Video Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3The iPORT NTx-GigE Embedded Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

eBUS SDK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Model Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Feature Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Selected GenICam Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Connector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Mounting the Power, GPIO, and Serial Connector to an Enclosure Backplate . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Power, GPIO, and Serial Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power, GPIO, and Serial Pinouts — 12-Pin Connector on GPIO Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Power, GPIO, and Serial Pinouts — 20-Pin Connector on GigE PHY Board . . . . . . . . . . . . . . . . . . . . . . . . . . 15GPIO Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Mapping the 12-Pin and 20-Pin Connectors to the 100-Pin User Circuitry Connector . . . . . . . . . . . . . . . . . . . 1812-Pin Circular Connector Mate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

100-Pin User Circuitry Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19NTx-Mini Adapter Board Pinout Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28PoE Powered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Externally Powered. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Power Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Output Power Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Thermal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Ambient and Junction Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Bulk Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Bulk Interfaces and Supported Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34UART/USRT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Supported USRT Clock Frequencies and Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35GenICam Interface for Serial Communication Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

i

Pixel Bus Definitions and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Pixel Bus Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Mono/RGB/Truesense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38YUV411_8_UYYVYY - 1 Tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39YUV411_8_UYYVYY - 2 Tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40YUV422_8_UYVY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41YUV8_UYV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Pixel Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Pixel Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Case 1: FVAL and LVAL are Level-Sensitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Case 2: FVAL and LVAL are Edge-Sensitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Case 3: FVAL is Edge-Sensitive and LVAL is Level-Sensitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Timing Values for all Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Signal Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47PLC Programming Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Installing the eBUS SDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Installing the eBUS SDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Installing the Driver and Configuring the NIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Connecting to the Embedded Video Interface and Configuring General Settings . . . . . . . . . . . . . . 59Connecting the Ethernet Cables and Confirming Image Streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Configuring the Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Providing the Embedded Video Interface with an IP Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Configuring an Automatic/Persistent IP Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Configuring the Embedded Video Interface’s Image Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Implementing the eBUS SDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Network Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Unicast Network Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Required Items — Unicast Network Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Embedded Video Interface Configuration — Unicast Network Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 69

Multicast Network Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Required Items — Multicast Network Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Connecting the Hardware and Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Configuring the Devices for a Multicast Network Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

System Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Troubleshooting Tips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Changing to the Backup Firmware Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Reference: Mechanical Drawings and Material List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Material List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

ii iPORT NTx-GigE Embedded Video Interface User Guide

Chapter 1

About this GuideThis chapter describes the purpose and scope of this guide, and provides a list of complimentary guides.

The following topics are covered in this chapter:

• “What this Guide Provides” on page 2

• “Related Documents” on page 2

About this Guide 1

What this Guide Provides

This guide provides you with all of the information you need to connect the iPORT™ NTx-GigE Embedded Video Interface to your sensor and related electronics to create a camera or other imaging device. In this guide you will find a product overview, connector details, and mechanical drawings along with instructions for installing the Pleora eBUS™ SDK, connecting the device, and performing general configuration tasks to properly display video.

The last chapter of this guide provides Technical Support contact information for Pleora Technologies.

Related Documents

The iPORT NTx-GigE Embedded Video Interface User Guide is complemented by the following guides:

• eBUS Player Quick Start Guide

• eBUS SDK C++ API SDK Help File

• eBUS SDK .NET API Help File

• eBUS SDK Programmer’s Guide

• GigE Vision Standard, version 2.0 available from the Automated Imaging Association (AIA) at www.visiononline.org

• GenICam Standard Features Naming Convention available from the European Machine Vision Association (EMVA) at www.emva.org.

• vDisplay HDI-Pro External Frame Grabber User Guide

• iPORT Advanced Features User Guide

2 iPORT NTx-GigE Embedded Video Interface User Guide

http://www.visiononline.org/

http://www.emva.org

http://www.emva.org

Chapter 2

About the iPORT NTx-GigE Embedded Video InterfaceThis chapter describes the embedded video interface, including the product variants and key features.


• “The iPORT NTx-GigE Embedded Video Interface” on page 4

• “Model Variants” on page 5

• “Feature Set” on page 6

• “Selected GenICam Features” on page 7

About the iPORT NTx-GigE Embedded Video Interface 3

The iPORT NTx-GigE Embedded Video Interface

Pleora’s iPORT™ NTx-GigE Embedded Video Interface hardware helps manufacturers shorten time-to-market, reduce risk, and lower costs by providing a straightforward way to integrate GigE Vision 2.0 video connectivity into cameras, x-ray detector panels, and imaging systems.

The NTx-GigE Embedded Video Interface interacts seamlessly with Pleora’s other products in networked or point-to-point digital video systems. It complies with the GigE Vision® 2.0 and GenICam™ standards, ensuring interoperability in a multi-vendor environment.

The ultra-compact NTx-GigE is easily embedded into small-body cameras, flat-panel x-ray detectors, and imaging systems. Power over Ethernet (PoE) and external power options provide design flexibility, while lowering component and operating costs. The product supports the IEEE 1588 Precision Time Protocol to synchronize image capture functions and other system elements, enabling the exact triggering of image acquisition.

Pleora’s iPORT NTx-GigE Embedded Video Interface is supported by:

• An evaluation kit to help speed time-to-market by enabling the rapid design of prototypes andproof-of-concept demonstrations, often without requiring hardware development;

• eBUS™ SDK, a feature-rich application development toolkit for manufacturers to rebrand anddistribute with their end-products;

• The AutoGen XML generation tool and a firmware reference design, which makes it fast and easyfor manufacturers to create a user-friendly GenICam interface for their products.

Figure 1: iPORT NTx-GigE Embedded Video Interface Block Diagram

eBUS SDK

As an element of Pleora’s video connectivity solutions, the iPORT NTx-GigE Embedded Video Interface is offered with the eBUS™ SDK, a feature-rich toolkit that provides the building blocks needed to quickly and easily design high-performance video applications that consume minimal CPU resources.


Model Variants

The iPORT NTx-GigE Embedded Video Interface is supplied in these variants and is equipped with these parts, as listed in the following table.

Table 1: NTx-GigE Model Variants

iPORT NTx-GigE Embedded Video Interface Package variants*

iPORT NTx-GigE Embedded Video Interface (Order code: 900-6004)

Quantity

Board set, including GigE PHY board and FPGA board 1

GPIO board, including flat-flex cable 1

12-pin circular connector 1

iPORT NTx-GigE Evaluation Kit (Order Code: 900-6005)

Quantity

Board set, including GigE PHY board and FPGA board 1

GPIO board with soldered 12-pin circular connector 1

NTX-Mini Adapter 1

Prober Board 1

Ethernet cable 1

Power supply 1

Gigabit Ethernet network interface card (NIC) 1

Pleora eBUS SDK, provided on USB stick (includes eBUS Player sample application) 1

iPORT NTx-GigE Embedded Video Interface User Guide (this guide) 1

*Before assembly, ensure that all components are included in the selected package.

5About the iPORT NTx-GigE Embedded Video Interface

e)

32

Hardware Frame Grabber

Number of data channels 1

Scan modes Area Scan (Progressivand Line Scan

Pixel depth (bits) 8, 10, 12, 14, 16, 24,

Pixel clock Min: 20 MHz

Max: 120 MHz

Taps 1, 2, 4

Image width (pixels) Minimum: 8 Default: 640 Maximum: 16,376 Increment: 4

Image height (pixels) Minimum: 1 Default: 480 Maximum: 16,383 Increment: 1

Windowing/region of interest

Yes

Tap reconstruction Interleaved only

User circuitry interface 100-pin Samtec Connector: LSHM-150-04.0-L-DV-A-N-TR

External interface 12-pin Hirose connector: HR10A-10R-12PB(71)

GigE interface RJ45 receptacle, Amphenol: RJHSE-3P85

GigE PHY Marvell 88E1510

FPGA Altera Cyclone V

Image Buffer 120 MByte 16-bit wide DDR3

Total image size should be smaller than (120MB-32k)

Inputs/Outputs on User Circuitry Interface

Video input 2.5V LVTTL/LVCMOS

GPIO inputs 4 x 2.5V LVTTL/LVCMOS

GPIO outputs 4 x 2.5V LVTTL/LVCMOS

UART/USRT inputs 3 x 2.5V LVTTL/LVCMOS

UART/USRT outputs 3 x 2.5V LVTTL/LVCMOS

Camera control outputs 4 x 2.5V LVTTL/LVCMOS

GPIO on 12-Pin Circular Connector

GPIO inputs 4 connections routed to user circuitry interface

GPIO outputs 3 connections routed to user circuitry interface

UART/USRT inputs Connection routed to user circuitry interface

UART/USRT outputs Connection routed to user circuitry interface

Feature Set


Table 2: Selected GenICam Features

Feature Description

Width Specifies the width of the image (in pixels).

Height Specifies the height of the image (in pixels).

OffsetX Specifies the horizontal image offset (in pixels).

OffsetY Specifies the vertical image offset (in pixels).

PixelFormat Specifies the format of the pixel provided by the device. Available pixel formats are:

• Monochrome pixel formats, 8 to 16 bits• Bayer pixel formats, 8 to 16 bits• RGB, 8 bits• BGR, 8 bits• YUV411_8_UYYVYY• YUV422_8_UYVY• YUV8_UYV• Truesense, 8 to 12 bits (Scf1WGWR8, Scf1WGWR10, Scf1WGWR12) Note: Early versions of the product will show the Truesense pixel formats as ScfWGWR8, ScfWGWR10, ScfWGWR12.

DeviceScanType Specifies the sensor scan type, such as areascan or linescan.

SensorDigitizationTaps Specifies the number of digitized samples output simultaneously by the camera, 1, 2 or 4 taps.

Selected GenICam Features

The iPORT NTx-GigE Embedded Video Interface supports the seven features mandated by the GigE Vision standard along with additional features, some of which are shown in the following table. The full list of features can be seen in the Device Control dialog box of Pleora’s eBUS Player application.

7About the iPORT NTx-GigE Embedded Video Interface

Chapter 3

External ConnectionsThis chapter describes the embedded video interface connections. It also includes pinouts for the GPIO, serial, FPGA, and power connector.


• “Connector Locations” on page 10

• “Mounting the Power, GPIO, and Serial Connector to an Enclosure Backplate” on page 11

• “Power, GPIO, and Serial Connections” on page 13

• “Power, GPIO, and Serial Pinouts — 12-Pin Connector on GPIO Board” on page 14

• “Power, GPIO, and Serial Pinouts — 20-Pin Connector on GigE PHY Board” on page 15

• “GPIO Routing” on page 17

• “Mapping the 12-Pin and 20-Pin Connectors to the 100-Pin User Circuitry Connector” on page 18

• “100-Pin User Circuitry Connector Pinouts” on page 19

• “NTx-Mini Adapter Board Pinout Mapping” on page 24

External Connections 9

Connector Locations

FPGA Board

J1

GPIO Board

J1

J2

GigE PHY Board

J9

J1

Table 3: Embedded Video Interface Connections

ID Location Type Description

J1 GigE PHY board

RJ-45 Ethernet connector

Interfaces the embedded video interface to Ethernet networks, as specified in IEEE 802.3.

The Ethernet interface can operate at 10, 100, or 1000 Mbps, and supports Internet Protocol Version 4 (IPv4).

If PoE is enabled, power is supplied to the camera. For more information, see “PoE Powered” on page 28.

J9 GigE PHY board

20-pin external interface

Connects to GPIO board with a 20-pin FPC cable, providing power and external signals. You can connect a 20-pin FFC cable to the GPIO board or to your own board (for example, if you need optoisolated GPIOs).

J1 GPIO board 12-pin circular connector

Provides power and external signals, such as serial communication and GPIO, to the embedded video interface.

Receives 4.7V to 16V of unfiltered DC input.

For detailed information, see “Power” on page 27.

J2 (not shown)

GigE PHY board

60-pin connector Allows communication between the FPGA board and the GigE PHY board. In the photograph above, the connector is located on the reverse side of the board.

J2 GPIO board 20-pin FFC connector

Connects to GigE PHY board with a 20-pin FPC cable.

J1 FPGA board 100-pin user circuitry interface

Interfaces directly to the camera head or other external device.

The connector is hermaphroditic, meaning the same part is used as the header and receptacle.

Samtec LSHM series 0.5mm pitch vertical 100-pin: LSHM-150-04.0-L-DV-A-N-TR.

J3 (not shown)

FPGA board 60-pin connector Allows communication between the FPGA board and the GigE PHY board. In the photograph above, the connector is located on the reverse side of the board.


Mounting the Power, GPIO, and Serial Connector to an Enclosure Backplate

The removable 12-pin power, GPIO, and serial circular connector and the corresponding GPIO board are suitable for mounting to a client-sourced enclosure.

GPIO board

12-pin connector

To mount the power, GPIO, and serial connector to an enclosure backplate

1. Insert the 12-pin connector through the external side of the backplate.

2. Secure with washer and hex nut.

3. Connect the GPIO board (12 holes) to the base pins of the 12-pin connector through the internal side of the backplate.

12-pin male connector

Insertion

Lock washer

Hex nut

GPIO board

Pins (soldered to GPIO board)

20-pin FFCEnclosure interiorBackplate of client-sourced enclosure

11External Connections

4. Assemble the 12-pin power, GPIO, and serial circular connector to the GPIO board by lining up the pins with the GPIO board.

When oriented correctly, the tab on the 12-pin connector is aligned with the small white dot on the GPIO board, as shown in the following figure. Please disregard the white numbering on the back of the GPIO board, as the pin numbers are labeled incorrectly in early versions of the product.

5. Solder the pins of the connector to the adapter board for a secure connection.

Tab

12-pin male connector

GPIO board and 12-pin male connector (assembled)

Tab location

12-pin maleconnector

When lined up properly,pin 9 and pin 1 on the 12-pin connector are inserted through

White dot

GPIO board and 12-pin male connector (assembled)

GPIO board

Line up tab betweenthe two bottom pins the bottom two pinholes


Power, GPIO, and Serial Connections

This section describes the power, GPIO, and serial connections for the embedded video interface.

GPIO Pinouts

The four GPIO inputs, three GPIO outputs, and two UART pins on the 12-pin and 20-pin connectors are routed to the 100-pin user circuitry connector. The inputs and outputs can be connected to user logic, such as level translators or optocouplers, and then routed to the NTx-GigE Embedded Video Interface GPIO signals.

If you plan to place optocouplers on the camera head, maximal isolation is determined by the design of the GPIO traces on the NTx-GigE Embedded Video Interface. The embedded video interface uses 0.5mm pitch connectors, resulting in 0.2 mm. creepage/clearance for GPIOs. This corresponds to a 63V isolation grade for Pollution Degree 1 (Pollution Degree 1: No pollution or only dry, non-conductive pollution occurs. The pollution has no influence.). To have a higher HV isolation grade, for example 500V, you should develop your own board for power and GPIO, that you can place the optocouplers on.

Serial Pinouts

The RX and TX signals are routed to the 100-pin user circuitry connector. The signals can be connected to user logic, such as a level translator and then routed to the NTx-GigE Embedded Video Interface BULK TX/RX pins.

Power Pinouts

The power pins are used when you want to use external power for the iPORT NTx-GigE Embedded Video Interface instead of PoE. The NTx-GigE Embedded Video Interface supports 4.7 to 16V input. The customer circuitry along with the NTx-GigE Embedded Video Interface can draw a maximum of 1.5A.

The NTx-GigE Embedded Video Interface requires <2.3W of external power.

Design includes reverse voltage protection, surge protection, and triple-filtering scheme on power pins, which meets class-B EMC certification without a ferrite bead on the power cable.

For more information about the NTx-GigE Embedded Video Interface power requirements, see “Power” on page 27.


Power, GPIO, and Serial Pinouts — 12-Pin Connector on GPIO Board

The power, GPIO, and serial pinout descriptions (J1 on the GPIO board) are listed in the following table.

Figure 2: 12-Pin Male Circular Connector

Tab location

Table 4: 12-Pin Circular Connector — Pinout Descriptions

Pin Name Type Notes

1 RET Power return

Power ground

2 VIN Power input Protected by 600W @ 1.0 ms PP Zener TVS, +/- 16 kV per HBM; receives 4.7V to 16V unfiltered DC input.

Reverse voltage protection circuit up to -30VDC.

3 GPIO_CONN_IN3 GPIO input Protected by ESD suppressors to IEC61000-4-2, Level 4 (+/-8 kV contact, +/-15 kV air discharge). EMI filtered by ferrite bead array BLA2ABD121SN4D (120 Ohm @ 100 MHz).

4 GPIO_CONN_OUT2 GPIO output ESD/EMI information is the same as pin 3

5 GND Ground Signal ground. Ferrite bead 0.2A, 600 Ohm @ 100 MHz to DGND of GigE PHY board.

6 GPIO_CONN_IN2 GPIO input ESD/EMI information is the same as pin 3





11 UART_CONN_TX Output ESD/EMI information is the same as pin 3. Also requires an 11 Ohm serial resistor.

12 UART_CONN_RX Input ESD/EMI information is the same as pin 3. Also requires an 11 Ohm serial resistor.

Shell GND_CHASSIS Ground For the purpose of EMI prevention, provide good electrical contact between the connector shell and the enclosure box. If you use an isolated enclosure box, connect it by wire to the GND pad (TP1 on the GPIO board).

Note: For the mapping of pins on the 12-pin circular connector and the 100-pin user circuitry connector, see “Mapping the 12-Pin and 20-Pin Connectors to the 100-Pin User Circuitry Connector” on page 18.


Power, GPIO, and Serial Pinouts — 20-Pin Connector on GigE PHY Board

The power, GPIO, and serial pinout descriptions (J9 on the GigE PHY board) are listed in the following table.

Table 5: 20-Pin Connector — Pinout Descriptions

Pin Name Type See table note...

1 RET Power ground 1



4 VIN/PWR Power input 1, 2, 3, 4, 5



7 GND/EMI_GND Signal ground 10

8 GPIO_CONN_IN0 GPIO input 6, 7, 8, 9

9 GPIO_CONN_OUT0 GPIO output 6, 7, 8, 9







16 DBG_LED0 Status LED, cathode, OC 7, 12, 13

17 3.3V Status LED, anode 7, 14

18 UART_CONN_TX Output 6, 7, 8, 9, 11

19 UART_CONN_RX Input 6, 7, 8, 9, 11

20 GND/EMI_GND Signal ground 10

1. Maximum 0.5A per pin, 1.5A per 3 pins.

2. Protected by +/-30VDC, 600W @ 1.0 ms PP Zener TVS, +/- 16 kV per HBM.

3. Reverse voltage protected, up to -30VDC.

4. You should not use 9-10 V power together with PoE. If you do, it will not damage the NTx-GigEEmbedded Video Interface, but the camera can be stacked in continuous reset mode when thepower supply switches between PoE and the wall power supply.

5. Triple filtering scheme is used to filter EMI and conduct emissions, to pass EMC class-B.

6. Protected by +/-30VDC (+/-42V clamping voltage) ESD suppressors to IEC61000-4-2, Level 4 (+/-8 kV contact, +/-15 kV air discharge).


7. EMI filtered by 120 Ohm @ 100MHz, 0.2A ferrite bead.

8. Passes to 100-pin camera head connector through interboard connectors.

9. Direction and logic of this pin is user defined by the circuitry on the camera.

10.Ferrite bead 0.2A, 600 Ohm @ 100 MHz to the GND of the GigE PHY board.

11.11-Ohm serial resistor.

12.Logical "0" (pulled-down) means that the backup load is used; logical "1" (3.3V) means that the main load is used.

13.For information about the status LED, see the description of the Power/Firmware LED in “Status LEDs” on page 51.

14.Not protected by a fuse; cannot be used as a power output.


GPIO Routing

The following image demonstrates the iPORT NTx-GigE Embedded Video Interface GPIO routing.

Your board is responsible for making the following connections:

• Connect UART_CONN_TX and UART_CONN_RX to BULK_TXn and BULK_RXn.

• Connect GPIO_CONN_OUT[2:0] to FPGA_GPIO_OUT[2:0].

• Connect GPIO_CONN_IN[3:0] to FPGA_GPIO_IN[3:0].

*An example of an adapter board is the NTx-Mini Adapter. If you are using the NTx-Mini Adapter, keep in mind the following notes:

• UART_CONN_Tx and UART_CONN_Rx are not connected to BULK_RXn and BULK_TXn, and cannot be used.

• For the BULK_RXn and BULK_TXn signals, n can be 0, 1, or 2.

• GPIO_CONN_In[3:0] is connected to FPGA_GPIO_Input[3:0] through 33R resisters.


Mapping the 12-Pin and 20-Pin Connectors to the 100-Pin User Circuitry Connector

This section describes how the pins of the 12-pin connector on the GPIO board and the 20-pin connector on the GigE PHY board are directly routed to the 100-pin user circuitry connector on the FPGA board. The use for each pin listed below is a suggestion as you can choose to use the pin for other functions.

Table 6: 12-Pin Circular Connector to 100-Pin User Circuitry Connector Mapping

NamePin on the 12-pin circular connector — GPIO Board

Pin on the 20-pin connector — GigE PHY Board

Pin on the 100-pin user circuitry connector — FPGA Board

GPIO_CONN_IN3 3 14 17

GPIO_CONN_OUT2 4 13 16






UART_CONN_TX 11 18 20

UART_CONN_RX 12 19 19

All signals in the table above are connected with the12-pin circular connector through a ferrite bead array, part number BLA2ABD121SN4D (120R@100MHz). UART pins have also serial 11Ohm resistors. There is no logic circuit because any GPIO logic must be designed on the customer board. These signals are all protected by the ESD suppressors CG0402MLC-05LG (5V, protection up to level-4 of ESD). According to an ESD suppressor specification, the maximal voltage level on this signal is 5V. The direction and function for the signal are defined by the user.

12-Pin Circular Connector Mate

The mating connector to the 12-pin power circular connector is a Hirose 12-pin connector, part number HR10A-10P-12P(73).


100-Pin User Circuitry Connector Pinouts

The following table provides the pinouts for the iPORT NTx-GigE Embedded Video Interface 100-pin user circuitry connector.

Pin 2Pin 100

Pin 99 Pin 1

All user circuitry inputs are 2.5V LVTTL.

For a mapping of PLC signals, see “PLC Programming Signals” on page 48.

Table 7: 100-Pin User Circuitry Pinouts

Pin Name Type Description

1 VCC_5V_30V PWR OUT VIN or VBUS. For more information, see “Power” on page 27.

2 VCC_5V_30V PWR OUT VIN or VBUS. For more information, see “Power” on page 27.

3 RET RET (GND) RET or GND. For more information, see “Power” on page 27.

4 RET RET (GND) RET or GND. For more information, see “Power” on page 27.

5 +2.5V PWR OUT 2.5V output. Can supply up to 0.3A.




9 1.8V N.C Not connected.

10 1.8V N.C Not connected.

11 GPIO_CONN_IN0 IN To pin 10 of 12-pin circular connector.

12 GPIO_CONN_OUT0 OUT To pin 9 of 12-pin circular connector.







18 GPIO_CONN_OUT3 N.C. Reserved GPIO.

19 UART_CONN_RX IN To pin 12 of 12-pin circular connector.

20 UART_CONN_TX OUT To pin 11 of 12-pin circular connector.

21 GND GND

22 GND GND

23 PWR_ON_RSTN INOUT, OC Power on Reset. See table note 1.

24 BULK_TX0 OUT Bulk interface 0 UART and USRT output.

25 N.C. N.C. N.C.

26 BULK_RX0 IN Bulk interface 0 UART and USRT input.

27 FPGA_GPIO_IN0 IN Connected to the Programmable Logic Controller (PLC). See table note 3.

28 BULK_CLK0 OUT Bulk interface 0 USRT output clock.

29 FPGA_GPIO_IN1 IN Connected to the PLC. See table note 3.





34 BULK_CLK1 OUT Bulk interface 1 USRT output clock.

35 FPGA_GPIO_OUT0 OUT Connected to the PLC.





40 BULK_CLK2 OUT Bulk interface 2 USRT clock.

41 FPGA_GPIO_OUT3 N.C Reserved GPIO.

42 GND GND

Table 7: 100-Pin User Circuitry Pinouts (Continued)



43 FPGA_SEL INOUT OC/N.C. Selection of FPGA load. See table note 2.

This signal has been added to ensure consistency with earlier Pleora products, such as the iPORT NTx-Mini Embedded Video Interface. For newer products, leave it N.C.

44 PB0_CLK IN Pixel bus clock.

45 GND GND

46 PB0_CLK_IN IN For future use. Connect to ground.

47 PB0_DATA0 IN Pixel bus data 0. See important warning in table note 4.

48 GND GND



51 PB0_GND GND



54 GND GND



57 GND GND



60 GND GND



63 PB0_CTRL_OUT0 OUT Connected to the PLC.






69 GND GND






Note: For the mapping of pins on the 12-pin circular connector and the 100-pin user circuitry connector, see “Mapping the 12-Pin and 20-Pin Connectors to the 100-Pin User Circuitry Connector” on page 18.

72 GND GND



75 PB0_FVAL IN Pixel bus frame valid.



78 PB0_DVAL IN Pixel bus data valid.



81 GND GND



84 GND GND



87 PB0_MVAL IN Pixel bus chunk data valid.



90 PB0_LVAL IN Pixel bus line valid.



93 GND GND



96 GND GND


98 N.C. N.C. N.C.

99 GND GND

100 GND GND




Table Notes:

1. PWR_ON_RSTN is a bidirectional open collector pin with a 10Kohm resistor to 3.3V on theFPGA board. This signal is high when power on the NTx-GigE Embedded Video Interface is at the appropriate levels. You can leave this set to N.C.; or connect with the power ready signal of the usercircuitry; or use it to start configuration of user devices, such as FPGAs or CPUs; or use it to initiate a reset of the FPGA on the NTx-GigE Embedded Video Interface.

2. FPGA_SEL selects the FPGA load to be used. Setting this pin high (1) runs the main load; low (0)forces the backup (factory) load. The FPGA board provides a 1Kohm pull-up to 2.5V and a DIPswitch to GND (normally off). You can leave this pin set to N.C. (recommended); or monitor theload used; or force the backup load by setting the DIP switch to GND or by using an open-collector signal.

3. If you do not use this GPIO input (FPGA_GPIO_IN), we recommend that you tie it to GNDinstead of leaving it not connected.

4. IMPORTANT: If your electronics output 3.0V or 3.3V, place a 33 ohm serial resistor between thePB0_DATA inputs on the 100-pin user circuitry connector and your electronics to avoid damageto the FPGA.


NTx-Mini Adapter Board Pinout Mapping

This section describes how the signals from the FPGA board are directly routed to the 60-pin FFC/FPC connector on the NTx-Mini Adapter board. This board is intended to help you evaluate the NTx-GigE with an existing camera connected to an iPORT NTx-Mini Embedded Video Interface.

Table 8: 60-Pin FFC/FPC Connector to FPGA Board

Signal on FPGA board NTx-Mini Embedded Video Interface 60-pin connector

Name Pin Name

2.5V 1 2.5V

2.5V 2 VCCIO

VIN 3 CAMERA_VIN

VIN 4 CAMERA_VIN

FPGA_SEL0 5 FPGA_SEL0

N.C (See notes 1 and 2) 6 FPGA_SEL1

PWR_ON_RST 7 PWR_ON_RST#

GND 8 GND

PB0_DATA0 (See note 1) 9 PIXEL_DATA0










GND 19 GND












GND 30 GND





PB0_MVAL (See note 1) 35 SPARE

PB0_LVAL (See note 1) 36 LVAL

PB0_FVAL (See note 1) 37 FVAL

PB0_DVAL (See note 1) 38 DVAL

BULK_RX2 (See note 1) 39 SERTTFG

BULK_TX2 (See note 1) 40 SERTC

GND 41 GND

PB0_CTRL_OUT0 (See note 1) 42 CC1




BULK_RX0 (See note 1) 46 BULK0_RXD

BULK_TX0 (See note 1) 47 BULK0_TXD

Reserved 48 BULK0_CLK

BULK_RX1 (See note 1) 49 UART1_RXD

BULK_TX1 (See note 1) 50 UART1_TXD

PB0_DATA24 (See note 1) 51 Reserved

GND 52 GND



PB0_DATA29 55 Reserved

PB0_DATA28 56 OUT_CLK0

PB0_CLK (See note 1) 57 PIXEL_CLK

Table 8: 60-Pin FFC/FPC Connector to FPGA Board (Continued)


Name Pin Name


1. These signals are connected to the FPGA board through 33R resisters.

2. To test a 32-bit wide pixel bus you can do the following:

a. On the adapter board, wire pin 26 on the J3 connector (30-pin) (which is not populated) to pin 6 on the J4 connector (60-pin).

b. Connect PB0_DATA27 from camera to pin 6 of the 60 pin connector.

Reserved 58 Reserved



Table 8: 60-Pin FFC/FPC Connector to FPGA Board (Continued)


Name Pin Name


Chapter 4

PowerThis chapter describes how the iPORT NTx-GigE Embedded Video Interface product variants receive, distribute, and use power.


• “Power Considerations” on page 28

• “PoE Powered” on page 28

• “Externally Powered” on page 28

• “Power Input Signals” on page 29

• “Output Power Signals” on page 29

• “Power Consumption” on page 30

Power 27

Power Considerations

The NTx-GigE Embedded Video Interface can be powered through the 12-pin circular connector or using Power over Ethernet (PoE). If both options are connected at the same time, the following one will be used:

• If VIN < 9V and PoE is supplied, the embedded video interface will be powered by PoE.

• If VIN > 10V and PoE is supplied, the PoE will be off and the embedded video interface will be powered by VIN (10-16V, 1.5A maximum).

• Important: 9V < VIN < 10V is outside of the recommended voltage range and may cause undetermined behavior.

Figure 3: NTx-GigE Embedded Video Interface Power Circuitry

PoE Powered

PoE supports 7W maximum. The NTx-GigE Embedded Video Interface uses a maximum of 2.5W. As a result, 4.5W at 12V is available for the camera head. The embedded video interface uses isolated PoE circuitry.

Externally Powered

When external power is supplied to the iPORT NTx-GigE Embedded Video Interface, the embedded video interface and user circuitry are powered from the 12-pin circular connector. Filtering, protection, and regulation circuitry can support up to 1.5A and 16V.

When using PoE, we recommend power of 4.7-9V or 10-16V.


Power Input Signals

The section determines the input current requirements.

The following tables list the input power signals for the NTx-GigE Embedded Video Interface.

Table 9: NTx-GigE Power Input Signals from the Power and GPIO Connector

Name Volts (V) Notes

VIN 4.7 - 16V* Efficiency of power circuitry (including drops on Schottky diodes) is flat in this range.

Unfiltered DC power from an external power supply through the 12-pin Hirose connector. Reverse voltage protected, up to -30 VDC.

The NTx-GigE Embedded Video Interface generates all internal power rails from the VIN signal. A resident common mode filter allows the input to be unfiltered, directly from a switching wall plug power supply. Maximal current is 1.5A, limited by filtering circuitry.

RET Ground Ground for VIN

GND Ground 0 volts relative to other voltages on the NTx-GigE Embedded Video Interface.

Output Power Signals

The following table contains the output power signals for the NTx-GigE Embedded Video Interface.

Table 10: NTx-GigE Power Output Signals to the 100-pin User Circuitry Connector

Name Volts (V) Current (A) Notes

VCC_5_30V 4.2 - 16V* Up to 1.5A Filtered VIN from wall power supply or from PoE.

2.5V 2.5V+/-5% 0.35A 2.5V is generated by a switcher connected to 3.3V.

2.5V is available for user circuitry.

Can supply up to 300 mA.

GND Ground N/A 0 volts relative to other voltages on the NTx-GigE Embedded Video Interface.

* When used as an output, the VIN voltage will match the input PWR voltage, minus the drop on the Schottky diode (maximum 0.49V).

29Power

Power Consumption

The following table outlines the power consumption of the NTx-GigE Embedded Video Interface.

The following table lists typical values measured during characterization, but are not guaranteed.

Table 11: Power Consumption

Power supply source Streaming rate Power (watts) Power current (A)

GPIO @ 5V Idle TBD TBD

400 Mbps TBD TBD

950 Mbps TBD TBD

GPIO @ 12V Idle 1.9 0.16

400 Mbps TBD TBD

950 Mbps 2.1 0.18

100-pin user circuitry connector @3.3V

Idle 2 0.61

400 Mbps TBD TBD

950 Mbps TBD TBD

PoE 48V Idle TBD TBD

400 Mbps TBD TBD

950 Mbps TBD TBD

PoE 56V Idle 3.4 0.06

400 Mbps TBD TBD

800 Mbps TBD TBD


Chapter 5

Thermal RequirementsThis chapter provides you with the information you need to ensure the optimal operating temperature for your NTx-GigE Embedded Video Interface.

You should store the NTx-GigE Embedded Video Interface at temperatures between -40° to +85°C.

Thermal Requirements 31

Ambient and Junction Temperatures

The following table outlines the components that consume the largest amount of power on the NTx-GigE Embedded Video Interface and that will therefore be most affected by high temperatures. If you are designing a product to operate at, or above, 85° C, you must provide a method to cool these components using a heat sink or thermal pad.

Table 12: NTx-GigE Embedded Video Interface Thermal Guidelines

Reference designator Description Rating for component on standard Pleora product

U2 GigE PHY Board Marvel PHY - 88E1510

Ambient: 0° to +70° C

Junction: 0° to +125°

Power consumption: ~ 450mW

U2 FPGA Board Samsung DDR3

K4B1G1646G-BCH9000

Ambient: 0° to +95° C

Junction: Not specified

Case: 0° to +95° C


U1 FPGA Board Altera FPGA

5CEFA4U19C8N

Ambient: not specified

Junction: 0° to +85° C



Chapter 6

Bulk InterfacesThis chapter describes the NTx-GigE Embedded Video Interface bulk interfaces and the supported protocols.


• “Bulk Interfaces and Supported Protocol” on page 34

• “UART/USRT Interface” on page 35

• “Supported USRT Clock Frequencies and Periods” on page 35

• “GenICam Interface for Serial Communication Configuration” on page 36

Bulk Interfaces 33

Bulk Interfaces and Supported Protocol

The NTx-GigE Embedded Video Interface has three Bulk interface ports available for serial communication. Each port supports the standard UART (Universal Asynchronous Receiver/Transmitter) and USRT (Universal Synchronous/Asynchronous Receiver/Transmitter) protocols. A UART/USRT interface consists of two port signals: TX and RX. The USRT interface also has a clock (CLK) signal, which is used to maintain synchronization between the receiver/transmitter. In the NTx-GigE Embedded Video Interface, the three Bulk interface ports are available on the 100-pin user circuitry connector.

The following table shows the connector pinout information for the Bulk interface port signals.

Table 13: NTx-GigE Embedded Video Interface Bulk Interface Signals and Connector Pinouts

Bulk signal names 100-pin user circuitry connector pin number

BULK_TX0 24

BULK_RX0 26

BULK_CLK0 28

BULK_TX1 30

BULK_RX1 32

BULK_CLK1 34

BULK_TX2 36

BULK_RX2 38

BULK_CLK2 40

GND See “100-Pin User Circuitry Connector Pinouts” on page 19.

The Bulk interfaces on the NTx-GigE Embedded Video Interface are 2.5V IOs.


UART/USRT Interface

The NTx-GigE Embedded Video Interface UART/USRT interface supports:

• 8-bit data transfer

• 1 start bit

• Programmable stop bit(s): 1 or 2

• Parity: even, odd, or none

• Baud rates (UART only):

• Predefined rates: 9600, 14400, 19200, 28800, 38400, 57600, 115200

• Programmable

• Loop back mode from downstream to upstream

Supported USRT Clock Frequencies and Periods

The following table lists the supported USRT clock frequencies and periods.

Table 14: Supported Clock Frequencies and Periods

Bulk system clock divider Clock period, tSCK (ns) Clock frequency (MHz)*

By 2 60 16.667

By 4 120 8.333

By 8 240 4.167

By 16 480 2.083

By 32 960 1.042

By 64 1920 0.521

By 128 3840 0.260

By 256 7680 0.130

* To obtain the exact frequency, divide the 33.333 MHz clock speed by one of: 2, 4, 8, 16, 32, 64, 128, or 256.

35Bulk Interfaces

GenICam Interface for Serial Communication Configuration

The following GenICam features are available for serial communication configuration.

Table 15: GenICam Features Available for Serial Communication

Feature Description

BulkSelector Selects Bulk0, Bulk1 or Bulk2 for configuration.

BulkMode UART/USRT protocol.

BulkSystemClockDivider Defines the frequency of the USRT output clock. The actual frequency produced is equal to the system clock frequency divided by the factor set by this feature. Available dividers are 2, 4, 8, 16, 32, 64, 128, and 256.

BulkOutputClockFrequency Represents the frequency of the USRT output clock controlled by the BulkSystemClockDivider.

BulkLoopback Loops back downstream data to upstream direction (loops the data back to the computer).

BulkNumOfStopBits Selects a stop bit option (either 1 or 2).

BulkParity Selects a parity option (None, Even, or Odd).

BulkUpstreamFifoWatermark Sets the level of upstream FIFO at which a GigE Vision event is generated.


Chapter 7

Pixel Bus Definitions and TimingThis chapter describes the interface responsible for transmitting data from the camera to the NTx-GigE Embedded Video Interface.


• “Pixel Bus Definitions” on page 38

• “Pixel Bus Timing” on page 43

• “Pixel Bus Signals” on page 44

• “Timing Values for all Cases” on page 46

Pixel Bus Definitions and Timing 37

Pixel Bus Definitions

The tables in this section provide the iPORT NTx-GigE Embedded Video Interface pixel bus definitions.

Mono/RGB/Truesense

Table 16: Mono/RGB/Truesense Pixel Bus Definitions

Mono8 / Bayer_8/Truesense

Mono10 / Bayer/

Truesense

Mono12 / Bayer/

Truesense

Mono14 / Bayer

Mono16 / Bayer

BGR8 RGB8

Tap Bit Tap Bit Tap Bit Tap Bit Tap Bit Component Bit Component Bit

PB0_Data 0 0 0 0 0 0 0 0 0 0 0 B0 0 R0 0

PB0_Data 1 0 1 0 1 0 1 0 1 0 1 B1 1 R1 1

PB0_Data 2 0 2 0 2 0 2 0 2 0 2 B2 2 R2 2

PB0_Data 3 0 3 0 3 0 3 0 3 0 3 B3 3 R3 3

PB0_Data 4 0 4 0 4 0 4 0 4 0 4 B4 4 R4 4

PB0_Data 5 0 5 0 5 0 5 0 5 0 5 B5 5 R5 5

PB0_Data 6 0 6 0 6 0 6 0 6 0 6 B6 6 R6 6

PB0_Data 7 0 7 0 7 0 7 0 7 0 7 B7 7 R7 7

PB0_Data 8 1 0 0 8 0 8 0 8 0 8 G0 0 G0 0

PB0_Data 9 1 1 0 9 0 9 0 9 0 9 G1 1 G1 1

PB0_Data 10 1 2 - nc 0 10 0 10 0 10 G2 2 G2 2

PB0_Data 11 1 3 - nc 0 11 0 11 0 11 G3 3 G3 3

PB0_Data 12 1 4 1 8 1 8 0 12 0 12 G4 4 G4 4

PB0_Data 13 1 5 1 9 1 9 0 13 0 13 G5 5 G5 5

PB0_Data 14 1 6 - nc 1 10 - nc 0 14 G6 6 G6 6

PB0_Data 15 1 7 - nc 1 11 - nc 0 15 G7 7 G7 7

PB0_Data 16 2 0 1 0 1 0 - nc - nc R0 0 B0 0

PB0_Data 17 2 1 1 1 1 1 - nc - nc R1 1 B1 1

PB0_Data 18 2 2 1 2 1 2 - nc - nc R2 2 B2 2

PB0_Data 19 2 3 1 3 1 3 - nc - nc R3 3 B3 3

PB0_Data 20 2 4 1 4 1 4 - nc - nc R4 4 B4 4

PB0_Data 21 2 5 1 5 1 5 - nc - nc R5 5 B5 5

PB0_Data 22 2 6 1 6 1 6 - nc - nc R6 6 B6 6

PB0_Data 23 2 7 1 7 1 7 - nc - nc R7 7 B7 7


YUV411_8_UYYVYY - 1 Tap

Table 17: YUV411_8_UYYVYY - 1 Tap Pixel Bus Definitions

Clock 1 Clock 2 Clock 3 Clock 4

Component Bit Component Bit Component Bit Component Bit

PB0_Data 0 Y11 0 Y11 4 Y13 0 Y13 4

PB0_Data 1 Y11 1 Y11 5 Y13 1 Y13 5

PB0_Data 2 Y11 2 Y11 6 Y13 2 Y13 6

PB0_Data 3 Y11 3 Y11 7 Y13 3 Y13 7

PB0_Data 4 U11 0 Y12 0 V11 0 Y14 0

PB0_Data 5 U11 1 Y12 1 V11 1 Y14 1

PB0_Data 6 U11 2 Y12 2 V11 2 Y14 2

PB0_Data 7 U11 3 Y12 3 V11 3 Y14 3

PB0_Data 8 U11 4 Y12 4 V11 4 Y14 4

PB0_Data 9 U11 5 Y12 5 V11 5 Y14 5

PB0_Data 10 U11 6 Y12 6 V11 6 Y14 6

PB0_Data 11 U11 7 Y12 7 V11 7 Y14 7

PB0_Data 12 through to PB0_Data 31

- - - - - - - -

PB0_Data 24 3 0 - nc - nc - nc - nc - nc - nc








Table 16: Mono/RGB/Truesense Pixel Bus Definitions (Continued)

Mono8 / Bayer_8/Truesense

Mono10 / Bayer/

Truesense

Mono12 / Bayer/

Truesense

Mono14 / Bayer

Mono16 / Bayer

BGR8 RGB8

Tap Bit Tap Bit Tap Bit Tap Bit Tap Bit Component Bit Component Bit

39Pixel Bus Definitions and Timing

Table 18: YUV411_8_UYYVYY - 2 Tap Pixel Bus Definitions



PB0_Data 0 Y11 0 Y13 0 Y15 0 Y18 0

PB0_Data 1 Y11 1 Y13 1 Y15 1 Y18 1

PB0_Data 2 Y11 2 Y13 2 Y15 2 Y18 2

PB0_Data 3 Y11 3 Y13 3 Y15 3 Y18 3

PB0_Data 4 U11 0 V11 0 U15 0 V16 0

PB0_Data 5 U11 1 V11 1 U15 1 V16 1

PB0_Data 6 U11 2 V11 2 U15 2 V16 2

PB0_Data 7 U11 3 V11 3 U15 3 V16 3

PB0_Data 8 U11 4 V11 4 U15 4 V16 4

PB0_Data 9 U11 5 V11 5 U15 5 V16 5

PB0_Data 10 U11 6 V11 6 U15 6 V16 6

PB0_Data 11 U11 7 V11 7 U15 7 V16 7

PB0_Data 12 Y11 4 Y13 4 Y15 4 Y18 4

PB0_Data 13 Y11 5 Y13 5 Y15 5 Y18 5

PB0_Data 14 Y11 6 Y13 6 Y15 6 Y18 6

PB0_Data 15 Y11 7 Y13 7 Y15 7 Y18 7

PB0_Data 16 Y12 0 Y14 0 Y17 0 Y19 0

PB0_Data 17 Y12 1 Y14 1 Y17 1 Y19 1

PB0_Data 18 Y12 2 Y14 2 Y17 2 Y19 2

PB0_Data 19 Y12 3 Y14 3 Y17 3 Y19 3

PB0_Data 20 Y12 4 Y14 4 Y17 4 Y19 4

PB0_Data 21 Y12 5 Y14 5 Y17 5 Y19 5

PB0_Data22 Y12 6 Y14 6 Y17 6 Y19 6

PB0_Data 23 Y12 7 Y14 7 Y17 7 Y19 7


- - - - - - - -

YUV411_8_UYYVYY - 2 Tap


YUV422_8_UYVY

Table 19: YUV422_8_UYVY Pixel Bus Definitions



PB0_Data 0 U11 0 V11 0 U13 0 V13 0

PB0_Data 1 U11 1 V11 1 U13 1 V13 1

PB0_Data 2 U11 2 V11 2 U13 2 V13 2

PB0_Data 3 U11 3 V11 3 U13 3 V13 3

PB0_Data 4 U11 4 V11 4 U13 4 V13 4

PB0_Data 5 U11 5 V11 5 U13 5 V13 5

PB0_Data 6 U11 6 V11 6 U13 6 V13 6

PB0_Data 7 U11 7 V11 7 U13 7 V13 7

PB0_Data 8 Y11 0 Y12 0 Y13 0 Y14 0

PB0_Data 9 Y11 1 Y12 1 Y13 1 Y14 1

PB0_Data 10 Y11 2 Y12 2 Y13 2 Y14 2

PB0_Data 11 Y11 3 Y12 3 Y13 3 Y14 3

PB0_Data 12 Y11 4 Y12 4 Y13 4 Y14 4

PB0_Data 13 Y11 5 Y12 5 Y13 5 Y14 5

PB0_Data 14 Y11 6 Y12 6 Y13 6 Y14 6

PB0_Data 15 Y11 7 Y12 7 Y13 7 Y14 7


- - - - - - - -

YUV8_UYV

Table 20: YUV8_UYV Pixel Bus Definitions

Clock 1 Clock 3

Component Bit Component Bit

PB0_Data 0 U11 0 U12 0

PB0_Data 1 U11 1 U12 1

PB0_Data 2 U11 2 U12 2

PB0_Data 3 U11 3 U12 3

PB0_Data 4 U11 4 U12 4

PB0_Data 5 U11 5 U12 5


PB0_Data 6 U11 6 U12 6

PB0_Data 7 U11 7 U12 7

PB0_Data 8 Y11 0 Y12 0

PB0_Data 9 Y11 1 Y12 1

PB0_Data 10 Y11 2 Y12 2

PB0_Data 11 Y11 3 Y12 3

PB0_Data 12 Y11 4 Y12 4

PB0_Data 13 Y11 5 Y12 5

PB0_Data 14 Y11 6 Y12 6

PB0_Data 15 Y11 7 Y12 7

PB0_Data 16 V11 0 V12 0

PB0_Data 17 V11 1 V12 1

PB0_Data 18 V11 2 V12 2

PB0_Data 19 V11 3 V12 3

PB0_Data 20 V11 4 V12 4

PB0_Data 21 V11 5 V12 5

PB0_Data22 V11 6 V12 6

PB0_Data 23 V11 7 V12 7


- - - -

Table 20: YUV8_UYV Pixel Bus Definitions (Continued)

Clock 1 Clock 3

Component Bit Component Bit


Pixel Bus Timing

The NTx-GigE Embedded Video Interface Pixel Bus transmits data from the camera to the embedded video interface in a format similar to deserialized Camera Link Standard data, as shown in the following image.

Table 21: Sub-clock Delays on the Camera Interface

Parameter Symbol Minimum Maximum Notes

PB0_CLK high-level width tCH 4.1 ns N/A N/A

PB0_CLK low-level width tCL 4.1 ns N/A N/A

PB0_CLK frequency fCP 20 MHz 120 MHz N/A

PB0_CLK clock period tCP 8.3 ns N/A N/A

PB0_DATAx setup time tDS 2 ns N/A By design

PB0_DATAx hold time tDH 2 ns N/A By design

PB0_CTRL_OUTx pulse width tCCP 30 ns N/A


Pixel Bus Signals

The output of the camera must match the format of the NTx-GigE Embedded Video Interface. You should select a case for your application and then refer to “Timing Values for all Cases” on page 46.

Case 1: FVAL and LVAL are Level-Sensitive

Case 2: FVAL and LVAL are Edge-Sensitive

When FVAL is edge sensitive, a rising edge (when rising-edge sensitive), or a falling edge (when falling-edge sensitive) signals the start of a frame. The frame ends either when all of the pixels have been acquired (as set in the image height and width settings) or the next FVAL valid edge (rising edge when rising-edge sensitive, or a falling edge when falling-edge sensitive) occurs. If the next FVAL valid edge occurs before all of the pixels have been acquired, the NTx-GigE Embedded Video Interface generates a Line Missing status or a Partial Line Missing error.


Case 3: FVAL is Edge-Sensitive and LVAL is Level-Sensitive

When LVAL is edge sensitive, a rising edge (when rising-edge sensitive) or a falling edge (when falling-edge sensitive) signals the start of a new line. The end of the line occurs either once all the pixels have been acquired (as set in the image width settings) or the next LVAL valid edge (rising edge when rising-edge sensitive or a falling edge when falling-edge sensitive) occurs. If the next LVAL valid edge occurs before all the pixels of a line have been acquired the NTx-GigE Embedded Video Interface generates a Partial Line Missing error.


Timing Values for all Cases

The TCP (PB0_CLK period) timing values stated in the following table are minimum values only.

Table 22: TCP Timing Values for All Cases

From To SymbolCase 1 (level) (tcp)

Case 2 (edge) (tcp)

Case 3 (both) (tcp)

FVAL valid LVAL valid a tFV2LV 0 b 0 1

FVAL valid Data valid a,c,d tFV2DV 0 b 16 f 1

LVAL valid Data valid a,c,d tLV2DV 0 1 0

LVAL valid LVAL invalid a tLV2LI 1 1 1

LVAL invalid LVAL valid a tLI2LV 1 1 1

LVAL invalid (Automatic Internal Re-trigger disabled)

Data valid a,c,d tLI2DV 1 N/A 1

LVAL invalid (Automatic Internal Re-trigger enabled)

Data valid tLI2DV 16 f N/A 16 f

Data invalid LVAL invalid a,c,d

tDI2LI 0 N/A 0

LVAL invalid FVAL invalid a tLI2FI 0 e N/A N/A

Data invalid FVAL invalid a,c,d

tDI2FI 0 e N/A N/A

FVAL invalid FVAL valid a tFI2FV 1 1 1

FVAL invalid Data valid a,c,d tFI2DV 1 N/A N/A

Last LVAL invalid Data valid tLLI2DV 16 f N/A 16 f

FVAL valid FVAL invalid tFV2FI 16 f 1 1

FVAL valid FVAL valid t2FV2FV 17 f 17 f 17 f

a. The valid state of FVAL and LVAL is high when they are set as level-high sensitive or rising-edgesensitive. Their valid state is low when they are set as level-low sensitive or falling-edge sensitive.

b. If LVAL is valid before FVAL becomes valid, the grabber drops the full line.

c. Data valid is defined by FVAL valid (note a), LVAL valid (note a), and DVAL valid (note e).

d. The valid state of DVAL is high when it is set as level-high sensitive, and low when set as level-lowsensitive. DVAL is always valid in the grabber when the parameter PixelBusDataValidEnabled is off.

e. If FVAL becomes invalid and LVAL is still valid, the line is truncated.

f. This is a worst-case value. Subtract 3 cycles if the pixel type is 8-bit, 1-tap. Subtract 1 cycle for allother pixel types except 10/12- bit, 2-tap, unpacked, and RGB unpacked. Subtract up to 7 cycles ifthe image size is a multiple of 32 bytes.


Chapter 8

Signal HandlingThe NTx-GigE Embedded Video Interface includes a programmable logic controller (PLC) that lets you control external machines and react to inputs. By controlling your system using the PLC, you can make functional changes, adjust timing, or add features without having to add new hardware.

Signal Handling 47

PLC Programming Signals

For an introduction to the PLC and for detailed information about how PLC signals are handled, see the iPORT Advanced Features User Guide, available on the Pleora Support Center at www.pleora.com.

The following table lists the PLC input and output programming signals that are specific to the iPORT NTx-GigE Embedded Video Interface, and indicates the pins on which they are available.

Table 23: PLC Signal Usage

Signal name PLC equation usage Associated pin

Pb0Fval Input Pin 75 on the 100-pin user circuitry connector

Pb0Lval Input Pin 90 on the 100-pin user circuitry connector

Pb0Dval Input Pin 78 on the 100-pin user circuitry connector

Pb0Spare Input Pin 87 on the 100-pin user circuitry connector

GpioIn0 Input Pin 10 on the 12-pin circular connector




BufferWM0 Input No associated pin

Grb0AcqActive Input No associated pin

PlcCtrl0 Input No associated pin




Pb0CC0 Input, output Pin 63 on the 100-pin user circuitry connector




GpioOut0 Input, output Pin 9 on the 12-pin circular connector



PlcFval0 Input, output No associated pin

PlcLval0 Input, output No associated pin

PlcMval0 Input, output No associated pin


http://www.pleora.com

PlcTrig0 Input, output No associated pin

PlcTimestampCtrl Input, output No associated pin

Timer0Trig Input, output No associated pin

Timer0Out Input No associated pin

Timer1Trig Input, output No associated pin

Timer1Out Input No associated pin

Counter0Reset Input, output No associated pin

Counter0Inc Input, output No associated pin

Counter0Dec Input, output No associated pin

Counter0Eq Input No associated pin

Counter0Gt Input No associated pin

Counter1Reset Input, output No associated pin

Counter1Inc Input, output No associated pin

Counter1Dec Input, output No associated pin

Counter1Eq Input No associated pin

Counter1Gt Input No associated pin

Rescaler0In Input, output No associated pin

Rescaler0Out Input No associated pin

Delayer0In Input, output No associated pin

Delayer0Out Input No associated pin

Event0 Input, output No associated pin




ActionTrig0 Input No associated pin

ActionTrig1 Input No associated pin

Table 23: PLC Signal Usage (Continued)

Signal name PLC equation usage Associated pin

49Signal Handling

Chapter 9

Status LEDsThe status LEDs indicate the operating status of the embedded video interface’s network connection and firmware. The following figure and table describe the status LEDs.

Power and Firmware Status LED (D1)

Network ActivityLED (J1)

Network ConnectionSpeed LED (J1)

Status LEDs 51

Table 24: Status LEDs

LED ID Description

Power/Firmware D1 Off. FPGA not configured.

Green. FPGA is configured.

Yellow. The backup load is running.

Note: The LED on the GPIO board (D1) also shows this status.

Network Activity J1 Off. No Ethernet connection.

Green on. Ethernet link.

Green on blinking. Data is being transmitted or received.

Network Connection Speed

J1 Off. No connection, 10 Mbps connection, or 100 Mbps connection.

Green on. 1 Gbps connection.


Chapter 10

Installing the eBUS SDKThis chapter describes how to install the eBUS SDK, and also provides information about installing the required driver.

Before you can configure and control your embedded video interface, you must install the eBUS SDK.


• “Installing the eBUS SDK” on page 54

• “Installing the Driver and Configuring the NIC” on page 54

Installing the eBUS SDK 53

Installing the eBUS SDK

You can install the Pleora eBUS SDK on your computer to configure and control your embedded video interface. Consult the eBUS Player Quick Start Guide or eBUS Player User Guide for information about setting up and configuring your camera for connection to the embedded video interface.

The Pleora Technologies eBUS SDK contains an extensive library of sample applications, with source code, to create working applications for device configuration and control, image and data acquisition, and image display and diagnostics.

It is possible for you to configure the embedded video interface and GigE Vision compliant video sources using other GenICam compliant software, however, this guide provides you with the instructions you need to use the Pleora eBUS Player application.

To learn more about the features that are available in the eBUS SDK, along with details on creating applications for device configuration and control, image and data acquisition, and image display and diagnostics, see the eBUS SDK Programmer’s Guide on the Pleora Support Center (www.pleora.com).

Installing the Driver and Configuring the NIC

Before you can configure the embedded video interface, use the Driver Installation Tool (included with the eBUS SDK) to install the correct driver. Then, set up your NIC.

To install a Pleora driver

1. Click Start > All Programs > Pleora Technologies Inc > eBUS SDK > Tools > eBUS Driver Installation Tool.

2. Under GigE Vision, click Install.

After a moment the driver installs and the driver status changes to Installed. The driver is installed across all network adapters on your computer.

3. Close the eBUS Driver Installation Tool.



You may be required to restart your computer.

To see the versions of the installed drivers, click Help > About.

To configure an IP address for the NIC

1. In the Windows Control Panel, click Network and Internet.

The instructions in this procedure are based on the Windows 7 operating system. The steps may vary depending on your computer’s operating system.

2. Click Network and Sharing Center.

55Installing the eBUS SDK

3. In the left-hand panel, click Change adapter settings.

4. Right-click the NIC and then click Properties.

5. Click Internet Protocol Version 4 (TCP/IPv4) and then click Properties.


6. Select Obtain an IP address automatically or Use the following IP address to give the NIC an IP address.

7. Close the open dialog boxes to apply the changes and close the Control Panel.

57Installing the eBUS SDK

8. Configure the NIC for jumbo packets (more often referred to as jumbo frames) and set the NIC’s Rx Descriptor to the maximum available value. Using jumbo packets allows you to increase system performance. However, you must ensure your NIC and GigE switch (if applicable) support jumbo packets.

To complete this task, right-click the NIC and click Properties. Then, click Configure. The exact configuration procedure, as well as the jumbo packet size limit, depends on the NIC.


Chapter 11

Connecting to the Embedded Video Interface and Configuring General Settings

After you have connected to the embedded video interface, you can provide it with a unique IP address on your network. When a connection is established, start eBUS Player and connect to the embedded video interface. Then you can configure its image settings to ensure images are received and displayed properly. You can also configure the buffer options to reduce the likelihood of lost packets.

eBUS Player is documented in more detail in the eBUS Player Quick Start Guide and the eBUS Player User Guide. The iPORT NTx-GigE Embedded Video Interface User Guide provides you with the eBUS Player instructions and overviews required to set up and configure the embedded video interface.


• “Connecting the Ethernet Cables and Confirming Image Streaming” on page 60

• “Configuring the Buffers” on page 61

• “Providing the Embedded Video Interface with an IP Address” on page 62

• “Configuring the Embedded Video Interface’s Image Settings” on page 63

• “Implementing the eBUS SDK” on page 65

Connecting to the Embedded Video Interface and Configuring General Settings 59

Connecting the Ethernet Cables and Confirming Image Streaming

The embedded video interface can communicate with your computer using either a direct connection or by connecting to a GigE switch. This section explains how to connect the embedded video interface to a GigE switch to confirm that images are streaming.

To connect the Ethernet cables and apply power

1. Connect the embedded video interface to the RJ-45 Ethernet connector on your computer’s NIC or a GigE switch.

2. Apply power.

To start eBUS Player and connect to a device

1. Start eBUS Player from the Windows Start menu.

2. Click Select/Connect.

If the device does not appear in the list, click the Show unreachable Network Devices check box to show all devices.

3. In the Device Selection dialog box, click the embedded video interface.

If the IP address is not valid, a warning ( ) appears in the Device Selection dialog box. Provide the device with an IP address, as outlined in “Providing the Embedded Video Interface with an IP Address” on page 62.

4. Click OK.

eBUS Player is now connected to the device.

To confirm image streaming

1. Click Play to stream live images or the test pattern.

2. After you confirm that images are streaming, click Stop.

If images do not stream, see the tips provided in “System Troubleshooting” on page 79.


Configuring the Buffers

You can increase the buffer count in eBUS Player to reduce the impact and likelihood of lost and out-of-order packets, and to make streaming more robust. A high number of buffers are needed in high frame rate applications, while a small number of buffers are needed for lower frame rates. Applications using a high number of buffers might experience greater latency.

To configure the buffers

1. Start eBUS Player and connect to the embedded video interface.

For more information, see “To start eBUS Player and connect to a device” on page 60.

2. Click Tools > Buffer Options.

3. Click the buffer option that suits your requirements.

4. Click OK.

Default size for streaming is 16 buffers.

61Connecting to the Embedded Video Interface and Configuring General Settings

Providing the Embedded Video Interface with an IP Address

The embedded video interface requires an IP address to communicate on a video network. This address must be on the same subnet as the computer that is performing the configuration and receiving the image stream.

To provide the embedded video interface with an IP address

1. Start eBUS Player.

2. Click Select/Connect.

3. Click the embedded video interface.

4. Click Set IP Address.

5. Provide the embedded video interface with a valid IP address and subnet mask. You can optionally provide a default gateway.

If you are using a unicast network configuration, the management entity/data receiver and the embedded video interface must be on the same subnet. The unicast network configuration is outlined in “Unicast Network Configuration” on page 68.

6. Click OK to close the Set IP Address dialog box.

7. Click OK to close the Device Selection dialog box and connect to the device.

Configuring an Automatic/Persistent IP Address

The Device Control dialog box allows you to configure a persistent IP address for the embedded video interface. Alternatively, the embedded video interface can be configured to automatically obtain an IP address using Dynamic Host Configuration Protocol (DHCP) or Link Local Addressing (LLA). The embedded video interface uses its persistent IP address first, but if this option is set to False, it can be configured to attempt to obtain an address from a DHCP server. If this fails, it will use LLA to find an available IP address. LLA cannot be disabled and is always set to True.

To configure a persistent IP address



2. Under Parameters and Controls, click Device control.

3. Under TransportLayerControl, set the GevCurrentIPConfigurationPersistentIP feature to True.

4. Set the GevPersistentIPAddress feature to a valid IP address in the GevPersistentIPAddress field.

5. Set the GevPersistentSubnetMask feature to a valid subnet mask address.

6. Optionally, enter a valid default gateway in the GevPersistentDefaultGateway field.

7. Close the Device Control dialog box.

8. Power cycle the embedded video interface.


To automatically configure an IP address




3. Under TransportLayerControl, set the GevCurrentIPConfigurationPersistentIP feature to False.

4. Set the GevCurrentIPConfigurationLLA and/or GevCurrentIPConfigurationDHCP values to True, depending on the type of automatic addressing you require.


6. Power cycle the embedded video interface.

Configuring the Embedded Video Interface’s Image Settings

You can configure the embedded video interface’s image settings, which provide the embedded video interface with information about the image coming from the camera. These settings allow the images to appear correctly.

The image settings are located under ImageFormatControl in the Device Control dialog box.

To turn the test pattern on or off




3. Under ImageFormatControl, click a test pattern option in the TestImage Selector list.



To change the pixel format



2. If images are streaming, click the Stop button.


4. Under ImageFormatControl, set the PixelFormat feature to a color format.



6. Click Play to see the changes.

To configure the image width and height



2. If images are streaming, click the Stop button.


4. Under ImageFormatControl, change the Width and Height to suit your camera.


Implementing the eBUS SDK

You can create your own image acquisition software for the embedded video interface. Consult the eBUS SDK Programmer’s Guide, the eBUS SDK C++ API Help file, and the eBUS SDK .NET API Help file for information about creating custom image acquisition software.


Chapter 12

Network ConfigurationsAfter you have connected to the embedded video interface and provided it with a unique IP address on your network, you can configure the embedded video interface for either unicast or multicast.


• “Unicast Network Configuration” on page 68

• “Multicast Network Configuration” on page 71

Network Configurations 67

Unicast Network Configuration

In a unicast configuration, an embedded video interface is connected to a GigE switch that sends a stream of images over Ethernet to the computer. Alternatively, the embedded video interface can be connected directly to the computer.

The computer is configured as both a data receiver and controller, and serves as a management entity for the embedded video interface.

Figure 4: Unicast Network Configuration

Ethernet

GigE switch

Camera withintegrated embedded

Management entity/data receiver

video interface


Required Items — Unicast Network Configuration

You require the following components to set up a unicast network configuration:

• Camera with integrated embedded video interface and cables

• Power supply

• CAT5e or CAT6 Ethernet cable (quantity: 1)

• GigE switch and an additional CAT5e or CAT6 Ethernet cable (optional)

• Desktop computer or laptop with eBUS SDK, version 2.0.0 (or later) installed

Embedded Video Interface Configuration — Unicast Network Configuration

After you have connected and applied power to the hardware components, use eBUS Player to configure the embedded video interface.

To configure the embedded video interface for a unicast network configuration


2. Click Tools > Setup.

3. Under eBUS Player Role, click Controller and data receiver.

4. Under GigE Vision Stream Destination, click Unicast, automatic.

5. Click OK.

6. Connect to the embedded video interface.


69Network Configurations

7. Click Play to view a live image stream.


Multicast Network Configuration

In a multicast network configuration, the iPORT NTx-GigE Embedded Video Interface is connected to a GigE switch, and sends a stream of images over Ethernet simultaneously to both a computer and to a vDisplay HDI-Pro External Frame Grabber. Then, the vDisplay HDI-Pro External Frame Grabber converts it to an image stream for display on a monitor.

Figure 5: Multicast Network Configuration

Management entity/data receiver

Ethernet

Ethernet

GigE switch

HDMI-to-DVI

Camera withintegrated embedded

vDisplayHDI Pro

or HDMI cable

video interface


Required Items — Multicast Network Configuration

You require the following components to set up a multicast network configuration:

• Camera with integrated iPORT NTx-GigE embedded video interface and cables

• Power supply

• vDisplay HDI-Pro External Frame Grabber and corresponding power supply

• Compatible display monitor

• Cable to connect the vDisplay HDI-Pro External Frame Grabber to the display monitor

• CAT5e or CAT6 Ethernet cables (quantity: 3)

• GigE switch and an additional CAT5e or CAT6 Ethernet cable (optional)

• Desktop computer or laptop with eBUS SDK, version 2.0.0 (or later) installed

Connecting the Hardware and Power

The following procedure explains how to connect the power, network, and data cables to the vDisplay HDI-Pro External Frame Grabber and NTx-GigE Embedded Video Interface.

To connect the network cables and apply power

1. Connect one end of a CAT5e/CAT6 cable to the Ethernet connector on your computer’s NIC. Attach the other end to an available port on the 10 GigE switch.

2. Attach one end of the video cable to the display monitor. Attach the other end to the HDI connector on the vDisplay HDI-Pro External Frame Grabber.

3. Connect one end of a CAT5e/CAT6 cable to the vDisplay HDI-Pro External Frame Grabber Ethernet connector. Attach the other end to an available port on the GigE switch.

4. Connect one end of a CAT5e/CAT6 cable to the iPORT NTx-GigE Embedded Video Interface Ethernet connector. Attach the other end to an available port on the GigE switch.

5. Apply power to the devices.

The message No Video appears on the display monitor.

No Video


Configuring the Devices for a Multicast Network Configuration

After you have connected and applied power to the hardware components, use eBUS Player to configure the vDisplay HDI-Pro External Frame Grabber and iPORT NTx-GigE Embedded Video Interface for multicast configuration. You may want to launch two instances of eBUS Player to perform both configurations. Begin by configuring the vDisplay HDI-Pro External Frame Grabber. Then, configure the embedded video interface to transmit images to a multicast IP address and port.

The vDisplay HDI-Pro External Frame Grabber is documented in the vDisplay HDI-Pro External Frame Grabber User Guide. The iPORT NTx-GigE Embedded Video Interface User Guide provides you with the vDisplay HDI-Pro External Frame Grabber instructions and overviews required to set up and configure the vDisplay HDI-Pro External Frame Grabber for a multicast configuration.

To configure the devices for a multicast network configuration



3. Under eBUS Player Role, click Controller.

You do not need to specify the GigE Vision Stream Destination, as the stream destination is not applicable to a video receiver.

4. Click OK.

5. Connect to the vDisplay HDI-Pro External Frame Grabber.



6. Click Device control.

7. Click Guru in the Visibility list.

8. In the TransportLayerControl > GigEVision category, set GevSCPHostPort to a streaming channel port (for example, 1042).

9. Set GevSCDA to a multicast address (for example, 239.192.1.1).

10.Close the Device Control dialog box.

11.Now, configure the iPORT NTx-GigE Embedded Video Interface, as outlined in “To configure the iPORT NTx-GigE Embedded Video Interface for a multicast network configuration” on page 75.


To configure the iPORT NTx-GigE Embedded Video Interface for a multicast network configuration

1. Start an additional instance of eBUS Player.


3. Under eBUS Player Role, click Controller and data receiver.

4. Under GigE Vision Stream Destination, click Multicast and enter the IP address and Port number.

The address and port must be identical to that configured for the vDisplay HDI-Pro External Frame Grabber in step 8 and 9 of “To configure the devices for a multicast network configuration” on page 73.

5. Click OK.

6. Connect to the iPORT NTx-GigE Embedded Video Interface.



8. Click Guru in the Visibility list.


9. Under TransportLayerControl > GigEVision, ensure that the port in the GevSCPHostPort field and the multicast IP address in the GevSCDA field are correct. They are configured automatically to the values set in step 4 of this procedure.

10.Close the Device Control dialog box.

Click Play to view the source image stream both on the computer and the display monitor.


The multicast image is shown on the computer and the display monitor receiver, as shown below.


Chapter 13

System TroubleshootingThis chapter provides you with troubleshooting tips and recommended solutions for issues that can occur during configuration, setup, and operation of the NTx-GigE Embedded Video Interface.

Not all scenarios and solutions are listed here. You can refer to the Pleora Technologies Support Center at www.pleora.com for additional support and assistance.

The Pleora Technologies Support Center can help you to learn more about integrating Pleora Technologies products. Use keywords to search the Pleora Technologies knowledge database for solutions and suggestions to optimize and troubleshoot Pleora Technologies products. The knowledge database includes a description of the issue and the suggested solution for your search results.

Details for creating a customer account are available on the Pleora Technologies Support Center.

Refer to the product release notes that are available on the Pleora Technologies Support Center for known issues and other product features.

System Troubleshooting 79


Troubleshooting Tips

The scenarios and known issues listed in the following table are those that you might encounter during the setup and operation of your embedded video interface. Not all possible scenarios and errors are presented. The symptoms, possible causes, and resolutions depend upon your particular network, setup, and operation.

If you perform the resolution for your issue and the issue is not corrected, we recommend you review the other resolutions listed in this table. Some symptoms may be interrelated.

Table 25: Troubleshooting Tips

Symptom Possible cause Resolution

SDK cannot detect or connect to the embedded video interface

Power not supplied to the embedded video interface

Both the detection and connection to the embedded video interface will fail if power is not supplied to the device.

Re-try the connection to the device with eBUS Player.

Verify that the Power/Firmware LED (D1 on the GigE PHY board) is green (power on). For information about the LEDs, see “Status LEDs” on page 23.

Verify the power connection.

Device is not connected to the network

Verify that the network activity LED and network connection speed LED are active (J1 on the GigE PHY board). If these LEDs are illuminated, check the LEDs on your network switch to ensure the switch is functioning properly. If the problem continues, connect the embedded video interface directly to the computer to verify its operation. For information about the LEDs, see “Status LEDs” on page 23.

The embedded video interface and computer are not on the same subnet

Images might not appear in eBUS Player if the embedded video interface and the computer running eBUS Player are not on the same subnet. Ensure that these devices are on the same subnet. In addition, ensure that these devices are connected using valid gateway and subnet mask information. You can view the embedded video interface IP address information in the Available Devices list in eBUS Player. A red icon appears beside the device if there is an invalid IP configuration.


SDK is able to connect, but no images appear in eBUS Player.

In a multicast configuration, images appear on a display monitor connected to a vDisplay HDI-Pro External Frame Grabber but do not appear in eBUS Player.

In a multicast configuration, the embedded video interface may not be configured correctly

Images might not appear on the display if you have not configured the embedded video interface for a multicast network configuration. The embedded video interface and all multicast receivers must have identical values for both the GevSCDA and GevSCPHostPort features in the TransportLayerControl section. For more information, see “Multicast Network Configuration” on page 71.

In a multicast configuration, your computer’s firewall may be blocking eBUS Player

Ensure that eBUS Player is allowed to communicate through the firewall.

Anti-virus software or firewalls blocking transmission

Images might not appear in eBUS Player because of anti-virus software or firewalls on your network. Disable all virus scanning software and firewalls, and re-attempt a connection to the embedded video interface with eBUS Player.

Dropped packets: eBUS Player, NetCommand, or applications created using the eBUS SDK

Insufficient computer performance

The computer being used to receive images from the embedded video interface may not perform well enough to handle the data rate of the image stream. The GigE Vision driver reduces the amount of computer resources required to receive images, and is recommended for applications that require high throughput. Should the application continue to drop packets even after the installation of the GigE Vision driver, a computer with better performance may be required.

Insufficient NIC performance

The NIC being used to receive images from the embedded video interface may not perform well enough to handle the data rate of the image stream. For example, the bus connecting the NIC to the CPU may not be fast enough, or certain default settings on the NIC may not be appropriate for reception of a high-throughput image stream. Examples of NIC settings that may need to be reconfigured include the number of Rx Descriptors and the maximum size of Ethernet packets (jumbo packets). Additionally, some NICs are known to not work well in high-throughput applications.

For information about maximizing the performance of your system, see the Configuring Your Computer and Network Adapters for Best Performance Application Note available on the Pleora Support Center.

Black bars appear on the sides of the images

Camera does not output images using the full image size

In eBUS Player, adjust the Width, Height, and image offset features until the black bars no longer appear.

Table 25: Troubleshooting Tips (Continued)

Symptom Possible cause Resolution

81System Troubleshooting

Changing to the Backup Firmware Load

In some cases, you may need to change from the main firmware load to the backup firmware load. You can use the slide switch (SW1 on the FPGA board) to change to the backup firmware mode.

To access the slide switches, peel back the small, protective plastic sheet that covers each slide switch.

OffOn

Table 26: Slide Switch Settings

Position FPGA load

Off Main load

On Backup load


Chapter 14

Reference: Mechanical Drawings and Material List This chapter provides the mechanical drawings, and also provides a list of connectors and cables, with corresponding manufacturer details.

Three-dimensional (3-D) mechanical drawings are available at the Pleora Technologies Support Center.


• “Mechanical Drawings” on page 84

• “Material List” on page 89

Reference: Mechanical Drawings and Material List 83

Mechanical Drawings

The mechanical drawings in this section provide the embedded video interface’s dimensions, features, and attributes. All dimensions are in millimeters.

Figure 6: NTx-GigE Embedded Video Interface FPGA Board


Figure 7: NTx-GigE Embedded Video Interface GigE PHY Board

85Reference: Mechanical Drawings and Material List

Figure 8: NTx-GigE Embedded Video Interface GPIO Board


Figure 9: NTx-Mini Prober Board


Figure 10: NTx-GigE Embedded Video Interface Board Set


Material List

The connector summaries for the embedded video interface are listed in the following table.

Table 27: Connector Summary

ID Location DescriptionManufacturer part number

Manufacturer

J1 FPGA board 100-pin user circuitry interface. Samtec LSHM series 0.5mm pitch vertical 100-pin.

LSHM-150-04.0-L-DV-A-N-TR Samtec

J1 GPIO board 12-pin external interface HR10A-10P-12P(73) Hirose

J1 GigE PHY board

RJ-45 jack RJHSE-3P85 Amphenol

J2 GPIO board 20-pin FFC connector 62674-201121ALF FCI

J9 GigE PHY board

20-pin FFC connector 62674-201121ALF FCI

J2 GigE PHY board

60-pin high speed hermaphroditic terminal/socket strip

LSHM-130-04.0-L-DV-A-N-TR Samtec

J3 FPGA board 60-pin connector LSHM-130-04.0-L-DV-A-N-TR Samtec

Source manufacturer, description, and identification may vary for each connector.


Chapter 15

Technical SupportOn the Pleora Support Center, you can:

• Download the latest software.

• Log a support issue.

• View documentation for current and past releases.

• Browse for solutions to problems other customers have encountered.

• Get presentations and application notes.

• Get the latest news and information about our products.

• Decide which of Pleora’s products work best for you.

To visit the Pleora Support Center

• Go to www.pleora.com and click Support Center.

If you have not registered yet, you are prompted to register.

Accounts are usually validated within one business day.

If you have difficulty finding an existing solution in the knowledge base, post a question by clicking Log a Case. Provide as many specific details about your system and the nature of the issue as possible.

Technical Support 91


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