US+U Simple Swivel iPad2/iPad3 Back Protector with Hand Strap review
Ipad3 Diagram
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2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PROPRIETARY PROPERTY OF APPLE INC.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
DESCRIPTION OF REVISI
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NOTICE OF PROPRIETARY PROPERTY:
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THE INFORMATION CONTAINED HEREIN IS THE
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SHEET
Apple Inc.
THE POSESSOR AGREES TO THE FOLLOWING:
DRAWING TITLE
REVIS
DRAWI
BRANC
REV ECN
7
3
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
IV ALL RIGHTS RESERVED
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
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J2 MLB - DVT OK2FAB
Schematic / PCB #s
ENGINEERING RELEASED
05
10 0001231154
LAST_MODIFIED=Tue Sep 6 17:35:11 2011
X26_WIFI_MIKE_BT 09/01/20116131 WLAN BB & POWER
JOE 01/19/20116030 CONNECTOR: X26
JOE 01/19/20115929 IO FLEX: B2B CONNECTOR
JOE 01/19/20115828 DISPLAY PORT MISC
JOE 01/19/20115727 IO FLEX: DOCK COMPONENTS
MARK 01/11/20115626 SENSOR PANEL FILTERS 2
MARK 01/11/20115525 SENSOR PANEL FILTERS 1
MARK 01/11/20115424 CONNECTOR: SENSOR
KAVITHA 02/03/20114323 AUDIO: HP/MIC FILTERS
KAVITHA 02/03/20114222 AUDIO: DETECT/MIC BIAS
KAVITHA 02/03/20113821 AUDIO: HEADPHONE OUT
KAVITHA 02/03/20113720 AUDIO: SPEAKER AMP
KAVITHA 02/03/20113619 AUDIO: L63B CODEC
RAMSIN 12/17/20103118 GRAPE: Z1, Z2
RAMSIN 12/17/20103017 GRAPE: GROUNDHOG,CONN,BOOST
JOE 01/19/20112216 VIDEO: EDP CONNECTOR
ALEX 09/30/20102115 MLB ALIASES/CONNECTIONS
MIKE 06/21/20101714 DDR 2 AND 3
MIKE 06/21/20101613 DDR 0 AND 1
MIKE N/A 1412 NAND
CHOPIN 12/10/20101311 AP: VIDEO BUFFER,BB USB MUXES
ALEX N/A1210 AP: MISC & ALIASES
MIKE N/A 119 AP: POWER
MIKE N/A 108 AP: DDR
JOE 01/13/201197 AP: TV,DP,MIPI
MIKE N/A 86 AP: NAND
JOE N/A 75 AP: I/Os
MIKE N/A 64 AP: MAIN
MIKE N/A 43 BOM TABLES
J2DEV N/A22 BLOCK DIAGRAM: SYSTEM
15748 01/21/2011FUNC TEST POINTS MIKE
15647 01/21/2011FUNC TEST POINTS MIKE
15546 01/21/2011CONSTRAINTS: DEBUG MIKE
15445 01/21/2011CONSTRAINTS: POWER / GND MIKE
15344 01/21/2011CONSTRAINTS: DDR/FMI MIKE
15243 01/21/2011CONSTRAINTS: DISPLAY/AUDIO MIKE
15142 01/21/2011CONSTRAINTS: LOW SPEED BUS MIKE
15041 01/21/2011CONSTRAINTS: MLB RULES MIKE
9340 10/04/2010FCT/ICT TEST/BRACKETS ALEX
9039 10/04/2010DEBUG AND MISC ALEX
8338 01/13/2011POWER: AMELIA VSS MADHAVI
8237 01/14/2011POWER: AMELIA PMU MLB
8136 01/13/2011POWER: AMELIA PMU MADHAVI
8035 01/13/2011POWER ALIASES MADHAVI
7534 01/13/2011POWER: BATTERY CONNECTOR MADHAVI
6333 09/01/2011WLAN 5GHZ AND TEST POINTS X26_WIFI_MIKE_BT
SYNC MASTER DATECONTENTSCSAPDF
DRAWINGMLB
MIKE NA11 Table of Contents 6232 09/01/2011WLAN 2.4GHZ AND ANT X26_WIFI_MIKE_BT
PDF CONTENTSCSA DATESYNC MASTER
SYNC_MASTER=MIKE
SCH,J2,MLB
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Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DRAWI
REVIS
BRANC
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
FF CAMERAVGA FLEX
REAR CAMERA
AUDIO
UART3
UART6
MIPI1C
DUAL-CORE ARMCORTEX-A9 W/ SMP HSIC1_1
ISP_I2C1
LPDDR2
HSIC0_1
AMP
AMP
BT_I2S
CSA 61-64
CSA 60
VA5/8 FLEX
VGA FLEX
BUTTON FLEX
HALL EFF PROX SENSOR
AE2
GPU
ARM A5 CPU
QUAD-CORE IMGSGX543-MP2400MHZ/800MB/S4X32-BIT
1 GBYTE
EDP
MIMO
WIFI/BT ANT 2
WIFI ANT 1
FMI2FMI1
HSIC1
CELLULAR/GPSX26
950 MHZ
H4G
DWI
UART5
DISPLAYPORT
CSA 31
CSA 31CSA 30
CSA 75
CSA 14CSA 14
I2S2
VIDEO DAC
FMI0
USB2.0
I2C0
I2C2
DOCK30-PIN
GYRO ACCELEROMETER ALS
ISP_I2C0SPI1
WIFI/BT
MIPI0C
USART
IPCSPI2
I2C1
UART1
AMP
ASP
LINEOUT
I2S0
Z2
AUDIO CODECL63B
TOUCH PANEL
RESOLUTION: 2048X1536
GROUNDHOGZ1
VSP
FMI3
XSP
CSA 36
I2S3
I2C 8H94
I2C 8H76
PPN1.0 PPN1.0NAND FLASHNAND FLASH
CSA 57
UART0
SPEAKE
PRIMARY CELLULAR
DIVERSITY CELLUL
GPS ANT
PMUAMELIA
BATTERY
DISPLAY/
BACKLIGHT
SENSOR PANELSENSOR PANEL
SENSOR PANEL SENSOR PANEL
COMPASS
CSA 81,82
I2C 8H1C
I2C 8H78
I2C 8H58
I2C 8H72I2C 8H32I2C 8HD0
MIC
EXMUXUS/CHINA
SYNC_MASTER=J2DEV
BLOCK DIAGRAM: SY05
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CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART NUMBERALTERNATE FORP AR T N UM BE R B OM O PT IO N REF DES COMMENTS:
TABLE_ALT_HEAD
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
TABLE_5_ITEM
PART NUMBERALTERNATE FORP AR T N UM BE R B OM O PT IO N REF DES COMMENTS:
TABLE_ALT_HEAD
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_ALT_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
PART NUMBERALTERNATE FORP AR T N UM BE R B OM O PT IO N REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
PART NUMBERALTERNATE FORP AR T N UM BE R B OM O PT IO N REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_5_ITEM
PART NUMBERALTERNATE FORP AR T N UM BE R B OM O PT IO N REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DRAWI
REVIS
BRANC
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
NAND
SDRAM
SCH AND BOARD P/N
DEVELOPMENT_JTAG_TAP
Power aliases required by this page:
INTERNAL_MIC
DEVELOPMENT_JTAG
16GB_PROD
(NONE)
32GB_PROD
JTAG_DAP
SPEAKER
(NONE)
ALTERNATECOMMON
64GB_PROD128GB_PROD
J2MLBDEV
NAND_IO_1V8
NAND_IO-3V3
SNOTE
MECHANICAL PARTS
BOM options provided by this page:
BARCODE LABEL/EEEE CODES
PMU
32GB FLASH CONFIGURATIONS
16GB FLASH CONFIGURATIONS
64GB FLASH CONFIGURATIONS
128GB FLASH CONFIGURATIONS
Page Notes
Signal aliases required by this page:
ALL AVAIL BOM OPTIONS
SOC
DEV1DEV BOM,MLB,J2085-3058 ?1
PCB1PCBF,MLB,J2820-2996 ?1 CRITICAL
SCH1SCH,MLB,J2051-8773 ?1 CRITICAL
U0600IC,SOC,H4G,FCBGA1225343S0533 CRITICAL1 ?
SY NC_M ASTE R=MI KE
BOM TABLES
825-7691 CRITICAL1 EEEE_J2A_64GEEEE FOR 639-2827 (J2A 64G) EEEE_DRF5
1 CRITICALEEEE FOR 639-2826 (J2A 32G) EEEE_J2A_32G825-7691 EEEE_DRF6
EEEE FOR 639-2844 (J2A 16G) EEEE_DRJQ EEEE_J2A_16G825-7691 CRITICAL1
FENCE,LARGE,TOP,MLB,J2 PD_FENCE_LARGE806-1857 CRITICAL1
806-1860 PD_FENCE_BTM1FENCE,1,BTM,MLB,J21 CRITICAL
806-1865 FENCE,2,BTM,MLB,J2 CRITICALPD_FENCE_BTM21
FENCE,SMALLER,BTM,MLB,J2 CRITICALPD_FENCE_BTM31806-2352
AUDIO SPEAKER,INTERNAL_MIC
U1400,U1410128GB_PROD335S0806 335S0814 TOSHIBA 24NM PPN1.0
128GB_PRODU1400,U14102 CRITICAL335S0814 HYNIX 26NM PPN1.0 64GB
64GB_PROD U1400,U1410335S0805 335S0782 TOSHIBA 24NM PPN1.0
CRITICAL 64GB_PROD2 U1400,U1410335S0782 HYNIX 26NM PPN1.0 32GB
U1400,U141032GB_PROD335S0781335S0804 TOSHIBA 24NM PPN1.0
335S0804 335S0781 16GB_PROD U1400 TOSHIBA 24NM PPN1.0
16GB_PRODU1400HYNIX 26NM PPN1.0 16GB1335S0781 CRITICAL
HYNIX 26NM PPN1.0 16GB335S0781 CRITICAL2 U 14 00 ,U 14 10 3 2G B_ PR OD
U1600,U1700SDRAM,LPDDR2,512MB,SAMSUNG 46NM2333S0579 ?CRITICAL
CRITICALU8100IC,PMU,AMELIA,D1974AB1343S0561 ?
EEEE_J2_128GEEEE_DKQK1 CRITICALEEEE FOR 639-1870 (J2 128G)825-7691
825-7691 EEEE FOR 639-2352 (J1 16G)1 CRITICALE EEE_D NKT E EEE_ J1_16 G
825-7691 CRITICALE EEE_D M2N E EEE_ J1_32 G1 EEEE FOR 639-2058 (J1 32G)
825-7691 EEEE FOR 639-2059 (J1 64G)1 CRITICALE EEE_D M2P E EEE_ J1_64 G
825-7691 EEEE FOR 639-2353 (J2 16G)1 CRITICAL EEEE_J2_16GEEEE_DNKV
825-7691 EEEE FOR 639-1572 (J2 32G)1 CRITICAL EEEE_J2_32GEEEE_DHWV
825-7691 EEEE FOR 639-1871 (J2 64G)1 CRITICALE EEE_D KQL E EEE_ J2_64 G
COMMON,ALTERNATEBASIC
CRITICALFENCE,NAND,TOP,MLB,J2806-2105 1 PD_FENCE_NAND
806-2349 1 PD_FENCE_SMALL CRITICALFENCE,SMALLER,TOP,MLB,J2
LPDDR2,HYNIX 44NM3 33 S0 57 9 U 16 00 ,U 17 00333S0580
LPDDR2,ELPIDA 45NMU1600,U1700333S0579333S0581
05
3
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BI
BI
BI
BI
(1 OF 12)
JTAG_TRST*
XO0
XI0
WDOG
USB11_DP1
USB11_DP0
USB11_DM1
USB11_DM0
USB_VDD330
USB_VBUS1
USB_VBUS0
USB_ID1
USB_ID0
USB_DVDD
USB_DP0
USB_DM0
USB_BRICKID1
USB_BRICKID0
USB_ANALOGTEST1
USB_ANALOGTEST0
TST_STPCLK
TST_CLKOUT
TESTMODE
RESET*
PLL5_AVDD11
PLL4_AVDD11
PLL3_AVDD11
PLL2_AVSS1
1
PLL2_AVDD11
PLL1_AVSS1
1
PLL1_AVDD11
PLL0_AVSS1
1
PLL0_AVDD11
PLL_USB_AV
SS11
PLL_USB_AVDD11
MIPI1D_VDD11_PLL
JTAG_TRTCK
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
JTAG_SEL
HSIC1_VSS1
22
HSIC1_VSS1
21
HSIC1_VDD122
HSIC1_VDD121
HSIC1_STB2
HSIC1_STB1
HSIC1_DVSS
HSIC1_DVDD
HSIC1_DATA2
HSIC1_DATA1
HSIC0_VSS1
22
HSIC0_VSS1
21
HSIC0_VDD122
HSIC0_VDD121
HSIC0_STB2
HSIC0_STB1
HSIC0_DVSS
HSIC0_DVDD
HSIC0_DATA2
HOLD_RESET
FUSE1_FSRC
FAST_SCAN_CLK
DDR3_CKEIN
DDR2_CKEIN
DDR1_CKEIN
DDR0_CKEIN
CFSB1
HSIC0_DATA1
USB_DM1
USB_DP1
USB_DVSS
USB_VSSA0
USB_VSSAC
PLL5_AVSS1
1
MIPI_VSS
USB_REXT1
USB_REXT0
PLL4_AVSS1
1
PLL3_AVSS1
1
CFSB0
MIPI0D_VDD11_PLL
(11 OF 12)
VSS VSS
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DRAWI
REVIS
BRANC
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
1 - DAISY CHAIN (FOR USE WITH 5-WIRE JTAG)
34MA
7MA
10MA
7MA
14MA
2.5MA EACH
2.5MA
JTAGSEL
3.16V
1.75V
1.16V
28MA34MA
BB
WLAN
PER RADAR #6755237
0 - PARALLEL
01005X5R6.3V
0.01UF10%
01005
0.01UF10%
X5R6.3V
10%
01005X5R
0.01UF6.3V
0.01UF
01005
6.3V10%
X5R
3042
3042
154042
154042
5%
100K
1/32W 01005
5%01005
100K
1/32W
010055%
100K
1/32W
01005
100K1/32WMF
1%
1%10K
MF01005
1/32W
1000PF
201
16VX7R
10%
01005MF
1/32W
0.00
0%
MLB
01005
0.01UF10%
X5R6.3V
H4GFCBGA
OMIT
H4GFCBGAOMIT
10
10
10
10
1042
104245
10
1%44.2
201MF1/20W
201MF1/20W
1%44.2
01005
0%
0.00
MF1/32W
0%
0.00
MF01005
1/32W
0.00
1/32WMF
0%
01005
0.00
0%1/32WMF
01005
0.00
0%1/32W
01005MF
0%
MF01005
1/32W
0.00
1/32W0%
01005MF
0.00
0201
80-OHM-0.2A-0.4-OHM
GDZ-0201GDZT2R5.1B
100K5%1/32WMF01005
DEVELOPMENT_JTAG_TAP
100K
5%1/32W MF01005
CRITICAL
SM-224.000MHZ-16PF-60PPM
01005
1/32W5%
22
MF
01005
22PF
CERM16V5%
01005
5%22PF
CERM16V
1.00M010051/32W1% MF
42.2K1%
MF1/32W
01005
01005
1/32WMF
1%82.5K
27303745
37
37 45
6.3VX5R
10%
01005
0.01UF6.3VCERM402
1UF10%
6.3VX5R
10%0.01UF
01005
0.01UF6.3VX5R
10%
01005
01005
0.01UF10%
X5R6.3V 6.3V
402CERM
10%1UF56PF
NP0-C0G01005
6.3V5%
6.3VX5R
10%0.01UF
01005
6.3VX5R01005
10%0.01UF
6.3VX5R
10%0.01UF
01005
0.01UF10%6.3VX5R01005
0.01UF6.3VX5R01005
10%
10%
X5R6.3V
0.01UF
01005
0.01UF6.3VX5R01005
10%
01005
0.01UF6.3VX5R
10%
SYNC_MASTER=MIKE
AP: MAIN
PP1V1_PL4_FVOLTAGE=1.1VMIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.1MM
=PP1V1_PLL_H4
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3MM
PP1V1_MIPID_PLL_FVOLTAGE=1.1VMIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3MMNET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.2MMVOLTAGE=1.1V
MIN_NECK_WIDTH=0.1MM
PP1V1_PL1_F
MIN_LINE_WIDTH=0.2MMVOLTAGE=1.1V
MIN_NECK_WIDTH=0.1MM
PP1V1_PL2_F
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.1MM
PP1V1_PL3_FVOLTAGE=1.1VMIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3MM
PP1V1_PL5_F
MIN_LINE_WIDTH=0.2MMVOLTAGE=1.1V
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3MMNET_SPACING_TYPE=PWR
PP1V1_PLL_USB_FVOLTAGE=1.1VMIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MM
RST_PMU_IN
=PP1V8_H4
24M_O
PPVBUS_USB
=PP3V3_USB_H4
=PP1V1_PLL_H4
=PP1V1_USB_H4
=PP1V1_MIPI_PLL_H4
=PP1V8_H4
USB_REXT0
USB_REXT1
NC_USB_D1_P
NC_USB_D1_N
HSIC0_BB_DATA1
AP_DDR1_CKEIN_1V2
NC_HSIC0_DATA2
HSIC0_BB_STB1
NC_HSIC0_STB2
HSIC1_WLAN_DATA1
NC_HSIC1_DATA2
HSIC1_WLAN_STB1
NC_HSIC1_STB2
JTAG_AP_SEL
JTAG_AP_TCK
JTAG_AP_TDI
JTAG_AP_TMS
NC_JTAG_AP_TRTCK
NC_USB_ANALOGTEST0
NC_USB_ANALOGTEST1
USB_BRICKID
NC_USB_BRICKID1
USB_DK_D0_N
USB_DK_D0_P
NC_USB_ID0
NC_USB_ID1
USB_AP_VBUS0
USB11_MUX_D0_N
NC_USB11_D1_N
AP_WDOG
XTAL_24M_I
XTAL_24M_O
=PP1V2_HSIC_H4
MIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.1MM
PP1V1_PL0_FVOLTAGE=1.1V
MAX_NECK_LENGTH=3MM
=PP1V1_HSIC_H4
=PP1V1_USB_H4
=PP3V3_USB_H4
USB_AP_VBUS1
JTAG_AP_TDO
JTAG_AP_TRST_L
TP_AP_TST_CLKOUT
AP_TST_STPCLK
RST_AP_L
AP_FAST_SCAN_CLK
AP_HOLD_RESET
AP_TESTMODE
RST_AP_1V8_L
USB11_MUX_D0_P
NC_USB11_D1_P
C06151
2
R06121
2
R06131
2
R06041 2
R06031 2
R06021 2
R06011 2
R06051 2
R06061 2
R06071 2
FL0600
1 2
DZ06001
2
R06091
2
R06081 2
Y0602
2 4
1 3
R06511 2
C061
2
C06501
2
R0650
1
2
R06421
2
R06431
2
C06121
2
C06141
2
C06081
2
C06091
2
C06211
2
C06221
2
C06201
2
C06041
2
C06031
2
C06001
2
C06011
2
C06021
2
C06071
2
C06301
2
C06311
2
C06351
2
C06341
2
C06331
2
C06321
2
R06211 2
R06221 2
R06201 2
R06411
2
R06401
2
C06401
2
R06521 2
U0600
W6
AR32
L6
F9
AK10
AF6
AR33
M31
AN28
K35
K33
N31
N30
L35
L33
P29
P31
P28
P30
H35
H33
H32
H31
J35
J33
K30
J30
K29
J29
AK29
AN29
AN30
AP30
AJ27
AR27
AM27
F27
F30
H24
H25
H26
H27
H28
H29
V33
V32
U33
U32
T33
T32
R33
R32
P33
P32
N33
N32
M33
M32
AR30
AH27
AR29
AR28 R34
P35
T34
N35
R30
J28
T28
K31
T35
M34
U35
N34
U29
L30
U28
L31
T31
K32
R31
K28
T30
J32
R28
M28
T29
L28
R29
L29
AP29
W35
Y35
U0600A1
A2
AA8
AN10
AN13
AN16
AP1
AP2
AP6
AP9
AP12
AP15
AP18
AA10
AP22AP25
AP28
AP31
AP34
AP35
AR1
AR2
AR5
AR8
AA12
AR11
AR14
AR17
AR19
AR34
AR35
B1
B2
B4
B9
AA14
B12
B15
B34
B35
C7
C10
C13
C16
C30
C31
AA16
C32
C33D3
D5
D8
D11
D14
D17
D30
D33
AA18
E1
E10
E21
E22
E24
E25
E26
E27
E28
E29
AA20
E30
E33
F2
F5
F16
F17
F21
F22
F24
F33
AA22
G3
G17
G18
G19
G20
G21
AA24
AA26
A5
AA35
AB1
AB4AB8
AB9
AB11
AB13
AB15
AB17
AB19
A8
AB21
AB23
AB25
AB27
AC3
AC8
AC10
AC18
AC20
AC22
A11
AC24
AC28
AC32
AC34
AD2
AD8
AD9
AD11
AD19
AD21
A14
AD23
AD25
AD27
AD29AE1
AE8
AE9
AE10
AE18
AE20
A17
AE22
AE24
AE26
AF3
AF8
AF9
AF27
AF30
AF32
AF34
A34
AG2
AG8
AG9
AH1
AH8
AH9
AH10
AH11
AH12
AH17
A35
AH22
AH25
AH26
AJ5
AJ13
AJ20
AJ29
AJ32
AJ34
AK2
AA2
AL1
AM3
AM8
AM19
AM22
AM25
AM28
AM32
AM34
AN7
05
45435
4545
45
45
45
45
471035
42
36 45
435
4 35
4 35
35
471035
42 46
42 46
4246
4246
4246
4246
10
2742
1042
2742
46
46
46
46
27 42
27 42
46
46
11 42
42 46
42
42
35
45
35
4 35
4 35
45
11 42
42 46
-
8/10/2019 Ipad3 Diagram
5/48
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
BI
OUT
BI
OUT
BI
OUT
INOUT
OUT
OUT
IN
OUT
OUT
IN
IN
IN
IN
OUT
IN
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
(2 OF 12)
UART5_RTXD
UART3_TXD
UART3_RXD
UART3_RTSN
UART3_CTSN
UART6_TXD
UART6_RXD
UART6_RTSN
UART6_CTSN
UART4_TXD
UART4_RXD
UART4_RTSN
UART4_CTSN
UART2_TXD
UART2_RXD
UART2_RTSN
UART2_CTSN
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO39
GPIO38
GPIO37
GPIO36
GPIO35
GPIO34
GPIO33
GPIO32
GPIO31
GPIO30
GPIO3
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO2
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO1
GPIO0
GPIO_3V1
GPIO_3V0
UART1_TXD
UART1_RXD
UART1_RTSN
UART0_TXD
UART0_RXD
TMR32_PWM2
TMR32_PWM1
TMR32_PWM0
EHCI_PORT_PWR2
GPIO9
GPIO10
UART1_CTSN
EHCI_PORT_PWR1
EHCI_PORT_PWR0
SPI0_SSIN
SPI0_SCLK
SPI0_MOSI
SPI0_MISO
SWI_DATA
SPI3_SSIN
SPI3_SCLK
SPI3_MOSI
SPI3_MISO
SPI2_SCLK
SPI2_MOSI
SPI1_SSIN
SPI1_SCLK
SPI1_MOSI
SPI1_MISO
SPDIF
SDIO0_DATA3
SDIO0_DATA2
SDIO0_DATA1
SDIO0_DATA0
SDIO0_CMD
SDIO0_CLK
I2S3_MCK
I2S3_LRCK
I2S3_DOUT
I2S3_DIN
I2S3_BCLK
I2S2_MCK
I2S2_BCLK
I2S1_MCK
I2S1_LRCK
I2S1_DIN
I2S1_BCLK
I2S0_MCK
I2S0_DOUT
I2S0_BCLK
I2C2_SDA
I2C2_SCL
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
DWI_DO
DWI_DIDWI_CLK
I2S2_DOUT
I2S2_DIN
I2S2_LRCK
I2S1_DOUT
I2S0_LRCK
I2S0_DIN
VSSA18_TS
VDDA18_TS
SPI2_SSIN
SPI2_MISO
THERM_RES_EXT
THERM_TEST_OUT
(3 OF 12)
IN
OUT
IN
IN
IN
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IN
OUT
IN
OUT
IN
OUT
IN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DRAWI
REVIS
BRANC
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CODEC ASP
- BB -> H4G
- BB_DIAGS_READY (RADAR #9179861)
NOTE FOR GPIO12:
- AP_MODEM_WAKE (RADAR #9179861)
NOTE FOR GPIO24:
- H4G -> BB
BUT OPTION IS HERE IN CASE THEY NEED TO BE SEPARATE
DEFAULT IS TO TIE HSIC_HOST_READY TO BOTH DEVICES
TO BB
NEW GPIO FOR J2. FILE A RADAR
TO SENSOR BOARD (ALS)
CODEC VSP & BT
TO SENSOR BOARD
TO CHARLESTON, CODEC AND PMU
CODEC XSP
NOT USED
TO GRAPE
3.0V IO
TO BT UART
TO DOCK MUX
TO BB USART
15 42
15 42
15 42
15 42
34 37
1%
MF01005
1/32W
33.2
1942
1942
1942
1942
1942
151942
151942
151942
151942
1942
1942
1942
1942
10
10
10
10 19 22 37 42
10 19 22 37 42
10 25 42
10 25 42
25 42
25 42
37 42
37 42
37 42
5%
201
220K
1/20WMF
5%
MF
220K
1/20W
201
201
5%
220K
1/20WMF
201MF
100K1/20W5%
MF
100K1/20W5%
201
100K
MF1/20W5%
201MF1/32W
01005
100K5%5%
201
100K1/20WMF
30 42
30 42
30 42
5 30 42
3042
24
24
30
537
3045
15
37
19
153045
201
100K5%1/20WMF
NOSTUFF
MF
100K
201
1%1/20W
1742
1742
1742
1742
1/32W0%
01005MF
0.00
10%
X5R6.3V
0.01UF
01005
01005MF1/32W1%100K
NOSTUFF
0%
MF01005
1/32W
0.00
MF
0%1/32W
01005
0.00
MF1/20W
5%100K
201
542
OMIT
H4GFCBGAOMIT
H4GFCBGA
51542
15 42
15 42
52837
52437
530
3042
526
10
18
30
10
5
539
10
10
26
26
26
26
25
11
20
10
10
10
15 42
15 42
30 42
30 42
30 42
30 42
5 24 37
30 45
SYNC_MASTER=JOE
AP: I/Os
IRQ_CODEC_L
NC_AP_GPIO7
NC_AP_GPIO8
PM_RADIO_ON
RST_DET_L
HSIC_BB_RDY
ONOFF_L
HOME_EMI_L
GPIO42_BRD_REV2
IRQ_ALS_INT_L
AUD_SPKRAMP_MUTE_L
PORT_DOCK_VIDEO_AMP_EN
RST_BB_L
SRL_L
NC_BOARD_ID_3
IRQ_ACCEL_INT1_L
UART0_AP_TXD
UART0_AP_RXD
IRQ_PMU_L
PM_BT_WAKE
=PP1V8_VDDA18_TS
HSIC_HOST_RDY
=PP1V8_VDDIOD_H4
UART1_BB_RTS_L
HSIC_HOST_READY_WLAN
HSIC_HOST_RDY
=PP1V8_S2R_MISC
=PP1V8_ALWAYS
=PP1V8_S2R_MISC
SRL_L
ONOFF_L
HOME_EMI_L
HSIC_WLAN_RDY
HSIC_HOST_READY_WL
GPIO40_BRD_REV0
GPIO41_BRD_REV1
UART1_BB_CTS_L
NC_AP_GPIO185
NC_AP_GPIO186
TP_LED_STROBE_EN
UART1_BB_RXD
UART1_BB_TXD
NC_AP_GPIO11
SPI2_IPC_SRDY
NC_AP_GPIO13
AUD_VOL_DOWN_LGSM_TXBURST_IND
IRQ_GYRO_INT2
BOOT_CONFIG_0
NC_AP_GPIO19
AUD_VOL_UP_L
IRQ_GRAPE_HOST_INT_L
PM_KEEPACT
BB_EMERGENCY_DWLD
IPC_GPIO_X26
BOOT_CONFIG_1
FORCE_DFU
BOOT_CONFIG_2
BOOT_CONFIG_3
NC_AP_GPIO3
NC_UART2_RXD
NC_UART2_TXD
NC_UART4_CTS_L
NC_UART4_RTS_L
NC_UART4_RXD
NC_UART4_TXD
NC_UART6_CTSN
NC_UART6_RTSN
UART3_BT_CTS_L
UART3_BT_RTS_L
UART3_BT_RXD
UART3_BT_TXD
BATTERY_SWI
TP_THERM_TEST_OUT
THERM_RES_EXT
SPI2_IPC_MISO
PP1V8_VDDA18_TS
NC_I2S1_DOUT
I2S2_VSP_LRCK
I2S2_VSP_DIN
I2S2_VSP_DOUT
DWI_AP_DI
DWI_AP_DO
I2C0_SCL_1V8
I2C0_SDA_1V8
I2C1_SCL_1V8
I2C2_SCL_3V0
I2C2_SDA_3V0NC_I2S1_BCLK
NC_I2S1_DIN
NC_I2S1_LRCK
NC_I2S1_MCK
I2S2_VSP_BCLK
NC_I2S2_MCK
I2S3_XSP_BCLK
I2S3_XSP_DIN
I2S3_XSP_DOUT
I2S3_XSP_LRCK
NC_I2S3_MCK
NC_SDIO0_WL_CLK
NC_SDIO0_WL_CMD
NC_SDIO0_WL_DATA
NC_SDIO0_WL_DATA
NC_SDIO0_WL_DATA
NC_SDIO0_WL_DATA
NC_AP_GPIO216
SPI1_GRAPE_MISO
SPI1_GRAPE_MOSI
SPI1_GRAPE_SCLK
SPI1_GRAPE_CS_L
SPI2_IPC_MOSI
SPI2_IPC_SCLK
NC_SPI3_MISO
NC_SPI3_MOSI
NC_SPI3_SCLK
NC_SPI3_CS_L
NC_SWI_AP
BOARD_ID_2
BOARD_ID_1
BOARD_ID_0
NC_SPI_FLASH_CS_L
I2C1_SDA_1V8
DWI_AP_CLK
IRQ_GYRO_INT1
IRQ_PROX_INT_L
NC_AP_GPIO31
HSIC_HOST_READY_WL
NC_AP_GPIO35
HSIC_WLAN_RDY
NC_AP_GPIO3V1
DFU_STATUS
IRQ_ACCEL_INT2_L
UART6_WLAN_RXD
UART6_WLAN_TXD
PM_RADIO_ON
DFU_STATUS
FORCE_DFU
IRQ_GYRO_INT2
PM_KEEPACT
I2S0_ASP_MCK_R
I2S0_ASP_BCLK
I2S0_ASP_LRCK
I2S0_ASP_DIN
I2S0_ASP_DOUT
I2S0_ASP_MCK
R0700
1 2
R07081 2
R07091 2
R07101 2
R07151
2
R07141
2
R07131
2
R07121
2
R07111
2
R07201
2
R07221
2
R11801 2
C11881
2
R10301
2
R07301 2
R07311 2
R08851
2
U0600
AG26
AE15
AE16
AJ14
AK15
AG17
AD13
AK17
AE14
AL17AF17
AL18
AK18
AJ18
AD12
AL16
AH18
AF18
AM18
AN18
AN19
AG18
AP20
AN20
AR20
AR21
AG14
AP21
AK19
AN21
AH19
AG19
AJ19
AR22
AL20
AM20
AN22
AP19
AH13
AH16
AE13
AE12
AH15
AN31
AP32
AD16
AD14
AC12
AH14
AG15
AP23
AL21
AG21
AF21
U5
T7
U8
T5
AG22
AJ21
AR24
AR23
Y6
Y7
W7
Y5
AL22
U9
V6
U7
V7
U0600
AN25
AM24
AG23
AJ23
AK23
AN24
AR25
AH21
AK21
AG24
AK25
AL25
AP26
AR26
AC17
AC16
AF26
AC14
AC15
AF24
AG25
AM26
AN26
AK27
AN27
AK26
AL26
AF25
AP27
AL27
AR31
AK28
AL28
AM29
AM30
AG27
U6
W5
T6
W8
AF20
AF19
AG20
AM21
AF23
AL23
AH23
AM23
AL30
AL29
AN32
AP33
AC13
AK16
AJ16
AF16
AG16
05
46
46
46
35
935
15 42
53042
5273539
35
5273539
52437
52437
52837
51542
542
46
46
46
46
46
46
46
46
46
46
46
46
46
46
45
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
4646
46
46
5 30
5
5 39
5 26
5 37
42
-
8/10/2019 Ipad3 Diagram
6/48
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
FMI0_ALE
FMI3_IO7
FMI3_IO6
FMI3_IO5
FMI3_IO4
FMI3_IO1
FMI3_IO0
FMI3_DQS
FMI3_CLE
FMI3_CEN7
FMI3_CEN6
FMI3_CEN5
FMI3_CEN4
FMI3_CEN3
FMI3_CEN2
FMI3_CEN1
FMI3_CEN0
FMI2_WEN
FMI2_REN
FMI2_IO7
FMI2_IO6
FMI2_IO5
FMI2_IO4
FMI2_IO3
FMI2_IO2
FMI2_DQS
FMI2_CLE
FMI2_CEN7
FMI2_CEN6
FMI2_CEN4
FMI2_CEN3
FMI2_CEN2
FMI2_CEN1
FMI2_CEN0
FMI2_ALE
FMI1_IO7
FMI1_IO4
FMI1_IO3
FMI1_IO2
FMI1_IO1
FMI1_IO0
FMI1_DQS
FMI1_CLE
FMI1_CEN1
FMI1_CEN0
FMI1_ALE
FMI0_WEN
FMI0_IO7
FMI0_IO6
FMI0_IO5
FMI0_IO4
FMI0_IO3
FMI0_IO2
FMI0_IO1FMI0_IO0
FMI0_DQS
FMI0_CEN7
FMI0_CEN6
FMI0_CEN5
FMI0_CEN4
FMI0_CEN3
FMI0_CEN1
FMI0_CEN0
FMI1_CEN2
FMI1_CEN3
FMI1_CEN4
FMI1_CEN7
FMI1_CEN6
FMI1_CEN5
FMI2_IO1FMI2_IO0
FMI0_CEN2
FMI2_CEN5
FMI0_CLE
FMI0_REN
FMI3_ALE
FMI1_IO5
FMI1_IO6
FMI3_IO3
FMI3_IO2
FMI1_REN
FMI1_WEN
FMI3_REN
FMI3_WEN
(4 OF 12)
(12 OF 12)
VSSVSS
IN
OUT
OUT
BI
OUT
OUT
OUT
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DRAWI
REVIS
BRANC
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CHECK WITH GRAPE ON VOLTAGE FOR THESE TWO SIGNALS
CHECK CONNECTION FOR VSSA18_TS
FMI2-3_CEN IS 3.0V
NEW GPIO FOR J2. FILE A RADAR
1244
1244
1244
1244
61244
61244
61244
61244
61244
61244
1244
1244
1244
1244
1244
1244
1244
1244
61244
61244
61244
61244
1244
1244
MF1/32W5%100K
01005
NOSTUFF
01005
100K5%1/32WMF
NOSTUFF
MF1/32W5%100K
01005
NOSTUFF
MF1/32W5%100K
01005
NOSTUFF
100K5%1/32WMF01005
NOSTUFF
01005
100K5%1/32WMF
NOSTUFF
MF1/32W5%100K
01005
NOSTUFF
MF1/32W5%100K
01005
NOSTUFF
OMIT
H4GFCBGA
H4GFCBGA
OMIT
100K5%1/32WMF01005
20
01005
100K5%1/32WMF
01005
100K5%1/32WMF
01005
100K5%1/32WMF
100K5%1/32WMF01005
17 45
16
1244
61244
17
61244
1244
1244
1244
AP: NANDSYNC_MASTER=MIKENC_FMI3_WE_LFMI1_WE_L
FMI1_CLE
FMI1_AD
FMI1_AD
FMI1_AD
FMI1_AD
NC_FMI2_CE1_L
RST_GRAPE_L
FMI0_ALE
NC_FMI3_AD
NC_FMI3_AD
NC_FMI3_AD
NC_FMI3_AD
NC_FMI3_AD
NC_FMI3_AD
NC_FMI3_DQS
NC_FMI3_CLE
NC_FMI3_CE7_L
NC_FMI3_CE6_L
NC_FMI3_CE5_L
NC_FMI3_CE4_L
NC_FMI3_CE3_L
NC_FMI3_CE2_L
NC_FMI3_CE1_L
NC_FMI3_CE0_L
NC_FMI2_WE_L
NC_FMI2_AD
NC_FMI2_AD
NC_FMI2_AD
NC_FMI2_AD
NC_FMI2_AD
NC_FMI2_AD
NC_FMI2_DQS
NC_FMI2_CLE
NC_FMI2_CE3_L
NC_FMI2_CE2_L
NC_FMI2_ALE
FMI1_AD
FMI1_AD
FMI1_AD
FMI1_AD
FMI1_DQS_P
FMI1_CE1_L
FMI1_CE0_L
FMI1_ALE
FMI0_WE_L
FMI0_AD
FMI0_AD
FMI0_AD
FMI0_AD
FMI0_AD
FMI0_ADFMI0_AD
FMI0_DQS_P
NC_FMI0_CE7_L
NC_FMI0_CE6_L
NC_FMI0_CE5_L
NC_FMI0_CE4_L
NC_FMI0_CE3_L
FMI0_CE1_L
FMI0_CE0_L
NC_FMI1_CE2_L
NC_FMI1_CE3_L
NC_FMI1_CE4_L
NC_FMI1_CE7_L
NC_FMI1_CE6_L
NC_FMI1_CE5_L
NC_FMI2_AD
NC_FMI0_CE2_L
NC_FMI2_CE5_L
FMI0_CLE
FMI0_RE_N
NC_FMI3_ALE
NC_FMI3_AD
NC_FMI3_AD
FMI1_RE_N NC_FMI3_RE_L
NC_FMI2_RE_L
GRAPE_FW_DNLD_EN_L
NC_FMI2_AD
FMI0_AD
PM_LCDVDD_PWREN
FMI1_CLE
FMI0_CLE
FMI1_ALE
FMI1_RE_N
FMI1_WE_L
FMI0_RE_N
PPIO_NAND_H4
FMI0_WE_L
FMI0_ALE
SPK_ID
=PP3V0_IO_MISC
FMI1_CE0_L
FMI0_CE0_LFMI1_CE1_L
PPIO_NAND_H4
FMI0_CE1_L
R08341
2
R08311
2
R08361
2
R08321
2
R08031
2
R08021
2
R08011
2
R08001
2
R08131
2
R08121
2
R08111
2
R08101
2
U0600
AE32
AH31
AF31
AD28
AG29
Y29
AH28
AG28
AM31
AF33
AG33
AG35AF35
AH35
AH33
AG31
AG32
AG34
AH32
AE33
AH34
AN34
AJ33
AN33
AD30
AE30
AJ31
AJ30
AL31
AK31
AK35
AL34
AL32
AN35
AK32
AK33
AL33
AK34
AM33
AJ35
AL35
AM35
AB34
AE35
AB28
AA28
AB30
AE28
AF28
AA29
AB31
AB32
AC33
AC31AB33
AC35
AE34
AD34
AD32
AD35
AD31
AD33
AB35
Y33
W31
W28
W29
V30
AG30
AC30
AH30
AE31
W30
Y32
AA34
W33
AA33
V34
AA30
V31
W32
Y30
AA31
AA32
U0600G22
G23
G30
H1
H4
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H30
H34
J2
J8
J9
J10
J11
J12
J14
J16
J18
J20
J22
J24
J26
J31
J34
K3
K8
K9
K10
K11
K13
K15
K17
K19
K21
K23
K25
K27
K34
L32
L1
L4
L8
L10
L12
L14
L16
L18
L20
L22
L24
L26
M2
M3
M8
M9
M11
M13
M15
M17
M19
M21
M23
M25
M27
M30
L34
N3
N8
N10
N12
N14N16
N18
N20
N22
N24
N26
M35
P1
P8
P9
P11
P13
P15
P17
P19
P21
P23
P25
P27
R2
R8
R10
R12
R14
R16
R18
R20
R22
R24
R26
P34
T3
T9
T11
T13
T15
T17
T19
T21
T23
T25
T27
R35
U1
U10
U12
U14
U16
U18
U20
U22
U24
U26
U30
U31
V9
V11
V13
V15
V17
V19
V21
V23
V25
V27
V29
U34
V35
W1
W3
W10
W12
W14
W16
W18
W20
W22
W24
W26
W34
Y9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
Y27
Y28Y31
Y34
R08041
2
05
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
61244
61244
61244
61244
61244
61244
6945
61244
61244
2835
61244
61244
61244
6945
61244
-
8/10/2019 Ipad3 Diagram
7/48
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
OUT
OUT
OUT
OUT
(5 OF 12)
DAC_VREF
DP_PAD_TX0P
DP_PAD_AUXN
DP_PAD_AUXP
EDP_PAD_TX0P
DP_PAD_AVSS_AUX
EDP_PAD_AVSS
DAC_AVSS30D
DP_PAD_AVDDX
DP_PAD_TX2P
DP_PAD_TX1N
DP_PAD_TX1P
DAC_AVSS30A1
DAC_AVSS30A2
DAC_IREF DAC_OUT1
DAC_OUT3
DP_HPD
DP_PAD_DC_TP
DP_PAD_R_BIAS
DP_PAD_TX2N
DP_PAD_TX3N
DP_PAD_TX3P
EDP_HPD
EDP_PAD_AUXN
EDP_PAD_AUXP
EDP_PAD_AVSSP0
EDP_PAD_AVSSX
EDP_PAD_DVDD
EDP_PAD_DVSS
EDP_PAD_R_BIAS
EDP_PAD_TX0N
EDP_PAD_TX1N
EDP_PAD_TX1P
EDP_PAD_TX2N
EDP_PAD_TX2P
EDP_PAD_TX3N
EDP_PAD_TX3P
DP_PAD_AVDDP0
DP_PAD_AVDD
DAC_COMP
EDP_PAD_AVDDX
EDP_PAD_AVDDP0
EDP_PAD_AVDD
EDP_PAD_AVDD_AUX
DP_PAD_DVDD
EDP_PAD_AVSS_AUX
DP_PAD_AVSSP0
DP_PAD_AVSSX
DP_PAD_DVSS
DP_PAD_AVSS
DP_PAD_TX0N
DAC_OUT2
EDP_PAD_DC_TP
DAC_AVDD30D
DAC_AVDD30A
DP_PAD_AVDD_AUX
MIPI_VDD11
MIPI1D_VREG_0P4V
MIPI0D_VREG_0P4V
ISP0_FLASH
SENSOR1_RST
SENSOR1_CLK
SENSOR0_RST
SENSOR0_CLK
MIPI1C_DNDATA0
MIPI_VSYNC
ISP1_SCL
ISP1_PRE_FLASH
ISP1_FLASH
ISP0_SDA
ISP0_SCL
ISP0_PRE_FLASH
MIPI1C_DPDATA0
MIPI1D_VDD18
MIPI0D_VDD18
MIPI0C_DNDATA3
MIPI1C_DNCLK
MIPI1C_DPCLK
MIPI1C_DNDATA1
MIPI1C_DPDATA1
MIPI0C_DPDATA0
MIPI0C_DNDATA0
MIPI0C_DPDATA1
MIPI0C_DPDATA2
MIPI0C_DNDATA2
MIPI0C_DPDATA3
MIPI0C_DPCLK
MIPI0C_DNCLK
MIPI0C_DNDATA1
ISP1_SDA
(6 OF 12)
PART NUMBERALTERNATE FORP AR T N UM BE R B OM O PT IO N REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DRAWI
REVIS
BRANC
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
1.2MA5MA
2MA
332MA
21MA
4MA
DP LANES 2/3 ARE FOR STEVE-NOTE ON
NOTE: 0.6V ANALOG REF
NOTE: 0.6V ANALOG REF
6MA
5MA
2MA5MA
1.2MA
5MA
172MA
14MA
6.3V
0.22UF20%
X5R402
1/20W1%
201
6.34K
MF
10%6.3V
201X5R
0.1UF
X5R6.3V10%
01005
0.01UF
6.3V
01005NP0-C0G
56PF5%
1UF
402
6.3V10%
CERM
6.3V10%0.01UF
X5R01005
0.22UF20%
402X5R6.3V
402X5R6.3V20%0.22UF MF
1/20W
201
0
5%
6.3VNP0-C0G01005
56PF5%
0.1UF10%
201X5R6.3V
1%
201
2001/20WMF MF
201
1/20W1%200
201MF
1%2001/20W
4.99K
1/32W1%
MF01005
0.01UF
01005X5R6.3V10%
NOSTUFF
NP0-C0G01005
6.3V
56PF5%
0
201MF
1/20W5%
01005
56PF
NP0-C0G6.3V5%
6.3V20%
X5R402
0.22UF
402
0.22UF
X5R
20%6.3V
402
0.22UF20%
X5R6.3V
10%6.3V
0.1UF
X5R201
MF1/32W
01005
1%4.99K
01005X5R6.3V10%0.01UF
NOSTUFF
402
1UF10%
CERM6.3V
201
6.3VX5R
10%0.1UF
6.3VX5R201
10%0.1UF
0.1UF
X5R
10%
2016.3V
0.00MF01005
0%1/32W
MF0.00
010050%
1/32W
0201
240-OHM-0.2A-0.8-OHM
201X5R
10%10V
2.2NF10VX5R201
10%2.2NF
28 43
28 43
28 43
28 43
28 43
28 43
37 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
0.1UF
201X5R6.3V10%
2543
2543
2543
2543
2543
2543
25 43
25 43
25 43
25 43
25 42
25 42
25 42
25 42
1/32W
01005MF
1.00K5%
1/32WMF01005
1.00K5%
1/32WMF01005
1.00K5%
1/32WMF01005
1.00K5%
28 43
28 43
28 43
28 43
H4G
OMIT
FCBGA
OMIT
H4GFCBGA
SYNC_MASTER=JOE SYNC_D
AP: TV,DP,MIP
132S0279 132S0154 RADAR:9624625C0960,C0961
NET_SPACING_TYPE=PWR
PP0V4_MIPI1DVOLTAGE=0.4VMIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3MM
=PP1V8_H4
ISP_AP_1_SDA
TP_CAM0_1V2_VDDCORE_EN
ISP_AP_0_SCL
CAM0_RESET_L
ISP_AP_0_SDA
ISP_AP_1_SCL
CLK_CAM_RF
PM_FRONT_CAM_SHUTDOWN
CLK_CAM_FF_R
PM_REAR_CAM_SHUTDOWN
CLK_CAM_RF_R
NC_ISP_AP_1_PRE_FLASH
NC_ISP_AP_1_FLASH
=PP1V8_MIPI_H4
NC_MIPI0C_AP_DATA_N
MIPI1C_AP_CLK_N
MIPI1C_AP_CLK_P
NC_MIPI1C_AP_DATA_N
NC_MIPI1C_AP_DATA_P
MIPI0C_AP_DATA_P
MIPI0C_AP_DATA_N
MIPI0C_AP_DATA_P
NC_MIPI0C_AP_DATA_P
NC_MIPI0C_AP_DATA_N
NC_MIPI0C_AP_DATA_P
MIPI0C_AP_CLK_N
MIPI0C_AP_DATA_N
DAC_AP_VREF
DP_AP_TX_P
DP_AP_AUX_N
DP_AP_AUX_P
EDP_AP_TX_P
DP_AP_TX_P
DP_AP_TX_N
DP_AP_TX_P
DAC_AP_
DP_AP_HPD
TP_DP_AP_ANALOG_TEST
AP_DP_R_BIAS
DP_AP_TX_N
DP_AP_TX_N
DP_AP_TX_P
EDP_AP_AUX_N
EDP_AP_AUX_P
=PP1V1_EDP_PAD_DVDD_H4
AP_EDP_R_BIAS
EDP_AP_TX_N
EDP_AP_TX_N
EDP_AP_TX_P
EDP_AP_TX_N
EDP_AP_TX_P
DAC_AP_COMP
DP_AP_TX_N
DAC_AP_
=PP1V8
DAC_AP_COMP_FTR=PP3V0_VIDEO_H4
CLK_CAM_FF
EDP_AP_HPD
EDP_AP_TX_P
EDP_AP_TX_N
TP_EDP_AP_ANALOG_TEST
MAX_NECK_LENGTH=3MM
MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MMNET_SPACING_TYPE=PWR
VOLTAGE=1.8V
PP1V8_EDP_AVDD_AUX
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3MMNET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.2MMVOLTAGE=0.4V
PP0V4_MIPI0D
DAC_AP_IREF
MIPI1C_AP_DATA_N
MIPI0C_AP_CLK_P
DAC_AP_
=PP3V0_VIDEO_H4
NC_MIPI_VSYNC_H4
=PP1V1_DP_PAD_DVDD_H4
MIPI1C_AP_DATA_P
=PP3V0_IO_H4
=PP1V8_DP_H4
VOLTAGE=1.8VMIN_LINE_WIDTH=0.2MM
PP1V8_DP_AVDD_AUX
MIN_NECK_WIDTH=0.1MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3MM
=PP1V1_MIPI_H4
C09271
2
R09501
2
C09551
2
C09521
2
C09241
2
C09511
2
C09531
2
C09261
2
C09251
2
R09101 2
C09231
2
C09091
2
R09551
2
R09561
2
R0951
2
R09201
2
C09501
2
C09301
2
R09111 2
C09311
2
C09321
2
C09331
2
C09341
2
C09101
2
R09211
2
C09571
2
C09351
2
C09031
2
C09081
2
C09071
2
R09001 2
R09401 2
FL09101 2
C09601
2
C09611
2C09561
2
R09301
2
R09311
2
R09321
2
R09331
2
U0600
G31
D32
G32
F32
D31
E32
F31 G35
G34
G33E31
AL15
C27
C28
C26
C25
D24
D23
D28
D27
B29
A26
A25
B24
B23
B28
B27
D29
F23
A29
C29
E23
A27
A28
D25
D26
B25
B26
C23
C24
AJ15
A23
A24
B18
A18
E19
E18
D20
D19
C21
D18
C18
F19
F18
B20
B19
A21
F20
C22
A22
E20
D21
D22
B21
B22
C19
C20
A19
A20
U0600
AD17
AF13
AK22
AF22
AF14
AE17
AP24
AN23
A32
C35
B32
B30
A30
A33
D35
B33
B31
A31
F25
F26
E35
E34
C34
F35
F34
D34
F28
F29
G24
G25
G26
G27
G28
G29
AD15
AJ24
AK24
AH24
AL24
05
45
4 10 35
26
25 42
25
42
25
42
46
46
35
4346
43 46
43 46
4346
4346
4346
45
35
735
25 42
45
45
735
46
35
935
3545
35
-
8/10/2019 Ipad3 Diagram
8/48
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BIBI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BIBI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BIBI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BIBI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
(7 OF 12)
DDR0_CA0
DDR0_CA1
DDR0_CA2
DDR0_CA3
DDR0_CA4
DDR0_CA5
DDR0_CA6
DDR0_CA7
DDR0_CA8
DDR0_CA9
DDR0_CK
DDR0_CKB
DDR0_CKE0
DDR0_CKE1
DDR0_CSN0
DDR0_CSN1
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR0_DQ0
DDR0_DQ1
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ2
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ3
DDR0_DQ30
DDR0_DQ31
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_NDQS0
DDR0_NDQS1
DDR0_NDQS2
DDR0_NDQS3
DDR0_PDQS0
DDR0_PDQS1
DDR0_PDQS2
DDR0_PDQS3
DDR0_VDDQ_CKE
DDR0_VREF_DQ
DDR0_ZQ
DDR1_CA0
DDR1_CA1
DDR1_CA2
DDR1_CA3
DDR1_CA4
DDR1_CA6
DDR1_CA7
DDR1_CA8
DDR1_CA9
DDR1_CK
DDR1_CKB
DDR1_CKE0
DDR1_CSN0
DDR1_CSN1
DDR1_DM0
DDR1_DM1
DDR1_DM2
DDR1_DM3
DDR1_DQ0
DDR1_DQ1
DDR1_DQ10
DDR1_DQ11
DDR1_DQ12
DDR1_DQ13
DDR1_DQ14
DDR1_DQ15
DDR1_DQ16
DDR1_DQ17
DDR1_DQ18
DDR1_DQ19
DDR1_DQ2
DDR1_DQ20
DDR1_DQ21
DDR1_DQ22
DDR1_DQ23
DDR1_DQ24
DDR1_DQ25
DDR1_DQ26
DDR1_DQ27
DDR1_DQ28
DDR1_DQ29
DDR1_DQ3
DDR1_DQ30
DDR1_DQ31
DDR1_DQ4
DDR1_DQ5
DDR1_DQ6
DDR1_DQ7
DDR1_DQ8
DDR1_DQ9
DDR1_NDQS0
DDR1_NDQS1
DDR1_NDQS2
DDR1_NDQS3
DDR1_PDQS0
DDR1_PDQS1
DDR1_PDQS2
DDR1_PDQS3
DDR0_DQ8
DDR0_DQ9
DDR1_CA5
DDR1_VREF_DQ
DDR1_CKE1
DDR1_VDDQ_CKE
DDR1_ZQ
(8 OF 12)
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ23
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
DDR2_DQ29
DDR2_DQ30
DDR2_DQ31
DDR2_CA0
DDR2_CA1
DDR2_CA2
DDR2_CA3
DDR2_CA4
DDR2_CA5
DDR2_CA6
DDR2_CA7
DDR2_CA8
DDR2_CA9
DDR2_DM0
DDR2_DM1
DDR2_DM2
DDR2_DM3
DDR2_PDQS0
DDR2_NDQS0DDR2_PDQS1
DDR2_NDQS1
DDR2_PDQS2
DDR2_NDQS2
DDR2_PDQS3
DDR2_NDQS3
DDR2_VDDQ_CKE
DDR2_VREF_DQ
DDR2_ZQ
DDR2_CK
DDR2_CKB
DDR2_CKE0
DDR2_CKE1
DDR2_CSN0
DDR2_CSN1
DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DQ8
DDR3_DQ9
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DQ16
DDR3_DQ17
DDR3_DQ18
DDR3_DQ19DDR3_DQ20
DDR3_DQ21
DDR3_DQ22
DDR3_DQ23
DDR3_DQ24
DDR3_DQ25
DDR3_DQ26
DDR3_DQ27
DDR3_DQ28
DDR3_DQ29
DDR3_DQ30
DDR3_DQ31
DDR3_CA0
DDR3_CA1
DDR3_CA2
DDR3_CA3
DDR3_CA4
DDR3_CA5
DDR3_CA6
DDR3_CA7
DDR3_CA8
DDR3_CA9
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
DDR3_PDQS0
DDR3_NDQS0DDR3_PDQS1
DDR3_NDQS1
DDR3_PDQS2
DDR3_NDQS2
DDR3_PDQS3
DDR3_NDQS3
DDR3_VDDQ_CKE
DDR3_VREF_DQ
DDR3_ZQ
DDR3_CK
DDR3_CKB
DDR3_CKE0
DDR3_CKE1
DDR3_CSN0
DDR3_CSN1
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DRAWI
REVIS
BRANC
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
998-3125 0.5MM PT
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
134044
134044
1344
1344
134044
1344
1344
1344
1344
1344
1344
1344
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
1444
13 44
13 44
13 44
13 44
13 44
01005
10%0.01UF
NOSTUFF
6.3VX5R
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
1.00K1%
MF1/32W
01005
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
1/32W1%
MF01005
1.00K
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
10%
01005
0.01UF
NOSTUFF
6.3VX5R
13 44
13 44
13 44
13 44
13 44
13 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
1.00K1%1/32WMF01005
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
MF
1.00K1/32W1%
01005
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
H4GFCBGA
OMIT
H4GFCBGA
OMIT
0.01UF
01005
10%
NOSTUFF
6.3VX5R
1/32W
1.00K1%
MF01005
MF
1.00K1/32W1%
01005
10%
01005
0.01UF
NOSTUFF
6.3VX5R
01005
1/32WMF
1%1.00K
01005
1.00K
MF
1%1/32W
0201
6.3VX5R
0.22UF20%
0201
6.3VX5R
0.22UF20%
0201
6.3VX5R
0.22UF20%
0201
6.3VX5R
0.22UF20%
MF
1%1/20W
240
201
1/20W
240
MF
1%
201
2401%1/20WMF201
2401%1/20WMF201
10%
01005
0.01UF6.3VX5R
NOSTUFF NOSTUFF
10%
01005
0.01UF6.3VX5R
NOSTUFF
0.01UF10%
01005
6.3VX5R
10%
01005
0.01UF
NOSTUFF
6.3VX5R
134044
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
134044
1344
1344
1344
1344
1344
1344
1344
1344
1344
1344
SYNC_MASTER=MIKE
AP: DDR
DDR1_DM
DDR1_DM
H4G_DDR0_ZQ
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.3MM
PPVREF_DDR1_DQ_H4
MIN_NECK_WIDTH=0.2MMVOLTAGE=0.6V
NET_SPACING_TYPE=PWR
PPVREF_DDR1_DQ_H4
PPVREF_DDR0_DQ_H4
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
NET_SPACING_TYPE=PWR
PPVREF_DDR0_DQ_H4
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
PPVREF_DDR2_DQ_H4
NET_SPACING_TYPE=PWR
PPVREF_DDR2_DQ_H4
PPVREF_DDR3_DQ_H4
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0.6V
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
PPVREF_DDR3_DQ_H4
DDR1_DQ
DDR1_DQ
=PP1V2_VDDIOD_H4=PP1V2_VDDIOD_H4
=PP1V2_VDDIOD_H4 =PP1V2_VDDIOD_H4
H4G_DDR1_ZQ
=PP1V2_S2R_H4
NC_DDR1_CKE
DDR1_CA
DDR0_DQ
DDR0_DQ
DDR1_DQS_P
DDR1_DQS_P
DDR1_DQS_P
DDR1_DQS_P
DDR1_DQS_N
DDR1_DQS_N
DDR1_DQS_N
DDR1_DQS_N
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DQ
DDR1_DM
DDR1_DM
NC_DDR1_CSN
DDR1_CSN
DDR1_CKE
DDR1_CK_N
DDR1_CK_P
DDR1_CA
DDR1_CA
DDR1_CA
DDR1_CA
DDR1_CA
DDR1_CA
DDR1_CA
DDR1_CA
DDR1_CA
=PP1V2_S2R_H4
DDR0_DQS_P
DDR0_DQS_P
DDR0_DQS_P
DDR0_DQS_P
DDR0_DQS_N
DDR0_DQS_N
DDR0_DQS_N
DDR0_DQS_N
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DQ
DDR0_DM
DDR0_DM
DDR0_DM
DDR0_DM
NC_DDR0_CSN
DDR0_CSN
NC_DDR0_CKE
DDR0_CKE
DDR0_CK_N
DDR0_CK_P
DDR0_CA
DDR0_CA
DDR0_CA
DDR0_CA
DDR0_CA
DDR0_CA
DDR0_CA
DDR0_CA
DDR0_CA
DDR0_CA
NC_DDR3_CSN
DDR3_CSN
NC_DDR3_CKE
DDR3_CKE
DDR3_CK_N
DDR3_CK_P
H4G_DDR3_ZQ
=PP1V2_S2R_H4
DDR3_DQS_N
DDR3_DQS_P
DDR3_DQS_N
DDR3_DQS_P
DDR3_DQS_N
DDR3_DQS_P
DDR3_DQS_N
DDR3_DQS_P
DDR3_DM
DDR3_DM
DDR3_DM
DDR3_DM
DDR3_CA
DDR3_CA
DDR3_CA
DDR3_CA
DDR3_CA
DDR3_CA
DDR3_CA
DDR3_CA
DDR3_CA
DDR3_CA
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQDDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
DDR3_DQ
NC_DDR2_CSN
DDR2_CSN
NC_DDR2_CKE
DDR2_CKE
DDR2_CK_N
DDR2_CK_P
H4G_DDR2_ZQ
=PP1V2_S2R_H4
DDR2_DQS_N
DDR2_DQS_P
DDR2_DQS_N
DDR2_DQS_P
DDR2_DQS_N
DDR2_DQS_P
DDR2_DQS_N
DDR2_DQS_P
DDR2_DM
DDR2_DM
DDR2_DM
DDR2_DM
DDR2_CA
DDR2_CA
DDR2_CA
DDR2_CA
DDR2_CA
DDR2_CA
DDR2_CA
DDR2_CA
DDR2_CA
DDR2_CA
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQDDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
DDR2_DQ
C10561
2
R10551
2
R10561
2
C10541
2
R10531
2
R10541
2
C10841
2
R10831
2
R10841
2
C10961
2
R10951
2
R10961
2
C10201
2
C10211
2
C10221
2
C10231
2
R10201
2
R10211
2
R10221
2
R102341
2
C10571
2
C10581
2
C10951
2
C10851
2
U0600
G5
G6
H5
H6
J5
M5
M6
N6
P5
P6
P4
N4
J1
K1
K6
J6
E12
E9
C14
D6
B14
B13
B8
C8
B7
B6
C6
D7
B17
C17
B16
E17
D13
D16
E16
C15
D15
E6
B5
C5
E5
C4
D4
C12
B3
C3
D12
B11
C11
B10
C9
D9
A12
A7
A15
A4
A13
A6
A16
A3
G11
D10
M4
E15
F15
F14
E14
F13
E8
F8
F7
E7
F6
F11
F12
A10
A9
F10
E13
L5
N5
G4
R5
H2
H3
P3
R3
U3
T2
U2
R4
C2
D2
E2
E4
J3
E3
F3
F4
G2
R6
T4
U4
V1
V2
V3
J4
V4
V5
K2
L2
K4
K5
N2
P2
G1
M1
D1
R1
F1
N1
C1
T1
N7
L3
E11
U0600
AL6
AK6
AL7
AK7
AL8
AL11
AK11
AK12
AL12
AK13
AM13
AM12
AR10
AR9
AK9
AK8
AD4
AG4
AA6
AK4
AB2
AB3
AH3
AF4
AJ3
AJ2
AK3
AF5
Y2
W2
Y3
W4
AC2
Y4
AA3
AA5
AA4
AL2
AL3
AL4
AM2
AN2
AN3
AC4
AL5
AK5
AE2
AD3
AF2
AE3
AG3
AH2
AD1
AJ1
AA1
AM1
AC1
AK1
Y1
AN1
AE7
AE4
AL9
AB5
AB6
AC5
AC6
AD5
AG5
AG6
AH6
AH5
AJ6
AH4
AJ4
AF1
AG1
AE6
AD6
AM11
AL13
AM6
AK14
AP7
AM7
AL10
AP13
AP14
AM14
AL14
AN14
AP4
AP3
AN4
AM4
AP8
AP5
AN5
AN6
AM5
AN15
AM15
AP16
AM16
AR18
AP17
AN8
AN17
AM17
AN9
AP10
AP11
AN11
AN12
AM10
AR7
AR12
AR4
AR15
AR6
AR13
AR3
AR16
AJ12
AM9
AE5
05
1
8 45
8 45
8 45
845
8 45
845
8 45
8 45
8935
89358935 8935
8 35
46
46
835
46
46
46
46
8 35
46
46
835
-
8/10/2019 Ipad3 Diagram
9/48
(9 OF 12)
VDDVDD
VDDIO18_GPIO
VDDIO18_UART1_TXD0
VDD_CPU
VDDIOD
VDDIOD7
VDDIOD6
VDDIOD5
VDDIOD4
VDDIOD3
VDDIOD2
VDDIOD1
VDDIOD0
VDDIO18_XO0
VDDIO18_FUSE0_FSRC
VDDIO18_UART2_TXD
VDDIO30_USB11
VDDIO30_GPIO_3V0
VDDIO30_DP_HPD
VDDIO30_CFSB(10 OF 12)
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DRAWI
REVIS
BRANC
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PART NUMBERALTERNATE FORP AR T N UM BE R B OM O PT IO N REF DES COM
FMI0-1 88MA
FMI2-3 88MA
1000MA
160MA
44MA
FMI2-3_CEN 2MA
ISP FLASH, SPI3 3MA
UART4 ?MA
GPIO30-39 4MA
2300MA
3800MA
SPI1 1MA
I2C2 1MA
C1100, C1102, C1103, C1121, C1122, C1124, C1154, C1155, C1156, C1191, C1615, C1621, C1721
10%1UF
402CERM6.3V
10%1UF
402CERM6.3V 6.3V
X5R0201
0.22UF20%
6.3VX5R0201
0.22UF20%
402
10%1UF
CERM6.3V
6.3VX5R0201
0.22UF20%
6.3VX5R0201
0.22UF20%
6.3VX5R0201
0.22UF20%
603
10UF
X5R6.3V20%
0610
20%4V
X5R-CERM
4.3UF
603
10UF
X5R6.3V20%
0610
20%4V
X5R-CERM
4.3UF
01005
10%6.3VX5R
0.01UF
01005
10%6.3VX5R
0.01UF
01005
10%6.3VX5R
0.01UF
01005
10%6.3VX5R
0.01UF
01005
0.01UF
X5R6.3V10%
0201
0.22UF
X5R6.3V20%
0201
20%6.3VX5R
0.22UF
0201
20%6.3VX5R
0.22UF
0201
20%6.3VX5R
0.22UF
0201
0.22UF
X5R6.3V20%
0201
0.22UF
X5R6.3V20%
01005
10%0.01UF
6.3VX5R
4.3UF
0610
4VX5R-CERM
20%
10UF
603
6.3VX5R
20%
X5R-CERM0610
4.3UF4V20%
0201
20%6.3VX5R
0.22UF
0402CERM
10U6.3V20%
0201
0.22UF
X5R6.3V20%
6.3V
X5R0201
0.22UF20%
56PF5%
NP0-C0G01005
6.3V
6.3VX5R0201
0.22UF20%
6.3VX5R0201
0.22UF20%
6.3VX5R0201
0.22UF20%
6.3VX5R0201
0.22UF20%
0
5%
NAND_IO_1V8
MF1/20W
201NAND_IO_3V3
MF1/20W
0
5%
201
H4GFCBGA
OMIT
FCBGAH4G
OMIT
01005
5%6.3V
NP0-C0G
56PF
01005
56PF
NP0-C0G6.3V5%
01005NP0-C0G
5%56PF6.3V
01005NP0-C0G
5%56PF6.3V
01005NP0-C0G
5%56PF6.3V
56PF5%
NP0-C0G01005
6.3V
6.3V
X5R0201
0.22UF20%
0610
20%4V
X5R-CERM
4.3UF
0610
20%4V
X5R-CERM
4.3UF
0201
0.22UF
X5R6.3V20%
6.3V
X5R0201
0.22UF20%
0201
0.22UF
X5R6.3V20%
4VX5R-CERM
0610
4.3UF20%
6.3V
X5R0201
0.22UF20%
0610
20%4V
X5R-CERM
4.3UF
603
10UF6.3VX5R
20%
0610
4.3UF
X5R-CERM4V20%
0201
0.22UF
X5R6.3V20%
0201
20%6.3VX5R
0.22UF
0201
20%6.3VX5R
0.22UF
01005
10%6.3VX5R
0.01UF
6.3V
X5R0201
0.22UF20%
0201
0.22UF
X5R6.3V20%
6.3VX5R
0201
0.22UF20%
6.3VX5R
0201
0.22UF20%
0610
4.3UF
X5R-CERM4V20%
6.3VX5R
0201
0.22UF20%
6.3VX5R
0201
0.22UF20%
6.3VX5R
0201
0.22UF20%
6.3VX5R
0201
0.22UF20%
6.3VX5R0201
0.22UF20%
6.3VX5R
0201
0.22UF20%
X5R-CERM4V
0610
4.3UF20%
0610
4V
4.3UF
X5R-CERM
20%4.3UF
X5R-CERM4V
0610
20%
6.3V
56PF5%
NP0-C0G0100501005
NP0-C0G
5%56PF6.3V
6.3VX5R0201
0.22UF20%
138S0657138S0702 QTYC1100,C1102
SY NC_M ASTE R=MI KE
AP: POWER
=PPVDD_SOC_H4
=PPVDD_CPU_H4
=PPVDD_SOC_H4
=PP1V2_VDDIOD_H4
=PP3V0_VDDIOD_H4
MAX_NECK_LENGTH=3 MM
VOLTAGE=1.8V
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
PPIO_NAND_H4
=PP1V8_VDDIOD_H4
=PP1V8_VDDIO18_H4
=PP3V0_IO_H4
=PP1V8_NAND_H4
=PP3V3_NAND_H4
C11971
2
C11961
2
C11921
2
C11951
2
C11241
2
C11321
2
C11311
2
C11221
2
C11211
2
C11301
2
C11291
2
C11911
2
C11941
2
C11031
2
C11021
2
C11111
2
C11101
2
C11091
2
C11041
2
C11081
2
C1159 1
2
C1160 1
2
C1161 1
2
C1162 1
2
C1163 1
2
C1164 1
2
C11651
2
C1166 1
2
C11541
2
C11551
2
C11561
2
C11521
2
C11511
2
C11841
2
C11701
2
C11711
2
C11741
2
C11731
2
C11721
2
C11831
2
C11811
2
C11821
2
C11011
2
C11001
2
C11231
2
C11171
2
C11051
2
C11071
2
C11061
2
C11261
2
C11251
2
C11351
2
C11341
2
C11331
2
C11381
2
C11371
2
C11361
2
C11501
2
C11531
2
C11571
2
C11581
2
C11
2
C11901
2
C11931
2
C11771
2
C11761
2
C11991
2
C11981
2
R11001 2
R11011 2
U0600
AA9
AA11
AC11
U25
U27
V10
V12
V14
V16
W9
W11
W13
W15
AD10
W17
Y10
Y12
Y14
Y16
AE11
AF10
AF11
AF12
AG10
AG11
AG12AG13
AA13
J13
J15
J17
J19
J21
J23
J25
J27
K12
K14
AA15
K16
K18
K20
K22
K24
K26
L9
L11
L13
L15
AA17
L17
L19
L21
L23
L25
L27
M10
M12
M14
M16
AB10
M18
M20
M22
M24
M26
N9
N11
N13
N15
N17
AB12
N19
N21
N23
N25
N27
P10
P12
P14
P16
P18AB14
P20
P22
P24
P26
R9
R11
R13
R15
R17
R19
AB16
R21R23
R25
R27
T10
T12
T14
T16
T18
T20
AC9
T22
T24
T26
U11
U13
U15
U17
U19
U21
U23
U0600
AA19
AA21
AC19
AC21
AC23AC25
AC26
AC27
AD18
AD20
AD22
AD24
AA23
AD26
AE19
AE21
AE23
AE25
AE27
V18
V20
V22
V24
AA25
V26
W19
W21
W23
W25
W27
Y18
Y20
Y22
Y24
AA27
Y26
AB18
AB20
AB22
AB24
AB26
N29
AJ17
AJ22
AJ25
AJ26
T8
V28
V8
AF15
AJ28
M29
N28
Y8
AH20
AK20
AL19
AK30
AH29
AE29
AF29
AB29
AC29
AA7
AB7
AJ10
AJ11
G7
G8
G9
G10
G12
G13
G14G15
AC7
G16
H7
J7
K7
L7
M7
P7
R7
AD7
AF7
AG7
AH7
AJ7
AJ8
AJ9
C11401
2
C11411
2
C11421
2
C11441
2
C11431
2
C11461
2
05
1
9
935
35
935
8 35
35
645
5 35
35
735
-
8/10/2019 Ipad3 Diagram
10/48
IN
OUT
OUT
OU
I
I
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DRAWI
REVIS
BRANC
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
0101
0100
J2A DEV
J2A AP
1111 RESERVED
1101 FMI0/1 4/4 CS
010
CURRENT SETTING ->
001
011
EVT
PROTO 2
100
0100 FMI0 2CS
0010 SPI0 W/TEST0011 SPI1 W/TEST
0000 SPI0
0101 FMI0 4CS
0111 RESERVED
1000 FMI1 2 CS
BOOT_CONFIG[3:0]
0110 FMI0 4CS W/TEST
1010 FMI1 4CS W/TEST1001 FMI1 4 CS
1100 FMI0/1 2/2 CS
FOR REFERENCE
0001 SPI1
PROTO 1 CHINA
PROTO 1 LOCAL3. READ
BOARD REVISION
PROTO 0000
BRD_REV[2-0]
1110 FMI0/1 4/4 CS W/TEST
2. ENABLE PU AND DISABLE PD
1. SET GPIO AS INPUT
S/W READ FLOW
0001
J2 DEV
J2 AP
J1 AP0000
BOARD_ID[2]
BOARD_ID[1]
BOARD_ID[0]
BOARD_ID[3-0]
J1 DEV
BOARD_ID_3
BOARD IDDEVELOPMENT_JTAG
2-WIRE DAP SCAN DUMP
JTAG_DAP
PRODUCTION
3. READ
3. READ
JTAG_DAP
DEVELOPMENT_JTAG
S/W READ FLOW
JTAG
I2C PULL-UPS
0010
0011
1. SET GPIO AS INPUT
1110
1101
1100
FMI0/1 4/4 CS
BOOT_CONFIG[3-0]
BOOT_CONFIG[3] (GPIO29)
BOOT_CONFIG[0] (GPIO18)
BOARD_ID[3]
2. DISABLE PU AND ENABLE PD
FMI0/1 4/4 CS WITH TEST
FMI0/1 2/2 CS
BOOT_CONFIG[1] (GPIO25)
BOOT_CONFIG[2] (GPIO28)
S/W READ FLOW
BOOT CONFIG ID
2. DISABLE PU AND ENABLE PD
DEVELOPMENT_JTAG_TAP
1. SET GPIO AS INPUT
MF
5%
01005
1/32W
10K
J2
442
442
4104245
4
4 10 42 45
201
5%1/20W
10K
MF
5%1/20W
10K
201MF
1/32WMF
5%
01005
10K
NOSTUFF
5%
01005
1/32WMF
DEV
10K
J2A
1/32W
10K
MF
5%
01005
SHORT-01005NOSTUFF
SHORT-01005NOSTUFF
NOSTUFF SHORT-01005
100K
MF1/32W
01005
5%
01005
5%
MF1/32W
10K
1.00K5%1/32WMF01005
1.00K5%1/32WMF01005
1.00K1/32WMF01005
5%5%
01005MF1/32W
1.00K5%1/32WMF01005
1.00K5%1/32WMF
1.00K
01005
NOSTUFF
201
5%
MF1/20W
10K
JTAG_DAP
100
DEVELOPMENT_JTAG_TAP
1/32W
0.00
0%
MF01005
1/32W
0.00
0%
MF
DEVELOPMENT_JTAG_TAP
01005100
JTAG_DAP
1/32W
0.00
0%
MF
DEVELOPMENT_JTAG_TAP
01005
1/20W
10K
MF201
5%
201MF1/20W5%10K
NOSTUFF
MF
10K
201
5%1/20W
AP: MISC & ALIASYNC_MASTER=ALEX
=PP1V8_H4
PP3V0_SENSOR_FLT
I2C0_SCL_1V8
I2C1_SDA_1V8
I2C2_SDA_3V0_ALS
I2C1_SCL_1V8
AP_TESTMODE
BOARD_ID_1
BOOT_CONFIG_1
BOOT_CONFIG_2
=PP1V8_H4
=PP1V8_H4
BOOT_CONFIG_0
BOOT_CONFIG_3
JTAG_AP_TRST_L
AP_FAST_SCAN_CLK
VIDEO_EMI_C_Y
VIDEO_EMI_Y_PR
VIDEO_EMI_CVBS_PB
JTAG_AP_TDO
JTAG_AP_TDI
JTAG_AP_TRST_L
AP_TST_STPCLK
JTAG_AP_SEL
AP_HOLD_RESET
USB_AP_VBUS1
BOARD_ID_2
I2C2_SCL_3V0_ALS
I2C0_SDA_1V8
BOARD_ID_0
GPIO42_BRD_REV2GPIO41_BRD_REV1GPIO40_BRD_REV0
R12051
2
R12021
2 R12101 2
R12121 2
R12131 2
R12111 2
R12141 2
R12071
2
R12081
2
R12091
2
R12011
2
R12001
2
R12031
2
R12061
2
R12041
2
XW1201 1 2
XW1200 1 2
XW1202 1 2
R12601 2
R12611 2
R07061
2
R07051
2
R07041
2
R07031
2
R07021
2
R07011
2
05
1
471035
242645
519223742
52542
242542
52542
4
5
5
5
471035
471035
5
5
4
4
4
4
5
242542
519223742
5
5
5
5
-
8/10/2019 Ipad3 Diagram
11/48
RX_VHIGH/USB_2D+
TX_VHIGH/USB_2D-
CH.3_OUT
CH.2_OUT
CH.1_OUT
VID_EN
USB_1D-
USB_1D+
SEL
DGNDAGND
CH.1_IN
CH.2_IN
CH.3_IN
USB_D-
USB_D+
RX_VLOW
TX_VLOW
VA_1
VDH
VA_0
VDL
OUT
OUT
OUT
OUT
INOUT
IN
BI
BI
BI
BI
IN
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DRAWI
REVIS
BRANC
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PART NUMBERALTERNATE FORP AR T N UM BE R B OM O PT IO N REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
CVBSIN
BB USB H4P FS USBDOCK_BB_EN = 0:
DOCK_BB_EN = 1: BB USB DOCK SERIAL
NOTE:
H4P UART0 DOCK SERIAL
NOTE: PLACE R0960-62 NEAR U0900
CIN
YIN
~15MA
THS7380IZSYRUCSP
CRITICAL
10 27 43
10 27 43
75
1/20WMF
1%
201
JTAG_DAP
201MF
1%
75
JTAG_DAP
1/20W
201
1%
MF
75
JTAG_DAP
1/20W
10 27 43
6.3V
0.1UF10%
X5R201
MF
100K5%
1/32W
01005
27 42
27 421542
1542
3042
3042
4 42
4 42
743
743
743
010056.3V
5%
NP0-C0G
56PF
6.3V
0.1UF10%
X5R201
100K5%MF01005
1/32W
5
37
1/32W
01005
5%1.00M
MF
RADAR:9009078U1300343S0539 343S0520
AP: VIDEO BUFFER,BB US
SYNC_DSYNC_MASTER=CHOPIN
=PP3V0_VIDEO_BUF
BUF_C_Y
USB11_ACC_RX_P
=PP3V2_S2R_USBMUX
BUF_Y_PR
PORT_DOCK_VIDEO_AMP_EN
DAC_AP_OUT1
DAC_AP_OUT3
DAC_AP_OUT2 VIDEO_EMI_CVBS_PB
VIDEO_EMI_Y_PR
VIDEO_EMI_C_Y
USB11_MUX_D0_N
DOCK_BB_EN
BUF_CVBS_PB
USB11_MUX_D0_P
USB11_ACC_TX_N
USB_BB_D_N
USB_BB_D_P
UART0_MUX_RXD
UART0_MUX_TXD
U1300
B2
B3
A3 A2
A4 A1
B4 B1
D3
E3
E1
E4
C2
D1
D4
F1
F2
F4
F3
C1
C4
E2
D2
C3
R13601 2
R13611 2
R13621 2
C13701
2
R13721
2
C13011
2
C1300 1
2
R13201
2
R13151
2
05
1
35
43
35
43
43
-
8/10/2019 Ipad3 Diagram
12/48
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IO0-1
IO7-1
IO6-1
IO3-1
IO4-1
IO5-1
IO1-1
IO2-1
IO7-0
IO5-0
IO6-0
IO4-0
IO2-0
IO3-0
IO1-0
IO0-0
VCC
CLE1
CE1*
CLE0
CE0*
WE0*
ALE0
RE0
RE0*
DQS0*
R/B0*
DQS0
ALE1
WE1*
RE1
RE1*
DQS1
DQS1*
R/B1*
ZQ
VREF
VSSQVSS
VCCQVDDI
TMSC
TCKC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IO0-1
IO7-1
IO6-1
IO3-1
IO4-1
IO5-1
IO1-1
IO2-1
IO7-0
IO5-0
IO6-0
IO4-0
IO2-0
IO3-0
IO1-0
IO0-0
VCC
CLE1
CE1*
CLE0
CE0*
WE0*
ALE0
RE0
RE0*
DQS0*
R/B0*
DQS0
ALE1
WE1*
RE1
RE1*
DQS1
DQS1*
R/B1*
ZQ
VREF
VSSQVSS
VCCQVDDI
TMSC
TCKC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NC
NC
NC
NC
NC
NC
NCNC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DRAWI
REVIS
BRANC
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
LEAVE VREF AS TP FOR M
DO NOT PLACE IN NAND SINGLE PCS
TEST POIN
LEAVE VREF AS TP FOR MLB
10UF
CERM-X5R0402-1
6.3V20%
CERM402-LF
2.2UF6.3V20%
0.1UF10%
201
6.3V
X5R
6 12 44
6 44
6 12 44
6 12 44
6 12 44
6 12 44
6 12 44
6 44
6 12 44
6 12 44
6 12 44
6 12 44
MF1/20W1%243
201
0.1UF10%
201
6.3VX5RCERM-X5R
0402-1
10UF6.3V20%
0402-1CERM-X5R
10UF6.3V20%
0402-1CERM-X5R6.3V20%10UF
LGA
OMIT
XXNM-XGBX8-MLC-PPN1.5-ODP
6.3VX5R0201-MUR
1.0UF20%
61244
61244
61244
61244
61244
61244
61244
61244
61244
61244
61244
61244
61244
61244
61244
61244
MF1/20W5%1K
NOSTUFF
201
1K5%1/20WMF
NOSTUFF
201
0402-1CERM-