Ion implantation effects on GaAs MESFETs

6
250 IEEE TRANSACTIOKS ON ELFC'IKON DFVICkS. VOI, 36. NO 2. FFHKII,\\KY lYXL) I I I loi8: ' 60 keV Si ions - 't * .+ I. + -.+ t *., t '..+ t 1015 ".t + : tt SIMS profile i TRIM profile : Pearson-IV fit -*+.. : ____________--- t I I I d4 Ion Implantation Effects on GaAs MESFET's Absfrucf-We report calculations of ion-implantation effects on the uniformity and the ultimately achievable performance of GaAs MES- FET's. The results of an extensive study of the profiles of Si, Se, and Re inns implanted into GaAs are incorporated into a combined process and device model for GaAs MESFET technology. Effects considered are the scaling of transconductances with implantation energy, implant profile and impurities effects on lo\r-gate-bias transconductances, dopant diffusion during annealing, encapsulant-thickness and etch- depth effects on threshold-voltage uniformity, and recoil-atom effects on threshold voltages for implants through SizN4 and SiOLcaps. I. INTRODUCTION ON implantation is the most widely used process in the I semiconductor industry for introducing controlled im- purity concentrations into Si. GaAs, and other materials. However, many effects are associated with ion implanta- tion that require a clear, quantitative understanding to maximize the performance and uniformity of devices manufactured using this technique. As part of an effort to develop process and device models for GaAs MESFET technology, we have made a systematic series of secondary-ion-mass spectrometry (SIMS) measurements of the profiles of Si, Se, and Be ions implanted into bare and ( SiO, and Si,NJ) encapsu- lated GaAs wafers [I]. Contrary to LSS [2] and Monte Carlo [3] calculations for implantation into amorphous materials, the profiles in GaAs are not near-Gaussian, but have large, exponential tails due to ion channeling in the GaAs crystal, such as that shown in Fig. 1 for 60-keV Si ions. The dependences of these profiles on ion energy, dose, wafer tilt and rotation angles, dislocation density, and cap thickness were discussed in an earlier paper [ 11. The present work examines how these profiles can af- fect GaAs MESFET electrical device characteristics. To illuminate implantation effects, we have used our com- bined process and device model GATES [4], [5] (in [4], GATES was called GEM) to calculate device threshold voltages, currents, and transconductances. This modeling program is discussed in Section 11. The present calcula- tions address issues of how to maximize the performance and uniformity of GaAs MESFET's. In consideration of Manuscript received May 3 1. 1988: revised September 2 1, 1988. This work was supported by the Wright-Patterson Air Force Materials Labora- tory under Contract F33615-85-C-5048. R. Anholt was with the Solid State Electronic, Laboratory. Stanford UniLersity, Stanford. CA 94305. He is now with Gatewa) Modeling. Inc.. Minneapolis. MN 55414. T. W. Signion i$ with the Solid State Electronics Laboratory. Stanford University. Stanford. CA 94305. IEEE Log Nuinbcr 8825245. Fig. 1. Compariwn of a SIMS measurement of a profile for 60-keV Si ions in GaAs with a Monte Carlo calculation [3] and with a fit to a Pearson- IV profile [I]. device performance, a primary question considered is how much do the shapes of the implant and resulting electron carrier profiles limit the ultimate transconductances ob- tainable for ion-implanted MESFET's? In Sections 111-A and 111-B, transconductance calculations for different en- ergy implants and MESFET biases are shown. Four pos- sible effects on device uniformity are considered in the remaining part of Section 111: the effects of cap thickness and etch-depth fluctuations on MESFET threshold-volt- age uniformity, of dopant diffusion during post-implant annealing, and the effects of Si-recoil ion distributions for implants through caps. A previous work considered the effects of wafer tilt and rotation angles on device thresh- old voltages [6]. 11. MODEL A combined process and device model for GaAs MES- FET technology, Gallium Arsenide Transistor Engineer- ing models (GATES) has been developed [4]-[5]. Pear- son-IV functions are used to describe the profiles of Si, Se, and Be ions in GaAs, using the parameters given in [ 11. The model determines the electron carrier profiles in one dimension by solving Poisson's equation [7] for no gate bias, and with the surface boundary condition dn (x) /ds = 0, corresponding to no electron diffusion out of the GaAs material. Once n(x) is obtained, the MES- FET pinchoff voltage is calculated using nm 0018-938318910200-0250$01 .OO 0 1989 IEEE

Transcript of Ion implantation effects on GaAs MESFETs

Page 1: Ion implantation effects on GaAs MESFETs

250 IEEE TRANSACTIOKS O N ELFC'IKON DFVICkS. VOI, 36. N O 2 . FFHKII,\\KY lYXL)

I I I loi8: ' 60 k e V Si i ons

-

't * .+ I. +

-.+ t *., t '..+ t 1015 ".t + : tt SIMS profile

i TRIM profile : Pearson-IV fit -*+.. : _ _ _ _ _ _ _ _ _ _ _ _ - - -

t I I I d4

Ion Implantation Effects on GaAs MESFET's

Absfrucf-We report calculations of ion-implantation effects on the uniformity and the ultimately achievable performance of GaAs MES- FET's. The results of an extensive study of the profiles of Si, Se, and Re inns implanted into GaAs are incorporated into a combined process and device model for GaAs MESFET technology. Effects considered are the scaling of transconductances with implantation energy, implant profile and impurities effects on lo\r-gate-bias transconductances, dopant diffusion during annealing, encapsulant-thickness and etch- depth effects on threshold-voltage uniformity, and recoil-atom effects on threshold voltages for implants through SizN4 and SiOL caps.

I . INTRODUCTION ON implantation is the most widely used process in the I semiconductor industry for introducing controlled im-

purity concentrations into Si. GaAs, and other materials. However, many effects are associated with ion implanta- tion that require a clear, quantitative understanding to maximize the performance and uniformity of devices manufactured using this technique.

As part of an effort to develop process and device models for GaAs MESFET technology, we have made a systematic series of secondary-ion-mass spectrometry (SIMS) measurements of the profiles of Si, Se, and Be ions implanted into bare and ( SiO, and Si,NJ) encapsu- lated GaAs wafers [ I ] . Contrary to LSS [2] and Monte Carlo [ 3 ] calculations for implantation into amorphous materials, the profiles in GaAs are not near-Gaussian, but have large, exponential tails due to ion channeling in the GaAs crystal, such as that shown in Fig. 1 for 60-keV Si ions. The dependences of these profiles on ion energy, dose, wafer tilt and rotation angles, dislocation density, and cap thickness were discussed in an earlier paper [ 11.

The present work examines how these profiles can af- fect GaAs MESFET electrical device characteristics. To illuminate implantation effects, we have used our com- bined process and device model GATES [4], [ 5 ] (in [4], GATES was called GEM) to calculate device threshold voltages, currents, and transconductances. This modeling program is discussed in Section 11. The present calcula- tions address issues of how to maximize the performance and uniformity of GaAs MESFET's. In consideration of

Manuscript received May 3 1. 1988: revised September 2 1 , 1988. This work was supported by the Wright-Patterson Air Force Materials Labora- tory under Contract F33615-85-C-5048.

R . Anholt was with the Solid State Electronic, Laboratory. Stanford UniLersity, Stanford. CA 94305. He is now with Gatewa) Modeling. Inc.. Minneapolis. MN 55414.

T. W . Signion i $ with the Solid State Electronics Laboratory. Stanford University. Stanford. CA 94305.

IEEE Log Nuinbcr 8825245.

Fig. 1 . Compariwn of a SIMS measurement of a profile for 60-keV Si ions in GaAs with a Monte Carlo calculation [ 3 ] and with a f i t to a Pearson- IV profile [ I ] .

device performance, a primary question considered is how much do the shapes of the implant and resulting electron carrier profiles limit the ultimate transconductances ob- tainable for ion-implanted MESFET's? In Sections 111-A and 111-B, transconductance calculations for different en- ergy implants and MESFET biases are shown. Four pos- sible effects on device uniformity are considered in the remaining part of Section 111: the effects of cap thickness and etch-depth fluctuations on MESFET threshold-volt- age uniformity, of dopant diffusion during post-implant annealing, and the effects of Si-recoil ion distributions for implants through caps. A previous work considered the effects of wafer tilt and rotation angles on device thresh- old voltages [6].

11. MODEL A combined process and device model for GaAs MES-

FET technology, Gallium Arsenide Transistor Engineer- ing models (GATES) has been developed [4]-[5]. Pear- son-IV functions are used to describe the profiles of Si, Se, and Be ions in GaAs, using the parameters given in [ 11. The model determines the electron carrier profiles in one dimension by solving Poisson's equation [7] for no gate bias, and with the surface boundary condition dn ( x ) / d s = 0, corresponding to no electron diffusion out of the GaAs material. Once n ( x ) is obtained, the MES- FET pinchoff voltage is calculated using

n m

0018-938318910200-0250$01 .OO 0 1989 IEEE

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25 I

TABLE 1

C A L C L L A I I O S S D I: F A I1.7 DF V i ('I-, Pj\ R 4 hf f. I tiKS US F 1) I \ Df. I'L hTIO% - M 0 i ) t M ES F ET

Parameter Symbol Value

Threshold vologe

Schottky barrier height

Operating temperature

Activation

"th -0.5v

"bi 0.78V

T 300°K

r) 80%

Series Source or Drain Resistance Rs. R D 1R-mm

Gate length Lg 1 pm

Gate S id th normalization W Imm

Wafer Acceptor impurity concentration NA 3 x I01Kcm-3

2xI0'6cmP Wafer EL2 concentration NEL2

and the threshold voltage VI,, is obtained from

where V,, = 0.78 V is the Schottky-barrier height for most gate metals on GaAs. The MESFET I-V characteristics are calculated using the two-piece mobility approximation by generalizing the methods of Puce1 et al. [8] to use the arbitrary electron profiles obtained from our zero-bias Poisson solutions [ 91. This method assumes abrupt deple- tion of the electron profile when gate bias is applied. All of the transconductances for selected gate and drain volt- ages are calculated analytically. For the electron mobility and saturated velocity, compensation and carrier-density effects 191, similar to those tabulated by Walukiewicz et al. [ lo] , are included. Table I lists the parameters used, except where noted, for the calculations presented in this paper.

111. RESULTS A . Projile Effects on MESFET Transconductarzccs

Narrower carrier profiles give higher MESFET trans- conductances. For FET's operating in the saturated-cur- rent regime, and fabricated using epitaxial layers of thick- ness a , the transconductance at gate bias V , and any drain bias on the saturated part of the I-V curves varies as 18, eq. (23b)l

(3 )

where W is the FET width and U , is the saturated electron velocity. This equation suggests a method for comparing transconductances of ion-implanted MESFET's with dif- ferent profiles, biases, and threshold voltages. To gauge the dependence on the profile that determines the param- eter U in (3), one must keep all other factors in (3) con- stant. Therefore, in Fig. 2 we plot calculated transcon- ductances for FET's with constant threshold voltage ( Vrl,

( a ) ( b )

Fig. 2 . Calculated tranwonductances ,Y,~, at Lero gate volta@c a n d on dose needed to obtain a constant thre\hold \ol tage of -0 .5 V lor MESFET'\ fabricated by implanting SI ions w i t h encrgirs bet\+een I O and 7-00 h c V into GaAa. For the solid line. a Pearson-1V profile. ba\ed on fits to nwa- atirenients h a s used. For the dashed and dah-dotted linea. Gau\hian pro- tiles were used. based on TRIM [3] and LSS 121 calculations 0 1 R;, and A K .

= -0.5 V) , VI,! = 0.78 V, gate voltage ( V , = 0 V ) . and width ( W = 1 mm) . The drain bias was kept at 2 V , though similar results were obtained at all drain biases greater than - 1 V. Although our model uses saturated velocities that vary slowly with the absolute doping. th: average saturated velocity is approximately 1.2 X 10 cm/s for all profiles shown in Fig. 2 . ; therefore. the tran- sconductance variations with implant energy directly re- flect profile effects. The threshold voltages were kcpt con- stant by varying the ion doses, which are shown i n Fig.

Three different types of profiles are compared i n Fig. 2: profiles derived from the LSS tables 121. TRIM Monte Carlo profiles 131, and measured profiles, fit to Pearson- IV functions. The LSS tables predict lower values of R,, than TRIM, which in turn predicts lower values than ex- periment. Since the pinchoff voltage varies roughly as the product of the dose and the effective moment of the im- plant distribution, to keep V,, or V,,, constant. higher doses are required using LSS profiles than the Pearson-IV pro- files to obtain the same threshold voltage. However. with the doses adjusted, the resulting transconductances for the LSS profiles are larger than for the TRIM and measured profiles.

None of transconductances increase inversely with the ion energy E. In part this occurs because the first moment of the distribution R,] only varies as E" x5 : but other fac- tors, such as AR,] , the profile shapes, and the absolute magnitude of the donor doping, compared to the wafer acceptor impurity concentrations also play a role in de- termining the pinchoff voltage and transconductance. As the ion energy decreases from 200 to 20 keV, the trans- conductances for the measured profiles only increase by a factor of 3 to 4. Between 30 and 10 keV. g,,, only in- creases from 150 to 225 mS/mm. which is much less than a factor of three. Sugitani et al . [ I I ] noted a similar slow increase in effective layer thicknesses ( a in ( 3 ) ) for I O - , 20-, and 30-keV Si implants in GaAs. derived by fitting observed distributions to Gaussian functions. and using

a b ) .

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252 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 36, NO. 2, FEBRUARY 1989

the first and second moments of the distributions to obtain effective layer thicknesses a in (3).

Since Se implant profiles for ion energies scaled ac- cording to E,, = 0.829 E;:* are essentially identical to Si profiles implanted at an energy Esi, [ l ] the results shown in Fig. 2 may also be applied to Se channel im- plants.

B. Maximizing low-bias transconductances For MESFET’s fabricated for small-signal microwave

amplifier applications, high transconductances are needed at low gate voltages (low dc source-drain currents IDS) to achieve high gain at low power levels. The best practical channel profile for achieving this is a “box” or epitaxial- layer profile, where the donor-impurity concentration falls off from a constant value to background levels over a few atomic layers. Gaussian implant profiles are less desir- able, but the observed implant profiles, with their expo- nential tails due to ion channeling, are even less optimal. Fig. 3 compares calculated transconductances as a func- tion of ZDs /ZDss for each of these profiles ( I D S S = IDS( Vg = 0, V, = 3V)). The box profile has a constant doping concentration of 2.2 X 10’’ cm-3 to a depth of 0.165 pm. The implant profiles for 100-keV Si use a Gaussian pro- file, derived from TRIM Monte Carlo [3] calculations, and a Pearson-IV profile, derived from SIMS measure- ments. For both the Gaussian and Pearson-IV profiles, a dose of 5 x 10I2 ions/cm2 was used, and recess etching to obtain a -3-V threshold voltage was done. The chan- nel donor profiles are shown in Fig. 3(b). Fig. 3(a) shows that, at a gate-bias of 0.1 IDss, the transconductances are only 70 mS/mm for the Pearson-IV, but are 80 mS/mm for the box profile. Due to differences in the exact shapes and magnitudes of the doping profiles, the three do not give exactly identical transconductances at high IDS; if normalized to the same transconductance at loss, the dif- ferences between the transconductances for the box and Pearson-IV profiles become even greater.

Although the Pearson-IV donor profile is very broad compared to the two other profiles, much of the channel- ing tail is cut off by the depletion region of the substrate junction created by the implanted donors and the substrate acceptors, assumed in Fig. 3 to be at a typical concentra- tion of 3 X 1015 cm-3 for LEC GaAs wafers [12]. The resulting electron profiles are more Gaussian than the do- nor atom profiles, which significantly improves the low- bias transconductances. Fig. 4 shows electron profiles and corresponding transconductances for various substrate ac- ceptor concentrations for devices implanted with 5 X 10l2, 100-keV Si ions/cm2, and etched to achieve a -3-V threshold voltage. For a high-purity wafer without accep- tor impurities, the electron and donor profiles are nearly identical, with the transconductance at 0.1 IDSS being less than 60 mS/mm. Carbon acceptor concentrations be- tween l and 6 X 1015 cmP3 can be present in LEC-grown GaAs. Fig. 4 suggests that the mid-range concentration of 3 X 1015 cmP3 is nearly optimal. For higher concen-

1 I Prolile Etlects

- 120

5 100

40- ’ 10141 -- Pearson 1 IV 1 I ‘\, I 0 0 02 0 4 0 6 0 8 1 0 0 0 0 1 0 2 0 3

DEPTH (pn) ~ D S ~ ~ D S S

(a) (b) Fig. 3 . (a) Transconductances of recess-etched MESFET’s versus the dc

source-drain current, normalized to the zero-gate-voltage value. Calcu- lations were made using Pearson-IV profiles, Gaussian profiles, and con- stant-doping (BOX) donor profiles, which are shown in (b).

Impurities

E

0.0 0.2 0.4 0.6 0.8 1.0

IDS~~DS s

(a)

I I

0 0 0 1 0 2 0 3 0 4 0 5

DEPTH (p)

(b)

Fig. 4. Transconductances of recess-etched MESFET’s versus the dc source-drain current (normalized to the zero-gate-voltage value), cal- culated using simulations of measured implant profiles for 5 x IO” 100- keV Si ions/cm’, and assuming various wafer acceptor impurity con- centrations. The corresponding electron carrier profiles after recess etch- ing to obtain a -3-V threshold voltage are shown in (b).

trations, the corresponding transconductances at all biases are lower, which is due to profile-shape effects.

Implanting buried p-layers has been proposed as a tech- nique to sharpen the fall off of the channel electron carrier profiles [13], which is expected to improve the low-bias transconductances. In Fig. 5, we show calculations for 100-keV Si/l35-keV Be co-implants at various Be ion doses. The substrate acceptor impurity level of 3 x 1015 cmP3 is assumed to be present for all cases. Using the buried p-layer improves the low-bias transconductances over those obtained with just the standard 3 X l O I 5 cmP3 substrate acceptor level. However, the high-bias trans- conductances are lower.

C. Difision during annealing For Si and Se ions implanted to concentrations less than

10” cmP3 in GaAs, the diffusion constants for typical fur- nace anneals ( T A < 900°C) are less than cm2/s (Se) and .cm2/s (Si) [14], [15]. Also, neither the outdiffusion of Si or Se ions into Si3N4 or Si02 caps nor the indiffusion of Si from the caps has been observed. As- suming that the diffusion coefficients D ( TA ) for anneal temperature TA are independent of electric-field and dopant concentration effects, the diffused concentration C(x) after a time t is calculated from the as-implanted

Page 4: Ion implantation effects on GaAs MESFETs

4NHOI.T 4 i i D SlGhlON. IOK-IhlPLANTA'I'ION EFFECTS ON GaAs MESFET'S 253

140- A

00 0 2 0 4 06 08 1 0 00 0 1 02 0 3 0 4

I D S I D S S DEPTH (urn)

(a) (b)

Fig. 5 . SIIIIIC as Fig. 1. I n addition to the standard 3 x 10l5 tin-'acceptor inipurities. implants of 135-kcV Be ions at doscs at 0.5 and 1 x I O " c n - are done.

concentration C ' ( x ) using [ 161

J 0

+ exp

This equation satisfies boundary condition at

(4 )

Fick's diffusion equation, with a he surface ( x = 0)

= o dC d.r - ( 5 )

corresponding to no transport of the implanted species across the GaAs-cap interface.

Fig. 6 shows how diffusion affects calculated threshold voltages for Se-ion-implanted MESFET's annealed at 900°C. To first order, diffusion only broadens the pro- files, but since the threshold voltages depend critically on the first moment, little effect of diffusion is seen. Thresh- old voltages are affected when the diffusion lengths - c t begin to exceed the first moment of the as-im- planted distributions. By this argument we can derive the following criterion: diffusion during annealing affects MESFET threshold voltages if

JDt RI, - tcapR,,,lR[>cap. (6) Here, RI,, and R,Jci,p are the projected ranges in amorphous &As and in the cap, is the cap thickness, and Rp is the range in crystalline GaAs [ I ] . The factor involving reap describes shifts in the distributions due to implanting through caps, as described in [ I ] . The arrows in Fig. 6 indicate the minimum annealing time t where (7) is sat- isfied. The device threshold voltages change by less than SO mV up to where (7) is satisfied, then decrease more steeply for longer anneals. Using this criterion, we can conclude that diffusion during annealing is more impor- tant for low-energy implants, and for implants through thick caps, where the effective moment of the implant dis- tribution is smallest. This argument considers only verti- cal diffusion. There is evidence that for self-aligned MES- FET's, lateral diffusion of dopants may significantly aff'ect threshold voltages even for rapid-thermal-annealed MES- FET's [ 171.

S e Ions in GaAs ~- -p- D - 10~'4 cms s T=903 C

02 Implbnfs Throuqh

0 0 Bare Wafer Implants

- 1 0 I

,L i-~~i ~--.~L~.-A 0 30 60 0 33 63 5'

ANNEAL TlhlE m . 1

Fig. 6. Threshold voltages versus annealing time for 100-. 300-. and 300- keV Se ions implanted into bare wafers and for 300-keV Se ions i n - planted through 25- to 100-nin S I ~ N , caps. The arroLcs indicate the inin- iniuni time where (6) is satisfied.

D. Process Sensitivitj Implanting through Si,N, or SiOz caps has the benefi-

cial effect of reducing the sensitivity of device threshold voltages and other characteristics to implant tilt and ro- tation angles [ 11. On the other hand, the threshold volt- ages then become sensitive to the cap thickness and den- sity. Fig. 7 illustrates changes in threshold voltage due to changes in cap thickness for MESFET's implanted with 60- to 200-keV Si ions in the channel. These calculations are for a constant threshold voltage of -0.5 V. so for increasing cap thickness or decreasing implant energy, the ion dose is increased. Once the dose was ad.justed, the change in threshold voltage due to a 1- to 2-inm change in cap thickness was calculated. Clearly, the minimum sensitivity occurs only at vanishing cap thickness. The sensitivities are largest for low ion energies, where the ratio of cap thickness to the projected range in GaAs is largest. To achieve a uniform wafer-to-wafer threshold- voltage uniformity of <20 inV for 80-keV Si ions im- planted through 50-nm caps, the cap thickness must be controlled to within < 1 nm.

For devices with recess-etched gates, the etch depth must be tightly controlled for good uniformity. Fig. 8 shows calculated sensitivities of threshold voltages due to small etch depth variations for 60- to 200-keV Si ion-im- planted MESFET's. Here, the initial implants are done into unencapsulated wafers with the doses adjusted to ob- tain constant -0.5-V threshold voltages. Unlike the quadratic sensitivity to cap thickness, the changes in threshold voltage with etch depth are nearly linear and approach constants when the etch depth exceeds the peak position of the implant concentration (indicated by arrows in Fig. 8). Also, the sensitivity to etch depth is smaller than that to cap thickness.

E. Recoil ion effects When ions are implanted through Si3N, and Si02 lay-

ers, Si, 0, or N atoms are knocked forward into the GaAs. The Si ions are additional donors, resulting in higher car-

Page 5: Ion implantation effects on GaAs MESFETs

~

254

Process Sensitivity

Target Vlh = -0 5 V 1 Implants Through Si3Nd Caps

01 0 50 100 150

CAP THICKNESS x (nm)

Fig. 7. Changes in threshold voltages due to changes in the cap thickness for 60- to 200-keV Si ion-implanted devices with doses varied to achieve a constant -0.5-V threshold voltage. The results in Figs. 7 and 8 can be scaled to other processes by multiplying dV, , , /dr by the ratio of the desired pinchoff voltage to that used here, 1.28 V .

IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36. NO. 2. FEBRUARY 1989

1 Process Sensitivity Recess Etching

40

60 keV SI i

>

9 201

10

50 100 150 RECESS DEPTH x jnm)

Fig. 8. Changes in threshold voltage due to changes in recess etch depth for 60- to 200-keV Si ion-implanted devices with doses varied to achieve a constant -0.5-V threshold voltage. The implants are done into unen- capsulated wafers.

rier concentrations. The N and 0 ions can compensate some of the Si donors, leading to smaller electron con- centrations [ 181, [ 191.

At the shallow depths where the recoil atom concentra- tions are large compared to those of the implanted ions, the recoil profiles can be predicted accurately using the TRIM Monte Carlo code [l] , [3]. An extensive set of TRIM calculations were made of recoil-atom distribu- tions, resulting from Si and Se implants through Si3N, and SiOz caps at energies between 60 and 400 keV (100 to 400 keV for Se) . The recoil-atom distributions were ac- curately fit to the expression [20]

where x is the depth in the GaAs in nanometers, and n ( = 1 to 1.5), B and A are parameters dependent on the ion energy, the cap thickness, the implant ion, and the recoil atom (Si, 0, or N ) .

Fig. 9 shows calculations of Si recoil-atom concentra- tions resulting from a 300-keV Se implant through a 100- nm Si,N, overlayer. The parameter B for this implant is

0 1 0 2 0 3 0 4

DEPTH (rim) 00

Fig 9 Concentratton? of Se ]on\ impldnted through 100-nm SI,N, caps and the concentrattons of knocked-on SI atoms from the cap

-0 50

-0 5 1

0 54 - 5 5 L

-0 56

-0 58

so 100 150 -0 60

CAP THICKNESS (nrn)

Fig. I O . The effects of knocked-on Si atoms on device threshold voltages when 60- to 200-keV Si ions arc implanted through Si,N, caps. Without recoils, a -0 .5-V threshold voltage was obtained for all ion energies and cap thicknesses, then the recoil distributions were added. resulting in the threshold voltages shown.

-0 5 y--- 1 S e Ions SigNd Caps Si Recoil Effects

l

I ~--d

0 50 100 150 CAP THICKNESS (nm)

Fig. 1 1 . Same as Fig. I O , for Se ion implantation through Si,N, caps.

approximately 300 nm; therefore, the recoil-atom concen- trations fall off as a power law function of depth for most depths shown in Fig. 9.

Figs. 10 and 11 show the effects of Si recoil atoms on MESFET threshold voltages. For these calculations, the ion dose was adjusted to obtain an initial threshold volt- age of -0.5 V, then the recoil atom distribution was added, and the threshold voltage was recomputed. For a

Page 6: Ion implantation effects on GaAs MESFETs

A N H O L I A N D SIGMON I O N - I b f P l - A N l A I ION EFFECTS O N Gal\\ MhSFLT'S

Si ion primary implant, the threshold voltages become as much as 60 mV more negative, while for the larger-mass Se ions. 300 mV changes are found. For a Be implant, with a typical buried-p-layer implant dose, the change in threshold voltage due to recoils is less than 3 mV. The maximum cap thicknesses rcZlp considered in these calcu- lations are about 1.5R,,,, where R,,, is the projected ion range in amorphous GaAs [ I ] .

IV. CONCLUSIONS In this paper we have addressed several ion-implanta-

tion effects on GaAs MESFET's. With decreasing chan- nel implant energy E , transconductances increase less quickly than 1 / E ; the increase over a factor of 10 reduc- tion in E is found to be only a factor of 3 to 4. At IOW gate biases, transconductances for implanted devices are smaller than for box profiles. The presence of substrate acceptors or implanted buried p-layers is found to im- prove low-bias transconductances.

A criterion has been derived to determine whether or not dopant diffusion during post-implant annealing affects device characteristics. For Si and Se at typical channel implant doses and energies, and with typical 800-850°C furnace or rapid thermal anneals, dopant diffusion effects on MESFET threshold voltages are insignificant.

Calculations are presented for the effects of cap-thick- ness and recess-etch depth fluctuations on threshold volt- ages. Also, for implantation through these SiOz and Si3N, layers, Si atoms from the cap that are knocked forward into the GaAs change threshold voltages by up to 60 mV for Si or 300 mV for Se ion implantation (for a target threshold voltage of -0.5 V ) .

A quantitative understanding of these effects should greatly benefit the design and optimization of GaAs MES- FET's for digital and monolithic-microwave applications.

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*

Robert Anholt (M'88) recei\ed the Ph D degree in nuclear chemistry trom the Uni ien i ty 0 1 Cali fornia at Berkele) in 1976

Between 1976 and 1986. he u d s d Rewarch A\wciate dt the Department ot Ph\ \ I C \ Stanlord University. uhere he \tudied electroniL and n u - clear excitdtion proces\c\ in he'ivq ion-dtoii i C O -

I i \ i o n \ at cnergie\ betaeen a leu megaelectron \o l t \ and 5eLeral hundred gigdelcctronvolt\ He loined the Solid Stcite Electronic\ Laborator) in

1986. where he developed a combined proces\ and device model tor GaA\ MESFET technolog) Hi\ re\earch ha \ tocu\cd o n ion-implotat ion i n t o GaAs. material5 and di\lOcation eftcct\ on MFS- FET'5. and the application of special proces\ing technique\ to m~i'iiriiiic

the performance and unitorinit) of GdAs MESFET'\ I n 1988. he t o r w d the Gatema) Modeling Corporation to di\tribute and \upport the GATES Softhare to the GaA\ IC dnd MMIC industriec

Dr Anholt I \ rl Fellou in the American Ph) Sical Societ)

* Thoma\ \?. Sigmon (S 68-M 69-SM 80) re c e i ~ e d the B Sc degree in engineering p h \ \ i i \ trom Texds Technological College. Lubbock i n

1962 and the M Sc and Ph D degree\ i n electri cal engineering froin Stanford UniLersit) in 1964 and 1970. respectiLely His Ph D dis\enation concerned the measurement of proton radiation damage and free carrier diftusi\itie\ in \iIicon by use of electron-beam-semiconductor interaction techniques

In the winnier ot 1969. he became a Re5earch Associate at Stanford Univenity in the Solid State Laboratory I n February 1970 he became an employee of Hewlett-Packdrd Laboratories \shere he was instrunienta: in the eFtabli5hment of one of the hrst indujtrial ion ini-

plantation facilities in the Santd Clara Valle) In the spring ot 1975 and 1976, he ua5 Guest Lecturer at the Calitornia Institute ot Technolog) Pasadend, where he taught a c o u n e on ion irnplantdtion in semiconductors In December 1976, he p i n e d the staff of the Electrical dnd Computer En- gineering Department Oregon Stdte Univer\ity as an A\\ociate Piolc \wr In June. 1978 he became a Senior Revearch A s w c i a t e in the Stdntord Elec- tronic\ Ldboratorie\ H here he ud\ engaged in a program dpplying x i \ a n i c d malytical technique\ in the study o t material5 and proce\se\ of intere\t tor high \peed \erniconductor device and circuit\ Iabrication Since Septeniher 198-3. he ha\ been a Prote\ror of Electrical Engineering Re\earch L n

gaged in tundainental studit\ ot electronic iiidteridl\ A priincir\ died 0 1 rejc'irch i n thL la\t tu\ \car \ has been the modeling ( i t the etteit 0 1 \lib \tr,ite m d proems detect\ in GdA\ o n MESFET de\ i cc p'iraineter\