I/O PADS In, Out, InOut, Gnd, Vdd, Source follower.
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Transcript of I/O PADS In, Out, InOut, Gnd, Vdd, Source follower.
I/O PADSI/O PADS
In, Out , InOut , In, Out , InOut , Gnd , Vdd,Gnd , Vdd,
Source followerSource follower
Bidirectional Pad -Bidirectional Pad -Digital Component.Digital Component.
•Operates as Pad_in or Pad_out:
•EO high => pad out.
•EO low => pad in.
pad
dataInUnBuff
dataOut
EO
DataIn
DataInB PadBidirHE_SCMOS
Pad LayoutPad Layout
DataIn OE DataOu
tDataInUnBufDataInBu
f
Pad In DC AnalysisPad In DC Analysis
DataInB, after one inverter, has less gain than dataIn
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
vpad (V)
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vol
tage
(V
)
v(dataInB)v(dataIn)v(pad)
simIn
Max frequency 100MhzMax frequency 100Mhz
•Dx = 4.11nsec (>80%*5=4nsec)
•Cursers mark position where output exceed 80% of max input value
0 1 2 3 4 5 6 7 8 9 10 11
Time (ns)
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vol
tage
(V
)
v(dataInB)
3.98
v(dataIn)
122.11m
v(Pad)
0.00
x1= x2= dx=6.05n 10.16n 4.11nsimIn
•VinBar
•Vin
•Vpad
Pad out Dc AnalysisPad out Dc Analysis
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
vdataout (V)
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vol
tage
(V
)
v(pad)v(dataout)
simOut
DataOut
Pad
Data
InB DataIn
Data
InUn
Buf
OE
OE
OEB
OEB
R=10
0
T0L=2u
W=22uT0L=2u
W=22uT0L=2u
W=22uT0L=2u
W=22u
T0L=2u
W=22u
T0L=2u
W=22u
BONDING
PAD
T0L=2u
W=22uT0L=2u
W=22uT0L=2u
W=22uT0L=2u
W=22u
T0L=2u
W=22u
T0L=2u
W=22u
•Response similar to dataIn.
•Explanation: It has two levels of amplifying, as the dataIn node.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
vpad (V)
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vol
tage
(V
)
v(dataInB)v(dataIn)v(pad)
simIn
0 5 10 15 20 25 30 35 40
Time (ns)
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vol
tage
(V
)
v(Pad)4.10
v(dataout)0.00
x1= x2= dx=4.81n 18.87n 14.06nsimOut
Max frequency 30Mhz Max frequency 30Mhz with 10pF capacitor as with 10pF capacitor as
loadload•Vpad
•DataOut
Dx = 14.06nsec (> 80%*17=13.6nsec)Cursors mark position where output exceed 80% of max input value
SfSf with no ideal current with no ideal current sourcesource
•Function: Pad follows Signal, with DC offset.
SFSF LayoutLayout
Signal
Vdd
Vss
SF behavior (with the pmos SF behavior (with the pmos as current source) as current source)
•Current source values -190 to -150 uA
•0<Vin<4 volt, the SF follow the input with 0.85 V offset.
3.5V
4 V
0 .0 0 .5 1 .0 1 .5 2 .0 2 .5 3 .0 3 .5 4 .0 4 .5 5 .0
vs (V)
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
3 .0
3 .5
4 .0
4 .5
5 .0
Volta
ge (V
)
v (sig n al)
v (Pad )
simSF_no_ideal_current
0 .0 0 .5 1 .0 1 .5 2 .0 2 .5 3 .0 3 .5 4 .0 4 .5 5 .0
vs (V)
-1 5 0
-1 0 0
-5 0
-0
Curre
nt (u
A)
i1 (M1 )
i1 (M2 )
i1 (M0 )
simSF_no_ideal_current
Let’s have a closer look
Vpad – Vsignal = 0.85 constant when 0 < Vsignal <= 4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
vs (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Vol
tage
(V
)
v(signal)
v(Pad)
c-b
simSF_no_ideal_current
Slew Rate of the SFSlew Rate of the SF
0.0 0.5 1.0 1.5 2.0
Time (us)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Vol
tage
(V
)
v(Signal)
3.92
v(pad)
4.72
c-b
802.11m
x1= x2= dx=670.33n 1.22u 546.41nsimSF_no_ideal_current_slewRate_good
•Vsignal
•Vpad
•Vpad-Vsignal
Vsignal = ramp from 0 to 5v in 1usec
The SF still follow the step in the range of 0<VSignal<4volt
Pad I/O With ESDPad I/O With ESD
•Two diodes are placed to protect the chip, and are normally at reverse charge.
•When signal exceeds 5+Vb volts, then D2 is forward biased and discharges the excess voltage.
•When signal is below –Vb, then a similar discharging process occurs through D1.
D2
D1
PadIOEsd LayoutPadIOEsd Layout
Diode 1 D1 in schematic
Diode 2 D2 in scehematicsignal
Modeling the PadModeling the Pad
The modeling was The modeling was done by attaching a done by attaching a capacitor, and a capacitor, and a resistor, to the pad. resistor, to the pad. They reperesent They reperesent the capacitance the capacitance and resistance of and resistance of three main models: three main models: Human, machine, Human, machine, and package.and package.
SIGNALSIGNAL
vinit
Gnd
V=5.0
R=1.5K
BONDING
PAD
Dpdiff
Dndiff
C=100pF
To run simulation, an initial voltage was To run simulation, an initial voltage was initialized on the model.initialized on the model.
Human model.Human model.
R=1.5kΩ, C=100pF,Initial Voltage = 2kV
0 50 100 150 200 250 300 350 400 450 500
Time (ns)
0.5
1.0
1.5
2.0 V
olta
ge (
kV)
v (v in it)
simPadWithESD_human_modelnew
0 50 100 150 200 250 300 350 400 450 500
Time (ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Cur
rent
(A
)
i1 (R4 )
simPadWithESD_human_modelnew
Machine Model.Machine Model.
R=25Ω, C=200pF,Initial Voltage = 200V
0 5 10 15 20 25 30 35 40 45 50
Time (ns)
0
50
100
150
200
Vol
tage
(V
)
v (v in it)
simPadWithESD_human_modelnew
0 5 10 15 20 25 30 35 40 45 50
Time (ns)
0
1
2
3
4
5
6
7
8
Cur
rent
(A
)
i1 (R4 )
simPadWithESD_human_modelnew
Package ModelPackage Model
R=1Ω, C=1.5pF,Initial Voltage = 2kV
0 10 20 30 40 50 60 70 80 90 100
Time (ps)
0.0
0.5
1.0
1.5
2.0
Vol
tage
(kV
)v (v in it)
simPadWithESD_human_modelnew
0 10 20 30 40 50 60 70 80 90 100
Time (ps)
0.0
0.5
1.0
1.5
2.0
Cur
rent
(kA
)
i1 (R4 )
simPadWithESD_human_modelnew