INVITED PAPER GrapheneGrowthand...

INV ITEDP A P E R

Graphene Growth andDevice IntegrationThis paper describes one of the emerging methods for growing grapheneVthe

chemical vapor deposition methodVwhich is based on a catalytic reaction between

a carbon precursor and a metal substrate such as Ni, Cu, and Ru, to name a few.

By Luigi Colombo, Fellow IEEE, Robert M. Wallace, Fellow IEEE, and Rodney S. Ruoff

ABSTRACT | Graphene has been introduced to the electronics

community as a potentially useful material for scaling elec-

tronic devices to meet low-power and high-performance

targets set by the semiconductor industry international road-

map, radio-frequency (RF) devices, and many more applica-

tions. Growth and integration of graphene for any device is

challenging and will require significant effort and innovation to

address the many issues associated with integrating the

monolayer, chemically inert surface with metals and dielec-

trics. In this paper, we review the growth and integration of

graphene for simple field-effect transistors and present

physical and electrical data on the integrated graphene with

metals and dielectrics.

KEYWORDS | Chemical vapor deposition (CVD); electrochemical

transfer; graphene; mobility; Raman spectroscopy; X-ray

photoelectron spectroscopy

I . INTRODUCTION

Over the past seven years or so there has been a lot of

excitement in using graphene for many electronic

applications among others [3]–[6]. Researchers have

looked to graphene as a material with which to fabricate

devices in order to exceed the performance characteristics

of current device applications as well as developing newdevices, especially for flexible electronics, transparent

electrodes for displays and touch screens, photonic

applications, energy generation, and batteries [3], [12],

[13]. The first graphene films were only a few tens of

micrometers on the side and so the principal first issue in

making graphene devices a reality is the development of a

graphene of sufficient quality and size to meet the basic

physical and electronic properties. Since the isolation ofgraphene from natural graphite, a number of techniques

and processes have been studied and are in development to

form graphene materials for a variety of applications; an

extensive and complete review of these processes has

recently been summarized by Bonaccorso et al. [22] and a

concise history of graphene is presented by Dreyer et al.[23]. It is still too early to select the final graphene growth

process for high-performance electronic devices sincenone of the processes meets all of the basic requirements.

Today, there are a few sources of high-quality graphene

films: 1) exfoliated graphene from natural graphite or

various other sources of graphite [24]; 2) graphene films

on SiC single crystals formed by the evaporation of silicon

from either the carbon- or silicon-rich surfaces of SiC [25];

and 3) graphene grown on metal substrates by chemical

vapor deposition (CVD) [11], [26]–[29]. The latter twographene growth techniques have emerged as having the

highest potential for high-performance electronic applica-

tions. There are other sources of ‘‘graphene,’’ for example,

reduced graphene oxide or growth on various other metal

surfaces. However, these are either discontinuous,

‘‘doped’’ with oxygen, or multilayered, as in the case of

growth on metals with high carbon solubility, but these

may be suited for applications having less stringentrequirements [23], [30], [31].

Each of the graphene sources has its advantages and

disadvantages: Graphene exfoliated from natural graphite

Manuscript received June 4, 2012; revised April 1, 2013; accepted April 17, 2013. Date

of publication May 24, 2013; date of current version June 14, 2013. This work was

supported in part by the Nanoelectronic Research Initiative and the Southwest

Academy of Nanoelectronics (SWAN–NRI) program. The work of R. M. Wallace was

also supported by an IBM Faculty award. The work of R. S. Ruoff was also

supported by the W. M. Keck Foundation, the National Science Foundation,

and the U.S. Office of Naval Research.

L. Colombo is with Texas Instruments Incorporated, Dallas, TX 75243 USA

(e-mail: [email protected]).

R. M. Wallace is with the University of Texas at Dallas, Richardson, TX 75080 USA


R. S. Ruoff is with the University of Texas at Austin, Austin, TX 78712-0292 USA


Digital Object Identifier: 10.1109/JPROC.2013.2260114

1536 Proceedings of the IEEE | Vol. 101, No. 7, July 2013 0018-9219/$31.00 �2013 IEEE

is of very high quality, as established by carrier transportproperties, but the area of these films (flakes) is limited to

hundreds of micrometers squared and is thus not scalable

to meet high-volume manufacturing (HVM) requirements.

Multilayer graphene grown on SiC single crystals has been

shown to have excellent transport properties [32]–[34].

Further, these films have the advantage of having

exceptional surface flatness, and it is for this reason that

this material is preferred by many surface scientists tostudy the basic physical properties of graphene. However,

in order to satisfy the requirements of many electronic

applications, from nanoelectronics to flexible electronics

and transparent conductive electrodes, it is necessary to

form large individual single layers of graphene. At this

time, exfoliation of the full graphene films from SiC

substrates has not been achieved yet, and even if it could

be achieved, as Hashimoto et al. suggest [35], it might beimpractical for many applications because of the SiC

substrate size limitations and, to a lesser extent, cost. The

introduction of 450-mm silicon integrated circuit devel-

opment and production in the next decade or so will make

the use of SiC as a source of graphene even more difficult

unless SiC graphene can be grown directly on these very

large Si wafers.

The most challenging aspect of the use of graphene forelectronic devices is the absence of a bandgap. It is well

known that graphene develops a bandgap as its width

narrows [36], and it would thus be desirable to be able to

grow graphene nanoribbons (GNRs) in place. There are

several reports on the chemical synthesis of atomically

precise GNRs [37]–[40], but there are no reports, to our

knowledge, of GNR deterministic placement. This is a key

research area that requires much more attention.Traditionally, processes such as CVD and atomic layer

deposition (ALD) have been a preferred method of film

growth/deposition for many types of materials, and it

would be desirable if such growth techniques could be

used for graphene. There have been several recent

attempts at the growth of graphene on Ni by CVD, but

the films were mostly multilayers with only small patches

of monolayer graphite [41], [42]. Recently, bilayergraphene synthesis at the underlying Ni/SiO2 interface

has been reported with arbitrary carbon sources to the

exposed Ni surface [43].

Li et al. [11] on the other hand developed a CVD process

of graphene on Cu substrates where one can grow a

monolayer of graphene on arbitrarily large Cu substrates.

This CVD process has now been adopted by many because of

the ease of implementation, and it is simplifying graphenedevice development, in comparison to exfoliated graphene.

The advantage of graphene on Cu by CVD over graphene

on SiC for HVM is that the CVD process is scalable to sizes

limited only by the size of the CVD system. For example,

Bae et al. [12] used the CVD graphene on Cu process to scale

the growth to square meter copper substrates for display and

touch screen applications.

After the introduction of CVD graphene on Cu therehas been a renewed focus in trying to grow large single

graphene layers on Pt, Ni, Co, and Ru among others [21],

[26], [29]. However, because of the higher C solubility in

these metals and difficulty in etching for some of them, the

processes are not yet commonplace, even though there are

definite thermal stability advantages in comparison to Cu.

The quality of graphene grown by CVD, as determined by

transport measurements, is now nearly equivalent to thatof graphene exfoliated from natural graphite on both SiO2

[44] substrates as well as on hexagonal boron nitride

(hBN) [45]. The availability of large-area graphene grown

on Cu affords the ability to form multilevel stacked 3-D

devices that cannot be easily fabricated using traditional

semiconductor materials with a low thermal budget. This

is all due to the ambipolar nature of graphene and the

ability to grow and transfer to any substrate.In order to take full advantage of graphene grown on

any electrically conductive substrate, it is critical to

develop a transfer process as well as the subsequent

cleaning and integration processes to ensure minimum

graphene degradation so as to take advantage of the as-

grown material properties. Alternative growth methods on

nonconductive substrates are being explored [43], [46],

[47] and may offer the prospect of high-quality materialwithout the need for transfer methods.

Fabrication of electronic devices will require the

development of low defect density, highly ordered large-

area graphene films, thin dielectric deposition processes

that do not disturb the band structure of graphene, to

select and develop contact materials and processes that

provide low contact resistance, and to develop associated

integration processes such as etching and surface cleaning.While thin dielectric deposition on Si is well developed

and understood, growth of scaled dielectrics on clean

graphene is facing some challenges. For example, because

clean graphene is chemically inert, uniformly thin di-

electrics, at the nanometer scale, have been difficult to

deposit. The chemical inertness of the graphene surface

requires some functionalizationVeither intentional or

unintentional (i.e., contamination). Growth of uniformlydeposited high-k dielectrics on hydrogen terminated Si

met a similar problem, and fortunately a thin oxide and/or

an O–H terminated surface were found to fix the problem.

Unfortunately graphene does not have a natural oxide and

so we have to look for different solutions. In addition, low-

resistance metal contacts, necessary for operation of high-

performance devices, have also shown to be challenging,

and so many researchers are dedicating significantresources to solve and understand this problem.

An additional significant complication that faces

graphene is that it does not have a bandgap, thus leading

to devices that do not turn off. It has been found that as the

width of graphene is decreased below a certain value the

confined carriers give rise to opening of a bandgap [36],

[48]. Bernal stacked bilayers of graphene have also been

Colombo et al. : Graphene Growth and Device Integration

Vol. 101, No. 7, July 2013 | Proceedings of the IEEE 1537

found to show a bandgap under a transverse electric field[49], [50]. Other than developing non-field-effect-transistor

(FET)-based devices, there are a number of groups trying to

introduce a bandgap in graphene to increase the performance

of graphene FETs [51]–[59].

In this paper, we will review the state-of-the-art

graphene growth and electronic device integration devel-

opment. It is not the intent of this paper, however, to

perform an exhaustive review of GNRs and bilayer FETdevices and related issues. Rather, we seek to provide the

reader with an introduction to graphene synthesis from an

electronics material integration perspective, as this is the

key step to HVM.

II . GRAPHENE METROLOGY ANDCHARACTERIZATION

Several techniques have been used in the study of

graphene and the associated integration issues, and so a

few words on these techniques are appropriate. The reader

will find numerous results in the graphene research

literature employing these techniques, many of which

provide the complementary information needed to enable

the integration of graphene and other materials required

for device fabrication. Examples of such characterizationtechniques are presented in what follows, but since a

detailed discussion is beyond the scope of this review, a

brief survey of these methods is offered here, with

references offered to the reader for further in-depth

details. Recent reviews of graphene metrology have

become available as well [60]–[62]. In this review we

focus on those techniques that primarily impact integra-

tion for device fabrication.Since ‘‘seeing is believing,’’ a number of microscopy

techniques have been employed in graphene research.

Optical microscopy is a first choice in this regard, where a

number of optical methods to enhance the image contrast

can be employed to get a sense of the graphene

macroscopic quality. The placement of exfoliated graphene

on a suitably thick SiO2 layer to enable contrast through

interference is now well known and convenient [63], [64].It is also noted that recent work has extended the

application of the spectroscopic ellipsometry technique

to graphene, where the phase change of the incident and

reflected light is used [65].

Of course, higher resolution studies require alternative

probes such as electron beams, and both scanning electron

microscopy (SEM), and high-resolution transmission elec-

tron microscopy techniques are used [66]. Recent studieshave employed powerful aberration-corrected TEMs for

superior resolution [67]. In this case, care must be exercised

in controlling the beam power so as to avoid damaging

graphene. Alternatively, such beams can be used to etch

graphene for device fabrication. Low-energy electron

microscopy [68] has also been employed to observe the

growth process of graphene in a number of studies [69]–[71].

A number of scanning probe microscopy techniqueshave been applied to graphene metrology, including

scanning tunneling and atomic force microscopy. The

former has revealed atomic resolution details of graphene

growth [72] and impurity effects [73], while the latter is

typically used for high-resolution profilometry, establish-

ing that single- or few-layer graphene growth is present,

for example [74].

Raman spectroscopy, widely employed for grapheneresearch due to the sensitivity to the bonding structure of

carbon allotropes [75], is used to establish the level of

perfection of sp2 bonding in a graphene sheet [76]. This

nondestructive technique typically uses coherent light that

results in inelastic scattering leading to potentially

resonant interactions that enable the study of electronic

and vibrational properties of molecules and crystals [77].

The technique can use a focused analysis spot and enablethe mapping of �50 � 50 �m2 regions in typical

applications.

Finally, X-ray photoelectron spectroscopy (XPS) has

also been used in the characterization of graphene and

graphite. The technique relies on the photoelectric effect

[78], where electrons are generated through the illumina-

tion of the sample by (typically) soft (�1.4 keV) X-rays,

often with a monochromatic source for superior resolu-tion. As a result, the energy of the generated electrons

limits their origin to less than �10 nm of the surface and,

as a result, the technique is quite surface sensitive. The

energy spectrum of the electrons is analyzed, and is

sensitive to the local carbon bonding environment [79].

The C1s lineshape for graphitic materials is complex, and

requires careful analysis to establish the presence of

detectable impurities (for example, C–O) on the surfacecompared to more complicated relaxation phenomenon

associated with the photoelectron generation [80], [81].

The analytical spot size is typically on the order of

squared millimeters and thus requires relatively large

samples.

III . GRAPHENE GROWTH

Graphite growth on metals has been observed by many

researchers, especially by the catalysis community over at

least the past 50 years [82]. Karu and Beer [83] reported

on the pyrolitic growth of many layers of graphene in 1966,

where they exposed the surface of nickel to methane,

dissociating it, diffusing the resulting carbon into the

nickel, and then precipitating multilayers of graphene on

the nickel surface upon cooling. Blakely and students inthe 1970s described the details of the C precipitation

process from metals (Ni, Pt, Pd, Co) as deduced by surface

analytical techniques and stated that monolayer graphite

was the first material to segregate to the surface of the

metal surface before full graphite precipitation upon

cooling to room temperature [84]–[88]. This pioneering

work provided the basic ideas on how to grow multilayer


1538 Proceedings of the IEEE | Vol. 101, No. 7, July 2013

graphene on metals and was recently reviewed byWintterlin and Bocquet [89].

The number of layers of graphene on metals is to first

order dependent upon the solubility of C in the metal and

the cooling rate. A higher solubility at a given temperature

results in a higher number of graphene layers precipitating

at the surface of the metal. Transition metal substrate

selection for graphene growth depends principally on the

solubility of C in the metal and the propensity for themetal–C solution not to form a metal carbide compound.

Before selecting a metal, one must thus first establish that

there are no stable or metastable metal carbide phases that

form during any of the process steps. Second, it is

important to select a material that has a low C solubility in

order to provide sufficient control of the number of

graphene layers. Fortunately, there is already an estab-

lished compendium of equilibrium phase diagrams avail-able online through the American Society of Metals of the

metal–carbon systems. The Co–C, Ni–C, Cu–C, Pd–C,

Ru–C, Rh–C, Pd–Cu, Ag–C, Ir–C, Pt–C, Au–C, Ge–C, and

perhaps others, are a few binary systems where a stable

carbide phase does not seem to form under equilibrium

conditions; however, one must also pay attention to

metastable phases as in the case of Ni2C [26], [90].

Fig. 1(a) and (b) shows the phase diagram of Ni–C andCu–C, respectively, where it is very clear for the Ni–C

system that, at temperatures less than the melting point

and the eutectic temperature, the solubility of C is as highas a few percent and it is still soluble at a temperature of

about 500 �C. On the other hand, the Cu–C system is a

particularly interesting system because the solubility is

extremely low. The Ir–C system is an equally attractive

system because of the low carbon solubility at

temperatures below 1000 �C as well as a high catalytic

activity.

Carbon also has a low reactivity and bond strength withCu [90], which makes it easy to remove the graphene

through chemical etching of the Cu substrate. The removal

has been accomplished by chemical etching of the metal by

several typical Cu etching chemistries such as aqueous

FeCl3 solutions, ammonium persulfate, or nitric acid, and

more recently by electrochemical etching to dissociate the

graphene from the substrate. The transfer process will be

reviewed in greater detail in Section IV-A.As noted earlier, it would certainly be desirable if

graphene could be grown directly on a dielectric surface,

without a metal intermediary. Growth of graphene has

been reported on hBN, magnesium oxide, cobalt oxide

(Co3O4) and perhaps others [91]–[94]. However, at this

time, there are no reports of high-quality, large-area

continuous single-layer graphene growth on any dielectric

surface.In the case of metals, there are other criteria for

substrate selection other than C solubility, such as

substrate etchability, availability or cost, purity, grain

size, orientation control, etc. Therefore, given these basic

requirements, it is desirable to have a metal–carbon

system that satisfies the aforementioned characteristics.

Unfortunately, at this time, there is no single metal that

fulfills all of the requirements but the metals being usedare providing a sufficient quantity and quality of graphene

to enable device development.

Currently, the research community has basically

overcome the challenge of the growth of monolayer

graphene by using CVD. However, because graphene does

not have a bandgap, it would be desirable for simple FETs

to have a channel material with a bandgap. Two

approaches have been used to introduce a bandgap ingraphene: one is to form GNRs, which have been shown to

have bandgaps and the second is to form bilayer graphene.

GNRs have been found to show width-dependent ‘‘band-

gap,’’ while the bilayers show a bandgap when a trans-

verse electric field is applied. The formation of GNRs

at the few nanometer dimension has the added challenge

of controlling the graphene edge structure and dimen-

sions or line edge roughness (LER) as it is commonlyreferred to for Si transistors [95]–[97]. Growth of bilayer

graphene on the other hand has been demonstrated on

both metals and dielectrics, but it is difficult to control

the number of layers at this time [43], [98], [99]. Some

advantages and disadvantages of the various graphene

preparation and growth techniques are summarized in

Table 1.Fig. 1. (a) Ni–C phase diagram. (b) Cu–C phase diagram.

(Adapted from [1].)



A. Chemical Vapor Deposition

1) Monolayer Graphene: CVD is one of the most

extensively used processes in the semiconductor industry

because of its flexibility, composition control, conform-ality, efficient material usage, etc. It would be advanta-

geous if we could use this process technology to grow

graphene films. As with most materials, thickness and

composition control are critical and in the case of

graphene, as a single element material, composition

control is not an issue, however thickness control,

impurities, and surface flatness are extremely critical.

Graphene grown on Cu was found to grow by a surfacemediated process and can now be grown routinely and can

be transferred to any substrate for further evaluation and

use, while still maintaining the overall properties of the as-

grown film [2]. Fig. 2(a) and (b) shows SEM images of

graphene on Cu and graphene transferred to SiO2,

respectively, showing the uniform nature of the film

across a large area [11]. Fig. 2(c) further shows the scaling

of graphene growth on Cu to very large areas. Since the

graphite growth process on Ni takes place by a precipita-

tion process, even for very thin Ni films, graphene is only

observed in small regions [41], small grains, where perhaps

the grains are depleted of the carbon through heavyprecipitation at grain boundaries. Recently, however,

Addou et al. [26] have reported on the growth of graphene

on Ni(111) at a relatively low temperature range,�500 �C–

650 �C. These results are encouraging, but even at such

low temperatures, it is difficult to completely prevent

precipitation upon cooling. Additionally, another set of

very interesting results of graphene growth on single-

crystal Co [29] and Ru [112] on sapphire has also beenrecently reported, suggesting that the elimination of grain

boundaries leads to improved control of graphene growth.

These results are important since they demonstrate the

ability to grow high-quality graphene and perhaps even

hetero-epitaxial graphene on nearly lattice matched

substrates such as Ni and Co. However, there could be

some technological limitations such as the unavailability

Table 1 Graphene Film Growth Techniques Comparison



of large-area sapphire single crystals. The results of

graphene growth on single-crystal Co [29] and Ru [112]

on sapphire have also been recently reported, suggesting

that the elimination of grain boundaries leads to improved

control of graphene growth. These results are importantsince they demonstrate the ability to grow high-quality

graphene and perhaps even hetero-epitaxial graphene on

nearly lattice matched substrates such as Ni and Co.

However, there could be some technological limitations

such as the unavailability of large-area sapphire single

crystals. These results could have a positive impact on the

fabrication of high-quality electronic devices on graphene if

the resulting graphene on lattice matched substrates has afinal lower defect density. Growth of large-area graphene is

critically important, not only for nanoelectronic devices

but even more so for plastic substrate electronics and

transparent conductive electrodes, as well as energy

generation applications. The principal difference between

these applications is that transparent conductive elec-

trodes may tolerate defects in the graphene films such as

grain boundaries that other devices may not. Higher per-formance thin-film electronic devices on flexible sub-

strates are promising since graphene would provide much

higher mobilities than other materials under evaluation

[113]–[115].

There have also been reports of CVD graphene

synthesis using patterned nucleation sites such as Ni

metal dots [116] or even patterned graphene seed regions

[117]. Such methods result in a high density of hexagonalgraphene regions upon further exposure to the CVD

process.

Recently, there have been some advances in the growth

of large single-crystal graphene with grain sizes up to

0.5 mm on Cu substrates [118], as shown in Fig. 3(a), and

up to 1 mm on Pt substrates [21], as shown in Fig. 3(b).

Fig. 3(a) shows a single crystal of graphene grown on Cu

where the average growth rate is about 3 �m/min, and it isof high quality as determined by Raman spectroscopy as

well as transport properties [118]. Recently, Petrone et al.[45] also reported on the mobility of CVD large-area

domain, probably single crystal, graphene grown by the

same process as that reported by Li et al. [118]. They found

the mobility to be as high as 2.5 � 104 cm2/V�s on SiO2

and 4.5 � 104 cm2/V�s on hBN for carrier-density-

independent mobility and a residual carrier concentrationat the Dirac point of much less than 1 � 1011 cm�2

indicative of a good transfer process. These films show

high mobility despite the fact that the growth front is

dendritic, i.e., ‘‘rough.’’ The growth rate of the films

grown on Pt is also about the same as the films reported

by Li et al. [118] on Cu. On the other hand, the graphene

grown on Pt and removed from the substrate by an

electrochemical process clearly shows a nearly flatgrowth front, as indicated by the nearly hexagonal shape,

Fig. 2. (a) SEM of graphene on copper and (b) optical image of

graphene transferred onto a quartz substrate. Adopted from [11].

(c) Large-area graphene grown by CVD on Cu and transferred to

polymethylmethacrylate (PMMA) by a roll-to-roll process.

Adapted from [12].

Fig. 3. Single crystals of graphene grown by CVD using methane on

polycrystalline (a) Cu (adopted from [9]) and on (b) Pt (adopted from

[21]) substrates.



120� corners of the crystal. With this faceted graphenesingle crystal, one would expect exceptional transport

properties, but at this time, while the density-independent

mobility is very good, > 7.1 � 103 cm2/V�s with a residual

carrier concentration of about 2 � 1011 cm�2, at the Dirac

point, it is lower than the best reported for graphene

grown on Cu or exfoliated graphene. However, this lo-

wer mobility could be a result of unoptimized device

processing.

2) Bilayer Graphene: Bilayer graphene has been observed

during the growth of CVD graphene layers in most reports.

The density of the bilayer regions has been decreasing as

the CVD process is improving. The principal reason for the

successful growth of monolayer graphene is the low C

solubility in the Cu substrate and the absence of catalytic

activity of graphene. It is this very reason that makes itdifficult to grow uniform controlled multilayer graphene

layers. The need for demonstration of bigraphene devices

has spurred many to investigate the growth of bilayer

graphene by CVD. There are a few reports on the

intentional growth of large-area Bernal stacked bilayer

graphene [98], [99]. The results seem promising and, at

this time, there are potentially two mechanisms for

growing these films: 1) growth of the second layer by theuse of graphene fragments formed on a source metal

surface (Cu in [99]); and 2) growth under the first

growing graphene films, as reported by Nie et al. [119].

There are also cases where the films are not uniformly

Bernal stacked, perhaps due to the presence of multiple

grains and thus poor registration of the first and second

films.

Progress is being made deliberately in the basicunderstanding of bilayer graphene growth [43], [119],

[120]. Sun et al. [120] studied the structure of graphene

and multilayer graphene on Ni by in situ low-energy

electron microscopy (LEEM) and found that single layers

of graphene are strongly bound to the Ni substrate and

the �-band structure characteristic of graphene is absent,

while it is present for bilayer graphene. This could be an

issue in the growth of either monolayers of graphene orbilayers; however, Peng et al. [43] using a similar process

find that the bilayers are well behaved according to

Raman spectroscopy. At this point though there are no

reports yet on the electrical behavior of these films.

B. Graphene NanoribbonsGNRs have been extensively studied with the intent of

introducing a bandgap in graphene as well as trying toevaluate the limits of graphene physical scaling. The first

reports have been on chemically derived GNRs from

natural graphite with widths below 10 nm. These films

showed semiconducting behavior with carrier mobilities

below 200 cm2/Vs. The need to form graphene with a

bandgap has spurred other groups to form GNRs by direct

chemical methods, a bottom–up approach and surface

mediated synthesis [40], [108], [121] as well as longitudi-nal chemical unzipping of carbon nanotubes (CNTs) [110].

GNRs have also been formed by a templating growth

process on SiC [101]. This would certainly be an elegant

approach to address the many issues of forming GNRs,

however, at this time, this can only be achieved directly on

SiC crystals and this can be an intermediate approach for

device evaluation. The continued development of GNR for

any device will be critical to the scaling of graphene-baseddevices regardless of whether a large bandgap is needed. In

addition, as already mentioned above, graphene scaling

will need precise LER control in order to yield uniform

device performance across a wafer [107]. It is unlikely that

traditional etching will meet the required uniform GNRs,

thus the development of deterministic atomically precise

formation approaches may be necessary. Graphene and

GNRs are being considered for interconnect applicationsas well but the effort for its implementation has been fairly

low in comparison to other applications [122], [123].

C. CVD Graphene CharacterizationRaman spectroscopy is one of the most effective

characterization tools for graphene. Ferrari et al. [124]

and Casiraghi et al. [125] have performed extensive studies

to establish the relationship between Raman spectralcharacteristics and the number of graphite layers and

transport properties. There are three principal Raman

spectral characteristics that are used to evaluate the

presence and quality of graphene: the D-band (peak) at

�1350 cm�1, the G-band at�1590 cm�1, and the 2-D-band

at �2700 cm�1. The D-peak is representative of defects in

graphene or graphite, while the G and 2-D-peaks, indicative

of the sp2 bonding, are very sensitive to the doping levels inthe films. Additionally, the 2-D-peak is made up of two

distinct peaks 2-D1 and 2-D2 in natural graphite, and as the

graphite tends toward a monolayer, the higher wave number

peak 2-D2 decreases to merge into a sharp 2-D-peak at the

lower wave number, and it is this signature that enables

one to distinguish graphene from multilayer graphene

[124]–[126].

Fig. 4 shows the Raman spectrum of graphene grownon Cu foils and transferred onto SiO2/Si substrate in

comparison to that of highly oriented pyrolitic graphite

(HOPG). The spectrum clearly shows a narrow 2-D

spectral band indicating that the film is a monolayer of

graphite, and the absence of a significant D-band shows

that the films have a negligible defect density.

The growth of graphene on copper can be controlled by

changing the processing conditions such as substratesurface conditions, temperature, pressure, precursor and

hydrogen partial pressure, and precursor type. At first, a

few bilayer regions in graphene on Cu were reported [11],

presumably as a result of defects on the Cu surface, long

growth times, and higher precursor pressures. The growth

of bilayer regions was studied by Nie et al. [119], and they

showed that the bilayer regions are a result of carbon



diffusion under the first graphene film rather than on top

of the graphene. The bilayer and sometimes trilayer

regions are always small and do not grow even after

extended growth periods suggesting that as the Cu surfaceis covered with graphene, the C source for the bilayer

growth disappears. What distinguishes the growth of

graphene on Cu from growth on other metals is that the

growth process is surface limited; that is, the growth ceases

as the metal surface is covered with graphene.

The 2-D surface-limited growth process of graphene on

Cu was identified using a carbon isotope labeling

technique, as reported by Li et al. [127]. In thisexperiment, the surface of Cu is exposed sequentially to

‘‘normal’’ methane, primarily 12CH4, and then to methane

containing 13C. Because of the mass difference between12C and 13C, the Raman peak positions shift, and this shift

was used to monitor the location of the two carbon

isotopes on the Cu surface. Fig. 5(b) shows the Raman map

of graphene grown on Cu by sequential exposure to 12CH4

and 13CH4 at about 1035 �C and the corresponding Ramanspectra [Fig. 5(a)]; it is clear from the banding, yellow and

black, that graphene is growing by a 2-D, i.e., surface

mediated, process. A similar experiment was performed

using thin-film Ni as the substrate, and it was found that

graphene does not grow by the same process on the Ni as

exhibited by the uniform shift of the G-peak, as shown in

Fig. 5(c) and (d).

IV. MATERIALS INTEGRATION

In order to create graphene-based electronic devices, it is

necessary to integrate graphene with a dielectrics, metalcontacts, and electrodes. Fig. 6 shows a cross section of a

simple four-terminal device with a source and drain, gate

dielectric, top gate electrode, and bottom gate contact or

body contact. In this section, we will review graphene

transfer from metals to dielectrics, dielectric deposition

and chemical analysis on graphene, and the effect of

dielectrics on electronic transport and contact materials.

A. Transfer of CVD GrapheneThe utilization of CVD graphene grown on metals for

device applications currently requires a transfer process

from the metal substrate to a more suitable substrate, a

Fig. 5. (a) Raman spectroscopic map of graphene grown on Cu using

isotopically labeled carbon in methane (12CVstandard graphene and13C). (b) Raman spectroscopic map of graphene grown on Ni using

isotopically labeled carbon in methane (12CVstandard graphene and13C). (Reprinted with permission, �2010 American Chemical Society;

adapted from [8].)

Fig. 6. Schematic diagram of a dual-gated graphene FET structure.

(Reprinted with permission,�2009 American Institute of Physics [14].)

Fig. 4. Raman spectrum of CVD graphene on SiO2 and that of HOPG.



dielectric. Following the original work on device measure-

ments using exfoliated graphene, a majority of the studies

with CVD graphene entail transfer to Si wafers with a SiO2

dielectric layer on the surface. The transfer process,although far from ideal, enables reasonable quality

graphene for device research and development, with the

potential for large-area substrates. In contrast, Si sublima-

tion from SiC renders graphene layers on a wafer surface

outright, and thus does not require a transfer process to

fabricate research devices [128]. In this case, however, the

available wafer area size limits the economics of the

process and, thus, the potential applications, specificallythose requiring integration with Si or those requiring very

large areas such as display applications in an HVM

environment.

The transfer process, first reported by Yu et al. [129],

entails a number of wet chemical processes; these can

include exposure of the graphene/metal substrate to

polymers, solvents, etchants, water rinses, as well as

assorted thermal anneals. From a semiconductor manu-facturing point of view, it is clear that such processes

would be expected to introduce organic contaminants or

defects at some level, and thus a systematic understanding

of the impact of the processes is desirable.

For example, spin-on poly(methyl methacrylate)

(PMMA) [11], [41] or polydimethylsiloxane (PDMS) [129]

have been used as a protective coating over the graphene

permitting the etching and removal of the underlying metalsubstrate used for growth, as shown in Fig. 7(a). At the

conclusion of the metal etching process, a ‘‘raft’’ of PMMA/

graphene remains, which can be essentially ‘‘fished’’ out of

the solution and placed onto a desired substrate, such as a

SiO2/Si wafer. The PMMA is then often dissolved away using

a suitable solvent, such as acetone.

Figs. 8 and 9 show the effect of PMMA residues on

graphene device behavior and the resulting surface charac-teristic as determined by XPS [18]. Fig. 8(a) shows the XPS

spectra of CVD graphene on Cu, followed by Fig. 8(c) after

transfer to a SiO2/Si substrate and PMMA removal using

acetone, and finally the film is annealed under ultrahigh

vacuum [Fig. 8(c)]. It is seen that the typical PMMA solvent

removal process is incomplete, resulting in detectable

residuals in the C1s spectra. The subsequent vacuum anneal

reduces these residuals to levels near the limit of detectionfor XPS, and is consistent with prior scanning tunneling

microscopy (STM) studies using a reducing atmosphere [73]

as well as more recent studies [133]. It is interesting that XPS

data performed on the same films after transfer do not show

any detectable metal; however, while XPS can provide initial

indications on the metal (Cu for example) concentration on

the graphene surface, more sensitive techniques such as

inductively coupled plasma mass spectrometry (ICPMS)will have to be used before such films can be introduced in

a Si line.

Another method of transferring the graphene is to use a

‘‘dry’’ process where the graphene is covered with the usual

polymer, for example, PMMA, but rather than placing the

substrate in the ‘‘wash water’’ and transferring the

graphene/PMMA stack over water, it is removed from on

Fig. 7. Graphene transfer process from the Cu substrate.

(a) Chemical dissolution of the Cu, (adapted from [2].

(b) Electrochemical separation [20] of Cu and graphene.

(Reprinted with permission, �2011 American Chemical Society.)



top of the etchant/water solution using a carrier and then

placed onto the desired substrate after drying [45], [131].

Yet another similar dry process is the use of a roll-to-rollprocess, as described by Bae et al. [12], for very large areas.

Recently, there have also been reports on the transfer of

graphene by an electrochemical process for both Cu [20]

substrates and Pt substrates [21], as shown in Fig. 7(b).

The clear advantage of this process is that the substrate can

be reused many times, and perhaps it may simplify the

handling of the graphene with the transfer polymer from

the solution. This type of process could have significantadvantages since it minimizes metal waste, a potential

environmental problem; further the graphene–polymer

stack can be transferred ‘‘dry’’ to the desired substrate.

There are advantages and disadvantages to any of the

current transfer processes, and it is important to optimize

each one, with particular attention to surface cleaning so

as to render the graphene surface as close to the as-grown

surface as possible.The fabrication of back-gated graphene transistors

(Fig. 9) enables the study of any correlated conductivity

(typically measured under a modest vacuum) and the

extracted mobility behavior. It is seen that the reduction of

such residues impacts the mobility substantially, pointing

to the need for careful control of contaminants introduced

by the transfer process. Further systematic studies havealso been performed at other stages of the transfer process,

including the effect of water exposure and in situ annealing

to remove physisorbed species prior to electrical measure-

ments [15]. Mobility measurements on CVD graphene

comparable to exfoliated graphene on SiO2/Si have been

obtained by controlling these processes, and through the

minimization of extrinsic impurities or defects.

CVD graphene has also been transferred onto alterna-tive dielectrics such as hBN and ideal substrate for

graphene since they are nearly lattice matched to each

other and are both layered materials. The use of exfoliated

hBN as a substrate for exfoliated graphene has resulted in

superior device performance due to several factors,

including chemical inertness and flatness [134], [135]. As

for large-area studies, work on CVD hBN has recently been

reported [136]. Single-layer hBN and multilayer hBN havebeen grown; however, at this time, the electrical

performance of the CVD grown hBN is still inferior to

exfoliated hBN from bulk grown crystals [137]. Table 2

shows a summary of the most common transfer process

used. There is still much work to be performed in

optimizing each of the processes, and process selection

will depend to the particular application.

Fig. 8.XPS C1s spectrum for (a) CVD graphene on Cu, (b) graphene after

transfer to SiO2 and removal of PMMA using acetone, and (c) after

300 �C/3 h ultra high vacuum (UHV) anneal. Curve fits to spectral

components attributed to graphene sp2 C–C bonds (d) and PMMA

residue (e)–(i) are shown. (Reprinted with permission,

�2010 American Institute of Physics [18].)

Fig. 9. (a) Rtotal versus VGS for the as-prepared devices, annealed at

300 �C in UHV, annealed at 300 �C in UHV, plus in situ annealed at 80 �C

and measured at room temperature, compared to the same device

measured at 77 K after 300 �C UHV anneal followed by an 80 �C in situ

anneal. (b) Mobility as a function of the different graphene and gFET

treatments. (Adapted from [15].)



B. Dielectrics on GrapheneOne of the basic properties of graphite, and thus

graphene, is that the surface is inert to surface oxidation

and other reactions at typical process temperatures (less

than about 500 �C) in comparison to other FET materials,

such as Si, Ge, and III–V semiconductors. Although

graphene is quite resistive to oxidation, at the current

typical device processing temperatures, there are somematerials that readily react with the graphene surface

under certain chemical conditions. The resultant disrup-

tion of the sp2 bonding due to such reactions results in

defect sites, which impact transport properties. However,

the oxidation behavior also makes integration of graphene

in a conventional device flow challenging. This section

summarizes the issues and progress on dielectric integra-

tion for graphene FETs.Dielectrics in contact with graphene are required to

enable field-effect control of electron and hole transport

through the graphene layer by means of an electrically

isolated external gate. Typical in many of the earlier

graphene-FET (gFET) devices utilizing exfoliated gra-

phene, a dielectric such as SiO2 was employed to serve as a

‘‘back-gate dielectric’’ in order to probe the transport

properties of graphene transferred to SiO2/Si wafer

substrate [4]. The application of a ‘‘top-gate’’ dielectric

on such structures enables the study of FET saturation

characteristics for high-performance analog applications

such as radio-frequency (RF) circuits [138]. A review of the

recent developments in graphene transistor designs and

their potential utility has been recently published [139].

A number of strategies have been employed to enablethe deposition of dielectrics on graphene, including metal

evaporation and ALD. The challenges of nucleating thin

dielectric films on the surface of graphene have been

recognized for some time, particularly in view of prior

work on CNT surfaces [140].

For high-k dielectrics such as HfO2 or ZrO2, ALD

methods were employed on CNT transistor structures so

that the CNT channel was essentially encased within thehigh-k layer [141]. As the ALD process generally requires

reaction with the available surface bonds for film

nucleation and subsequent growth [142], it was later

shown that defects in the nanotubes can result in such

nucleation sites [140]. Alternative methods for nucleation

sites entailed the concepts of functionalizing the CNT

surface sufficiently to enable subsequent ALD of dielectrics

Table 2 Graphene Transfer Process Comparison



[143], based in part on earlier observations of CNTresistivity changes upon exposure to species such as NH3

and NO2 that were apparently physisorbed to the CNT

surface [144], [145]. Using a combination of NO2 and

trimethyl–aluminum (TMA), a well-known ALD precursor

for Al2O3 deposition, Farmer and Gordon [143] demon-

strated that a thin, uniform Al2O3 dielectric can be formed

on the single-wall CNT surface by ALD.

Without such functionalization of clean graphene,nonuniform film deposition occurs largely at defect sites,

as seen in Fig. 10 for the HOPG surface, which is thought

to be representative of the graphene surface [146]. It can

be seen that the ALD process decorates the step edges of

the surface, while the relatively inert terraces remain free

of detectable deposition under these conditions. The NO2-

functionalization strategy was subsequently adapted for top-

gate Al2O3 dielectric growth on the exfoliated graphenesurface for quantum Hall effect measurements of ambipolar

transport [147]. Later work on gFETs demonstrated,

however, that such NO2 functionalization can degrade

gFET mobility presumably through charge impurity scatter-

ing as well as interface phonons with the Al2O3 [148].

Another challenge for adopting NO2 in standard device pro-

cessing lies in the corrosive properties of the gas in

deposition tools where residual water may be present andsafety considerations due to the strong reactivity. As a result,

alternative functionalization methods are being explored.

A common point-of-use oxidizer, well established in

semiconductor fabrication technology, is ozone, and this has

been recently explored for surface functionalization of

graphene [16], [17], [149]. The effect of an O3 pre-treatment

to the HOPG surface on Al2O3 ALD is shown in Fig. 10(c). In

this work, the HOPG surface was exposed to O3 at 200 �Cresulting in substantial C–O bonding thus rendering the

surface active for subsequent Al2O3 ALD growth with a

TMA/water chemistry. Of course, the formation of detect-

able C–O bonding implies some disruption of the HOPG

surface, and thus damage to a graphene specimen with this

process would clearly be anticipated. Such elevated

temperature etch damage (and chemical doping) has also

been reported upon exposure to O2/Ar mixtures as well as to

ultraviolet light, for example, [150].The O3 process can be optimized for an exfoliated

graphene layer by conducting the O3 pretreatment at room

temperature, followed by an elevated temperature TMA/

water ALD process, as reported by Lee et al. [17] As seen in

Fig. 11(a), the Raman spectra of the 25 �C O3 exposure for

20 s results in no detectable defect band (‘‘D’’� 1350 cm�1),

while the elevated temperature clearly results in etch

damage and thus a detectable ‘‘D’’-band [Fig. 11(b)]. Theresultant Al2O3 film was then grown with a TMA/water

chemistry at 200 �C and incorporated as a top gate on a

dual-gated gFET device using exfoliated graphene. Electri-

cal characterization shows ambipolar behavior with an

extracted mobility [14], [151] as high as 5000 cm2/s [17].

The mechanism associated with functionalization by

O3 on clean graphene has been considered using first-

principles computational methods and in situ electricalcharacterization [152], [153]. It is found that the short time

25 �C O3 exposure is predicted to weakly chemisorb on the

surface, resulting in an epoxide species with submonolayer

surface coverage. This species then serves as a nucleation

site for subsequent ALD dielectric growth. Additionally,

the effect of extrinsic contamination with the O3 process is

also a consideration for film nucleation [154].

Organic species have also been shown to facilitatenucleation for subsequent ALD dielectric film growth, such

as perylene tetracarboxylic acid (PTCA) [155] or perylene-

3,4,9,10-tetracarboxylic dianhydride (PTCDA) [156], but

transport measurements of gFETs using these organic layers

have not yet been reported. Polymer-based nucleation layers

have also been employed and include photoresist materials

such as hydrogen silsesquioxane (HSQ) [157] as well as a

planarization polymer that performs as a low-k dielectricbuffer layer [158], [159]. In the latter case, an extracted

mobility up to 7700 cm2/s was reported for top-gated gFETs

with an HfO2 layer deposited on the buffer layer [159]. The

use of such ‘‘seed’’ layers for functionalization and subse-

quent high-k dielectric deposition has also been proposed to

decouple the surface phonon interaction associated with

Fig. 10. Atomic force microscope images of the HOPG surface after

(a) exfoliation and (b) exposure to an ALD process of TMA and water

at 250 �C, and (c) after exposure to an ALD process and ozone at

200 �C. (Reprinted with permission, �2008 American Institute of

Physics [16].)

Fig. 11. (a) Raman spectrum of a pristine single graphene layer

(bottom) and graphene treated with O3 at 25 �C for 20 s. (b) The same as

(a) except with O3 exposure at 200 �C. (Reprinted with permission,

�2010 American Institute of Physics [17].)



such oxides and the graphene interface, potentially enhanc-ing the resultant mobility.

Given the ability of organic species to result in

nucleation and growth of ALD dielectric films by ALD,

one may also ponder the effects of spurious surface

contamination from, for example, atmospheric exposure.

Such contamination is well documented in the Si

integrated circuit fabrication community, and contains

organic species as well as physisorbed species such aswater [160]. Estimates of the formation of a monolayer on

a typically reactive surface have been less than 30 min

[161]. Enhanced surface contamination from B during

exposure of a surface under clean-room conditions has also

been reported [162]. The concentration of such species on

freshly exfoliated graphene may be anticipated to be

somewhat less than that on active surfaces such as the

native oxides of Si or III–V compounds, but their effect onnucleation in an ALD process cannot be ruled out.

Residues from processing also surely play a role in this

context. The impact of such contamination on ALD high-kdielectric growth has been recently reported [149].

An alternative method to ALD of gate dielectrics on

graphene includes the physical vapor deposition (PVD) of

metals and metal oxides. Early work on high-k gate

dielectric deposition on Si employed this concept [163].Examples include sputtered Zr [164] as well as evaporated

La and Al [165]. and subsequent oxidation to form thin

(�2–5 nm) ZrO2, La2O3, and Al2O3, respectively. In the

context of graphene, Kim et al. [14] utilized this approach

to produce a ‘‘seed layer’’ for subsequent Al2O3 ALD

growth. A 1–2-nm Al metal film was deposited by e-beam

evaporation on exfoliated graphene, followed by exposure

to the clean-room ambient resulting in extensive oxidationof the thin Al layer [166]. This surface was then submitted

to a water/TMA ALD process to produce a 15-nm Al2O3

dielectric film incorporated into a top-gated structure. A

dielectric constant of k ¼ 6:0 was reported for the

resultant Ni/Al2O3/AlOx/graphene gate stack, and an

extracted mobility as high as 8600 cm2/s was reported.

This work was recently extended by comparing Ti and Al as

nucleation layers. The data indicate that the Ti is a moreeffective and uniform metal as an adhesion layer yielding

an improved capacitance scaling for the Al2O3 top-gate

dielectric on exfoliated graphene [167].

Lemme et al. [168], [169] studied the use of an electron-

beam evaporated SiO2 layer (20 nm) as a gate dielectric on an

exfoliated graphene gFET and observed that the mobility is

reduced from �4800 cm2/V�s for electrons and holes to

�700 and 500 cm2/V�s, respectively, after deposition of thetop-gate stack. An interaction of the �-orbitals of the under-

lying graphene with the SiO2 resulting in van der Waals

bonding [170] was proposed as the source of mobility de-

gradation for this gFET. There are limited reports utilizing

such PVD methods to seed ALD on CVD graphene, and

mobilities greater than 4000 cm2/V�s have been extracted

from electrical measurements of Al2O3 top-gated films [11].

There are limited reports on the effect of the depositeddielectrics on the Raman signature. The limited data show

that there are no significant deleterious effects as established

by the absence of the Raman D-band for processes that yield

good electrical data [17], [171].

Scaling of deposited oxides has been extensively

studied with some nucleation–functionalization ap-

proaches better than others as described above, but scaling

down to monolayer levels without pinholes and low gateleakage has been difficult to achieve. The introduction of

hBN [134] and transition metal dichalcogenides (TMD)

[172] as potential dielectrics has changed the landscape of

dielectric scaling approaches and is now attracting a lot of

attention [173], [174]. Graphene, exfoliated and CVD on

Cu, transfer to hBN flakes has yielded excellent carrier

mobilities as a result of lower substrate induced disorder.

Deposition and growth of these materials is now beingextensively investigated because of the promising electri-

cal results using exfoliated films. However, the deposition

of the same materials on metal substrates and on graphene

at the monolayer level has not yielded the same transport

properties, to our knowledge, yet.

While ALD, perhaps in this case atomic layer epitaxy

(ALE), can still be a desired approach for the growth of

these ‘‘new’’ 2-D materials, there are other techniques suchas molecular beam epitaxy that could be equivalently

attractive. The advantage of processes like MBE is that one

could avoid the use of precursors that tend to introduce

unwanted hydrocarbons and perhaps metallic impurities

because of the difficulty in procuring very high purity

precursors, and thus provide purer films. At this time,

there are no reported data on the effect of specific

impurities in gate dielectrics on device performance.

C. Graphene-Dielectric Interface CharacterizationThe characterization of the graphene-dielectric inter-

face is also a topic of intense interest. An important

method in this work is X-ray photoelectron spectroscopy

[175], which enables the detailed understanding of the

interfacial bonding present. Particularly when coupled

with in situ treatments of the graphene surface, one canobtain a fundamental understanding of reaction pathways

during the dielectric growth process. Another important

technique is scanning tunneling microscopy/spectroscopy.

An example of in situ analysis of 1 nm of Al deposited

on HOPG is shown in Fig. 12 [7]. In this work, the effect of

annealing of the exfoliated HOPG sample, prior to Al

metal deposition was conducted, to remove physorbed

species on the surface, such as hydroxyls from (brief)atmospheric exposure. It is seen in Fig. 12(a) that the post-

anneal surface reveals a characteristic C1s line shape for

sp2 carbon, and that the Al2p spectra is consistent with

unoxidized Al on the clean HOPG surface. Upon exposure

to O2 at 200 �C, the aluminum is not completely oxidized,

as seen by the small remnant Al0 metal feature at�72.6 eV.

In contrast, if the exfoliated HOPG surface is not annealed



prior to deposition, the surface has remnant oxygen-related

physisorbed species (likely hydroxyls), and the deposited Al

reacts with these species to consume them forming AlOx at

the interface [Fig. 12(c)]. It is clear that subsequent

oxidation then results in complete oxidation of thedeposited Al. In contrast to the behavior of Al, a 1-nm Hf

layer deposited at room temperature can result in Hf–C

formation on HOPG, as seen in Fig. 13. Fig. 13(a) shows the

XPS spectra of Hf/graphene after Hf deposition; where a

C1s feature at �282 eV is clearly evident and indicative of

Hf–C bonding. Perhaps the formation of Hf–C reaction is

aided by the presence of adsorbates on the graphite surface;

graphite–titanium reactions have been reported afterannealing at high temperatures, and at T G 600 K

interfacial reactions have been observed. It is therefore

not surprising that Hf also reacts with graphite at room

temperature. In the case of Al, Al4C3 can also be formed,

but it readily reacts with water and is thus unstable [176]. In

the presence of oxygen as was the case for the Ti, Hf, and Al

interfacial layers reported by Fallahazad et al. [167], [177]

and Kim et al. [178], the graphene seems to be very stableagainst carburization. Such bonding would be anticipated

to be catastrophic for a monolayer graphene sheet. A

substantial amount of oxidized Hf is also noted on this

surface from the companion O1s and Hf4f spectra.

However, if one performs an anneal prior to deposition

and utilizes a liquid N2 cooled shroud in the e-beam

deposition process, thereby improving the vacuum during

deposition through the cryo-adsorption of residual gasspecies such as hydroxyls, carbide formation is suppressed

and the Hf metal getters the remaining oxygen to form

HfOx on the HOPG surface, as shown in Fig. 13(b). Again,

subsequent oxidation of this film results in the formation of

HfO2 [Fig. 13(c) and (d)]. A comparison of the topography

of these metal–oxide films using ex situ AFM (not shown)

reveals that the AlOx is clustered while the HfOx isrelatively smooth, presumably due to a lower surface

diffusion rate of Hf relative to Al, and is consistent with the

interfacial chemical behavior observed. Taken together,

these results point to the importance of controlling the

interfacial reactions through careful control of the depo-

sition tool conditions, and thus substantial optimization

can be achieved for device development. In situ studies of

the HfO2/graphene (derived from SiC) have also beenrecently reported [179].

As noted previously, improvements in the capacitance

scaling by engineering the interface are necessary.

Fallahazad et al. [167] used Ti as a nucleation layer to

improve the uniformity of the top dielectric as well as an

increase in the dielectric constant. The increase in

dielectric constant of the Al2O3/TiO2 stack was associated

Fig. 12. O1s, C1s, and Al2p spectra for graphite sample with

predeposition anneal at 500 �C to remove physisorbed interfacial

hydroxyls (a) Al as-deposited and (b) Al oxidized in 1000 mbar O2

at 200 �C for 10 min. Sample without predeposition anneal

(c) Al as-deposited and (d) oxidized under the same conditions as (b).

(Reprinted with permission, � 2009 American Institute of Physics [7].)

Fig. 13. 1-nm Hf deposited on (a) exfoliated graphite with

deposition chamber walls at 25 �C and P ¼ 1� 10�8 mbar, (b) annealed

(500 �C/30 min) graphite with chamber walls cooled by liquid N2

and P ¼ 4� 10�10 mbar, (c) Hf oxidized in 1000 mbar O2 at 25 �C,

(d) HfO2 deposited by reactive e-beam deposition with 1� 10�6 mbar

partial pressure of O2. A difference spectrum between the two

graphite+HfO2 C1s peaks is shown in (e); the peak for sample (c)

is broader than (d) by 0.13 eV. (Reprinted with permission,

� 2009 American Institute of Physics [19].)



with a partial crystallinity of the Al2O3. It is interesting tonote that no interdiffusion of the Al and Ti took place as

perhaps expected given the low processing temperature. It

was also noted that the roughness of the oxidized Ti layer

(�0.24 nm) is about half of that for the oxidized Al layer,

consistent with a reduced surface diffusion rate for Ti

relative to Al. The extracted dielectric constant of the

Al2O3/TiO2 stack is larger than that for the Al2O3-only

stack, and that the extracted mobility is also impacted bythe higher dielectric capacitance density obtained through

the incorporation of Ti-based nucleation layer. The falloff

in the mobility with increasing (Al2O3) gate stack thickness

was attributed to Coulomb scattering from charged point

defects (e.g., oxygen vacancies) in the dielectric [167].

Recent studies have also examined the placement of Al2O3

nanoribbons on exfoliated graphene, where top-gate mobi-

lities as high as 23 600 cm2/V�s were reported for the thin-nest top dielectric, 38 nm and a residual carrier concentration

at the Dirac point of about 4.1� 1011 cm�2 [180].

Recently, in situ electrical measurements of ALD Al2O3

deposited on exfoliated graphene utilizing the ozone

functionalization methods described previously indicate a

back-gated mobility as high as 19 000 cm2/V�s have also

been reported [153]. Finally, extensions to deposited low-kdielectrics on exfoliated graphene have been reported forparylene-C, a dielectric normally employed for organic

thin-film transistor development [181]. Further work using

such dielectric deposition methods applied to large-area

CVD graphene is anticipated in the near term.

V. METAL CONTACTS

Successful device fabrication and operation requires lowcontact resistance for the source and drain regions since

this can limit device performance. There has been a

significant amount of effort in decreasing the metal

contact resistance in silicon devices. The contact resis-

tance of metals to graphene or to CNTs is still very high

compared to state-of-the-art contacts in silicon devices.

There have been some advancements in the contact

resistance of metals on graphene, but it is still about anorder of magnitude too high.

There are several issues at this time, metal selection,

graphene surface cleaning, and metal–graphene bonding

type and understanding. Metal selection involves ensuring

that the metal does not fully carburize thus destroying the

graphene or dissolving the graphene, and must have the

desired work function. With the exception of Cu, Ir, Au,

and Ag, most metals either react or can significantlydissolve the carbon under appropriate thermodynamic and

chemical conditions. A few studies have been carried out

to extract the contact resistance of metals on graphene

[10], [182]–[184]. The contact resistance of metals on

graphene was measured by the traditional transfer length

method (TLM) for a several metals and the graphene

carefully characterized. Robinson et al. [10] measured the

contact resistance of the following metals on graphene/SiC: Ti/Au, Cr/Au, Ni/Au, Pt/Au, Cu/Au, and Pd/Au after

various oxygen plasma treatments and found that while the

graphene quality degraded according to Raman measure-

ments, i.e., the D-band intensity increased significantly, the

specific contact resistance decreased to about 10�7 W cm2.

A summary of the process conditions and the effect on the

contact resistance is shown in Fig. 14. This is a major

advancement, but even though there was a large workfunction difference between the various metals, there was

no correlation to the contact resistance. The reasons for the

high contact resistance vary and the lack of correlation to

the specific metal may be associated with the lack of precise

understanding of the graphene–metal interface chemistry,

an area still to be carefully investigated.

Certainly, graphene on SiC maybe the best source of

‘‘clean’’ graphene since exposure to hydrocarbons and other

Fig. 14. Process showing that surface preparation has a significant

effect on the specific contact resistance of Ti to graphenen. (Reprinted

with permission, � 2011 American Institute of Physics [10].)



chemicals used in the processing and transfer of CVDgraphene is much lower. However, the multilayer nature of

graphene on SiC may introduce aspects in the understanding

and controlling the contact resistance in single-layer

graphene that have not been comprehended so far. Recently,

Xia et al. [185] also reported on the reduction of the contact

resistance of Pd to graphene down to about 170 W-cm, but

this is still too high for most device applications. Therefore, it

is important to continue to develop a basic understanding ofthe metal–graphene interface chemistry.

In addition to the basic understanding of the interface

chemistry, it is also important to select the appropriate

metal deposition technique in addition to graphene surface

cleaning and preparation. Nagashio et al. [186] have

recently reported that sputtered Ti led to extremely high

resistivity in comparison to evaporated Ti.

VI. SUMMARYSignificant advancements have been made in the growth

and integration of large-area graphene films over the past

eight years or so. Freestanding extremely large graphene

films can be grown using CVD on weakly interacting

substrates like Cu with transport properties equivalent to

graphene exfoliated from natural graphite. Because of theability to grow very large-area and high-quality graphene

films, the CVD growth process is enabling the develop-

ment of many different applications, from displays to RFdevices. In addition, the community is learning how to

grow relatively large single crystals of graphene on metal

surfaces that will hopefully help identify the material

requirements for the most demanding devices.

Because of the physical size demands and manufactur-

ability, it is likely that CVD processes, in general, will win

out over other graphene production means for HVM of

graphene-based high-performance devices. Growth ofgraphene on SiC can provide very high-quality material

but many applications require large substrate areas that

this technique cannot currently provide. CVD of graphene

on dielectrics would be a preferred process; however,

there are still many challenges that face this approach, and

more work needs to be done. The contact resistance also

requires a significant amount of work in understanding

metal–graphene interface, and the effect of extrinsicfactors of which at this stage of development there are

many. Finally, an equivalently challenging problem is the

scaling of gate dielectrics on graphene with a desired

dielectric constant. While dielectrics have been scaled on

Si down to about 1 nm in products and dielectrics of

thicknesses much lower than 1 nm can de deposited or

grown on Si, the deposition details of dielectrics on

graphene still need more work. The use and developmentof 2-D crystals such as hBN and TMD could help address

the need for scaled dielectrics. h

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ABOUT T HE AUTHO RS

Luigi Colombo (Fellow, IEEE) received the B.S.

degree in physics from the Iona College, New

Rochelle, NY, USA, in 1975 and the Ph.D. degree in

materials science from the University of Rochester,

Rochester, NY, USA, in 1980.

From 1980 to 1981, he was a Postdoctoral

Fellow at the Mechanical and Aerospace Science

Department, University of Rochester, Rochester,

NY, USA. In 1981, he joined Texas Instruments (TI)

Incorporated, Dallas, TX, USA, where he first

worked on infrared detector materials until 1995. Over this period, he

developed a HgCdZnTe liquid phase epitaxy process, which he also put in

production in 1991, and it is still in production today. Since then, he has

been responsible for the development of high-k capacitor metal–

insulator–metal structures for dynamic random access memories,

development of high-k gate/metal gate transistor gate stack using

Hf-based dielectrics, and low-leakage SiON-based 45-nm transistor gate

stack development. He is currently a TI Fellow in the External Research

Development Group at TI, where he is responsible for the development of

newmaterials such as graphene and its integration in new device flows for

beyond complementary metal–oxide–semiconductor (CMOS) device

technology as part of the Nanoelectronics Research Initiative. He is also

an Adjunct Professor in the Department of Materials Science and

Engineering, University of Texas at Dallas. He is the author or coauthor

ofmore than 140 publications in peer-reviewed journals and proceedings,

more than 100 contributed and 60 invited talks at international meetings

and symposia, has written three chapters in edited books, and holds a

total of 107 U.S. and international patents. He is on the European

Community Graphene Flagship Advisory Board, the AIP Corporate

Associates Advisory Committee, Cambridge University Graphene Centre

Advisory Board, and the Solid State Electronics Editorial Board.

Dr. Colombo is a member of the American Physical Society, the

Material Research Society, the American Vacuum Society, and the

Electrochemical Society. In 2012, he was elected to IEEE Fellow for his

contributions to infrared detector materials and devices and high-k

dielectrics in integrated circuits.



Robert M. Wallace (Fellow, IEEE) received the

Ph.D. degree in physics from the University of

Pittsburgh, Pittsburgh, PA, USA, in 1982, 1984,

and 1988, respectively.

He was then a Postdoctoral Research Associate

in Chemistry with the Pittsburgh Surface Science

Center, Pittsburgh, PA, USA. In 1990, he joined as a

Member of Technical Staff (MTS) with the Texas

Instruments Central Research Laboratories, Dallas,

TX, USA, where he was elected Senior MTS in 1996.

In 1997, he was appointed to manage the Advanced Technology Branch

that focused on advanced device concepts and the associated material

integration issues. In May 1999, he joined as Professor of Materials

Science and Director of the new Laboratory for Electronic Materials and

Devices with the University of North Texas, Denton, TX, USA. In 2003, he

joined as Professor of Electrical Engineering and Physics with the

University of Texas at Dallas (UT-Dallas), Richardson, TX, USA. He has

authored or coauthored over 225 publications in peer-reviewed journals

and proceedings and 70 U.S. and international patents. His research

interests include materials and integration issues for advanced logic and

memory technologies.

Dr. Wallace serves on the editorial board of the Journal of Materials

Science: Materials in Electronics and Applied Surface Science. He was

named Fellow of the American Vacuum Society (AVS) in 2007 and an IEEE

Fellow in 2009 for his contributions to the field of high-k dielectrics in

integrated circuits. He holds the Erik Jonsson Distinguished Chair in the

Erik Jonsson School of Engineering and Computer Science at UT-Dallas.

He is also a member of the AVS, the Materials Research Society, the

American Chemical Society, and the Electrochemical Society.

Rodney S. Ruoff received the Ph.D. degree in

chemical physics from the University of Illinois at

Urbana-Champaign, Urbana, IL, USA, in 1988.

He joined the University of Texas at Austin

(UT-Austin), Austin, TX, USA, as a Cockrell Family

Regents endowed chair in September 2007. He was

a Fulbright Fellow in 1988–1989 at the Max Planck

Institute fuer Stroemungsforschung, Goettingen,

Germany. Prior to joining UT-Austin, he was the

John Evans Professor of Nanoengineering in the

Department of Mechanical Engineering at Northwestern University,

Evanston, IL, USA, and Director of NU’s Biologically Inspired Materials

Institute from 2002 to 2007. He has coauthored over 300 peer-reviewed

publications devoted to chemistry, physics, materials science, mechanics,

engineering, and biomedical science; cofounded Graphene Energy, Inc.;

and is the founder of Graphene Materials, LLC. and Nanode, Inc.

Dr. Ruoff is on the editorial board of Composites, Science, and

Technology; Carbon; Journal of Nanoengineering and Nanosystems; and

is a Managing Editor and Editorial Board Member of NANO. He is a Fellow

of the Materials Research Society (MRS), the American Physical Society

(APS), and the American Association for the Advancement of Science

(AAAS). He was a Distinguished Chair Visiting Professor at Sungkyukwan

University’s Advanced Institute of NanoTechnology (SAINT) for several

years and has been recently named that again. He is a Fellow of the APS;

was a Lee Hsun Lecture Award recipient, 2009, Institute of Metal

Research, Chinese Academy of Sciences, Shenyang, China; and was listed

as the 16th most cited materials scientist of among the top 100 most cited

for the decade 2000–2010 (http://bucky-central.me.utexas.edu/

RuoffsPDFs/THE%20Top%20100%20Materials%20Scientists).



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