InvenSense MPU-6050ES 3-Axis R-1208-901 … · 1.0.0 Top Level Diagram ... 12.1.0 Resistor Ladder...

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InvenSense MPU-6050ES 3-Axis Gyro/Accelerometer ASIC Circuit Analysis of Analog Blocks Chapter Excerpt - Voltage ReferenceGenerator

InvenSense MPU-6050ES 3-Axis Gyro/Accelerometer ASIC

Overview

Introduction

Brief Design Overview

Component Descriptions

Device Summary

References

Figures To view, please click on the appropriate bookmark in the panel on the left.

0.1.1 Package Markings 0.1.2 Package X-Ray 0.1.3 Pin Configuration 0.1.4 Die Markings 0.2.1 Die Photograph 0.2.2 Annotated Die Photograph 0.2.3 Die Architecture 0.2.4 Block Diagram 0.2.5 Single-Axis Gyroscope Signal Path

Schematics

1.0.0 Top Level Diagram 2.0.0 I/O Interface 2.1.0 Enabled Schmitt Trigger 3.0.0 SDA Interface 3.1.0 Buffer 3.2.0 Enable Generator 4.0.0 Self-Test Accelerometer and Second Order Sigma-Delta ADC 4.1.0 Latch 4.2.0 1 Bit DAC B 4.3.0 1 Bit DAC 4.4.0 Amplifier 4 4.5.0 Amplifier 3 4.6.0 Amplifier 2 4.7.0 Variable Capacitor Feedback 4.8.0 Variable Capacitor Feedback Controller


4.9.0 Reference Generator 4.10.0 Data Path Selector 5x 4.10.1 Data Path Selector 4.11.0 Clock 4.11.1 Nonoverlapping Clock Generator 2 4.11.2 Counter 4.11.3 Clock Selector 4.11.4 Latch 4.12.0 Level Shifter 4.13.0 Integrator 4.13.1 Amplifier 4.13.2 Buffer 4.13.3 Bias Reference 4.13.4 Variable Capacitor Feedback Controller 4.13.5 Variable Capacitor Feedback 4.14.0 Switch Capacitor Control 4.15.0 Data Path Selector 3x 5.0.0 SCL Interface 6.0.0 I/O Interface 7.0.0 Self-Test Accelerometer and Second Order Sigma-Delta ADC 7.1.0 Clock 7.1.1 Nonoverlapping Clock Generator 1 7.2.0 Integrator 7.2.1 Variable Capacitor Feedback Controller 7.2.2 Variable Capacitor Feedback 7.3.0 Data Path Selector 3x 8.0.0 Clock Data Interface 9.0.0 Single-Axis Gyroscope Signal Path 9.1.0 Second Order Sigma-Delta ADC 9.1.1 1 Bit DAC 9.1.2 1 Bit DAC 9.1.3 Latch 9.1.4 Latch 9.1.5 Comparator 9.1.6 Amplifier


9.1.7 Reference Generator Amplifier 9.1.8 Amplifier 9.1.9 ADC Clock 9.1.9.1 Integrator Switch Clock 9.1.9.2 VIN Switch Clock 9.1.9.3 Voltage Reference Generator Clock 9.2.0 Anti-Aliasing Filter 9.2.1 AAF Bias Generator 9.2.2 Switch Control 9.2.3 Switch Control 9.2.3.1 Decoder (3-to-8 Bit) 9.2.4 Feedback Amplifier 9.2.5 AAF Integrator Amplifier 9.2.6 AAF Integrator Amplifier 2 9.2.7 Feedback Amplifier 2 9.2.8 AAF Integrator Amplifier Type 2 9.2.9 Feedback Amplifier Type 2 9.3.0 Demodulator 1 9.3.1 Switch 9.3.2 Switch Control 9.3.2.1 Decoder (3-to-8 Bit) 9.3.3 Buffer 1 9.3.4 Bias Generator 9.3.5 Buffer 2 9.4.0 Coriolis Sense Amplifier 9.4.1 Variable Feedback Capacitor 9.4.2 Switch 9.4.3 Switch Control 9.4.3.1 Decoder (3-to-8 Bit) 9.4.4 Integrator Amplifier 9.4.4.1 Variable Compensation Capacitor 2 9.4.4.2 Variable Compensation Capacitor 1 9.4.5 Feedback Amplifier 9.4.6 Integrator 1 Bias 9.4.7 Subthreshold MOSFET Bias 9.4.8 Capacitor Switch Control 9.4.9 Voltage Reference Generator 9.4.9.1 Amplifier 9.5.0 Sense Amplifier 9.5.1 Switch


9.5.2 Switch 9.5.3 Switch 9.5.4 Switch Control 9.5.4.1 Decoder (3-to-8 Bit) 9.5.5 Switch 9.5.6 Variable Feedback Capacitor 9.5.7 Subthreshold MOSFET Bias 9.5.8 Integrator 2 Bias 9.5.9 Feedback Amplifier 9.5.10 Sense Amplifier 9.5.10.1 Variable Compensation Capacitor 1 9.5.10.2 Variable Compensation Capacitor 2 9.5.11 Capacitor Switch Control 9.5.12 Voltage Reference Generator 9.5.12.1 Amplifier 9.6.0 Feedthrough Cancellation 9.7.0 Amplitude Control 9.7.1 Buffer 9.7.2 Buffer 9.7.3 Data Switch 9.7.4 Switch 9.7.5 Counter 9.7.6 Amplifier 9.7.7 Amplifier 9.7.8 Amplifier 9.7.9 Amplifier 9.7.10 Comparator 9.7.11 Variable RC Feedback 9.7.12 Amplitude Switch Control 9.8.0 Shutdown Interface 9.9.0 Clock Divider 9.10.0 Drive Loop Data Interface 9.11.0 Bias Generator 9.12.0 Bias Generator 9.13.0 Shutdown Control Interface 9.14.0 Level Shifter 9.15.0 Quadrature Sine Wave Oscillator 9.15.1 5 Bit Decoder 9.15.2 Resistor Ladder (32 Bit) 9.15.3 Amplifier


9.15.4 Amplifier 9.15.5 Bias Generator 9.15.6 Switch 9.15.7 Amplifier 9.15.8 Variable Feedback Capacitor 9.15.9 Variable Capacitor Feedback Controller 9.15.10 Amplifier 10.0.0 Self-Test Accelerometer and Second Order Sigma-Delta ADC 10.1.0 Integrator 10.1.1 Variable Capacitor Feedback 10.2.0 Data Path Selector 5x 10.3.0 Data Path Selector 3x 10.3.1 Data Path selector 10.4.0 1 Bit DAC 11.0.0 VLOGIC Interface and ESD 12.0.0 Reference Generator and Temperature Sensor 12.1.0 Resistor Ladder (16 Bit) 12.2.0 4 Bit Decoder 12.3.0 Bias Generator 12.4.0 Level Shifter 12.5.0 Buffer 12.6.0 Buffer 12.7.0 Buffer 12.8.0 Buffer 12.9.0 Bias Generator 12.10.0 Bias Generator 12.11.0 Control Interface 12.12.0 Amplifier 12.13.0 Amplifier 12.14.0 Voltage Reference Generator 12.14.1 Amplifier 12.15.0 Regulator 12.15.1 Level Shifter 12.15.2 Level Shifter 12.15.3 Amplifier 12.15.4 Amplifier 12.16.0 Bias Generator


12.16.1 Variable Bias Generator 1 12.16.2 Variable Bias Generator 2 12.16.3 Voltage Reference Generator 2 12.16.3.1 Amplifier 13.0.0 Charge Pump with Clock Input Control 13.1.0 Bias Generator 13.2.0 Buffer 13.3.0 Charge Pump 13.4.0 Clock Data Interface 13.5.0 Internal Bypass Capacitor Selector 13.6.0 Amplifier 13.7.0 Clocked Comparator 13.7.1 Nonoverlapping Clock Generator 13.8.0 Clock Divider 13.9.0 Counter 13.10.0 Local Oscillator 14.0.0 SAR ADC (12 Bit) 14.1.0 Buffer 14.2.0 Comparator with Sample-and-Hold 14.2.1 Comparator 14.2.2 Amplifier 14.3.0 Counter 14.3.1 S/R Latch 14.4.0 SAR Control 14.5.0 Successive Approximation Register 14.6.0 DAC (12 Bit) 14.6.1 Resistor Ladder 2 14.6.2 Resistor Ladder 1a 14.6.3 Resistor Ladder 1b 14.6.4 Resistor Ladder 1c 14.6.5 Resistor Ladder 1d 14.6.6 Resistor Ladder 1e 14.6.7 Resistor Ladder 1f 14.6.8 Resistor Ladder 1g 14.6.9 Resistor Ladder 1h


15.0.0 I/O Interface 16.0.0 Charge Pump Supply Enable 16.1.0 ESD Protection 17.0.0 Bandgap Voltage and Current Reference 17.1.0 Voltage Reference Generator 17.2.0 Bandgap Reference Generator 18.0.0 Voltage Reference Generator 18.1.0 Amplifier 18.2.0 Bias Generator 18.3.0 Amplifier 18.4.0 Bias Generator 18.5.0 Amplifier 18.6.0 Charge Pump 18.7.0 Clock Divider 18.8.0 Buffer 18.9.0 Switch 18.10.0 Amplifier 18.11.0 Bias Generator 19.0.0 Switch 20.0.0 Output Interface 20.1.0 Enabled Schmitt Trigger 21.0.0 I/O Interface 21.1.0 Schmitt Trigger 21.2.0 Tri-State Buffer with Level Shifter 22.0.0 Clock Generator Subset 22.1.0 Nonoverlapping Clock Generator Interface 22.2.0 Core Logic Clock Interface 22.2.1 Core Clock Frequency Divider 1 22.2.2 Core Clock Frequency Divider 2 22.2.3 Nonoverlapping Clock Generator 22.2.4 Level Shifter


22.2.5 Temperature Sensor with Hysteresis Feedback 22.2.5.1 Amplifier 22.2.6 Bias Generator 27.0.0 Clock Circuitry 27.1.0 Control Logic 27.1.1 S/R Generator Counter 27.1.2 Digital Logic 27.1.3 Digital Logic 27.1.4 S/R Clock Divider 27.2.0 Level Shifter 27.3.0 Clock Divider 27.3.1 Combinational Logic 27.3.2 Combinational Logic 27.3.3 Combinational Logic 27.3.4 Combinational Logic 27.3.5 Combinational Logic 27.3.6 Clock Divider 27.3.7 Combinational Logic 27.4.0 Output Routing Stage 27.6.0 Unused Transistors 27.7.0 Clock Source Selector 27.7.1 PDF Clock Selector Control Logic 27.7.2 Decoder 27.8.0 Combinational Logic 27.8.1 Digital Logic 27.8.2 Control Logic 27.9.0 Clock Switch 27.10.0 Clock Switching Interrupt Generator 27.10.1 Combinational Logic 27.10.2 Combinational Logic 27.10.3 Combinational Logic 27.10.4 Combinational Logic 27.10.5 Combinational Logic 27.10.6 Combinational Logic 27.10.7 Combinational Logic 27.11.0 Clock Generator 27.11.1 Clock Divider 27.11.2 Variable Bias Current Generator with Controller


27.11.3 Relaxation Oscillator 27.11.3.1 Double-Ended Differential Amplifier 27.11.3.2 Double-Ended Differential Amplifier 27.11.3.3 Single-Ended Differential Amplifier 27.11.3.4 Single-Ended Differential Amplifier 27.11.4 Phase-Locked Loop 27.11.4.1 Bias Generator 27.11.4.2 Charge Pump 27.11.4.3 Loop Filter 27.11.4.4 Phase Frequency Detector 27.11.4.5 Voltage Controlled Oscillator 27.11.4.5.1 Variable Bias Generator 27.11.4.5.2 Level Shifter 27.11.4.6 S/R Generator Counter 27.12.0 CLKIN Interface 27.12.1 Control Logic 27.12.2 Clock Divider 27.13.0 I/O Interface 27.14.0 Clock Divider 27.15.0 AN_HJ_OSC_2 28.0.0 OTP Memory Block 28.1.0 OTP Memory 28.1.1 Dummy Cell 28.1.2 Dummy Cell 28.1.3 Memory Select Switch 28.1.4 OTP Memory 28.1.5 Memory Select Switch 28.1.6 OTP Memory 28.1.7 OTP Memory 28.1.8 Memory Select Switch 28.1.9 OTP Memory 28.1.10 OTP Memory 28.1.11 OTP Memory 28.1.12 OTP Memory 28.1.13 OTP Memory 28.1.14 OTP Memory 28.1.15 OTP Memory 28.1.16 Memory Select Switch 28.1.17 OTP Memory


28.1.18 OTP Memory 28.1.19 OTP Memory 28.1.20 OTP Memory 28.1.21 OTP Memory 28.1.22 Memory Select Switch 28.1.23 Memory Select Switch 28.1.24 OTP Memory 28.2.0 OTP Memory Controller 28.2.1 Level Shifter 28.2.2 Decoder 28.2.3 Level Shifter 28.2.4 Decoder 28.2.5 Decoder 28.2.6 Combinational Logic 28.2.7 Combinational Logic 30.0.0 Single-Axis Gyroscope Signal Path 30.1.0 Second Order Sigma-Delta ADC 30.1.1 1 Bit DAC 30.1.2 ADC Clock 30.1.2.1 VIN Switch Clock 30.1.2.2 Integrator Switch Clock 30.2.0 Quadrature Sine Wave Oscillator 30.2.1 Amplifier 30.2.2 Resistor Ladder (32 Bit) 30.3.0 Sense Amplifier 30.3.1 Variable Feedback Capacitor 30.3.2 Sense Amplifier 30.3.2.1 Variable Compensation Capacitor 2 30.3.2.2 Variable Compensation Capacitor 1 30.4.0 Anti-Aliasing Filter 30.5.0 Demodulator 1 30.6.0 Coriolis Sense Amplifier 30.6.1 Integrator Amplifier 30.6.2 Capacitor Switch Control 30.7.0 Amplitude Control 30.7.1 Amplifier 30.7.2 Amplifier 30.7.3 Variable RC Feedback 30.7.4 Buffer


30.7.5 Buffer 30.8.0 Bias Generator 30.9.0 Bias Generator 30.10.0 Shutdown Control Interface 30.11.0 Level Shifter 30.12.0 Drive Loop Data Interface 31.0.0 Single-Axis Gyroscope Signal Path 31.1.0 Second Order Sigma-Delta ADC 31.1.1 1 Bit DAC 31.1.2 Amplifier 31.2.0 Quadrature Sine Wave Oscillator 31.2.1 Amplifier 31.2.2 Resistor Ladder (32 Bit) 31.3.0 Sense Amplifier 31.4.0 Anti-Aliasing Filter 31.5.0 Demodulator 1 31.6.0 Coriolis Sense Amplifier 31.7.0 Amplitude Control 31.7.1 Variable RC Feedback 31.7.2 Amplitude Switch Control 31.8.0 Bias Generator 31.9.0 Bias Generator 31.10.0 Shutdown Control Interface 31.11.0 Drive Loop Data Interface

Cell Library

About Chipworks

BIA

S1

BIA

S2

NINV

SD

OUT

18.8.0 Buffer

MI353INV

ENP

18.9.0 Switch

MI354

Z1 Z2

SDSD2

IREF

BREF1

BREF4BREF3

BA

MP

4B

AM

P3

BA

MP

1

BP

2B

P1

BA

MP

2

BREF2

18.11.0 Bias generator

MI357

C1320NMOSCAParea=1.148n



R1323

sq=0.745kRPOLY

R1335

sq=0.745kRPOLY

R1345

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R13

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sq=9

57.0

RP

OLY

R13

33

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57.0

RP

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R13

39

sq=9

57.0

RP

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R15

16

sq=2

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PO

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R1517

sq=0.627kRPOLY

V1G_AND22_14_9

X2632

V1G_INV_14_7

X3188

V1G_INV_14_7

X3359

X2840

V1G_OR3_14_7B

P2

BP

1

INV

NINVSD

OUT

18.1.0 Amplifier

MI343

BP

2B

P1

INV

NINVSD

OUT

18.3.0 Amplifier

MI345

IREFSD

BP1BP2

BREF1BREF2BREF3BREF4


MI346

VPP2

SD

N

INV BIA

S

NINV

SD

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18.5.0 Amplifier

MI347

CDNCK VPP2

18.6.0 Charge pump

MI350

CDNCK

SDSDN

18.7.0 Clock divider

MI352

BIA

SB

P2

BP

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INV

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18.10.0 Amplifier

MI355

GNDGNDGND

GND

GND

GND

GND

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IREFSD

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BREF1BREF2BREF3BREF4


MI344

CDNCTL3CDNCTL2CDNCTL1

SDCTL<4>

BREF23

BREF32

BREF11

LSUPPBUFENA

SD4

CK

LSUPPBUF

SD2

SD3

LSUPP

LGCSUP2

LGCSUP

LSUPP2

BREF24

BREF22BREF21

BREF14

BREF12BREF13

BREF33BREF34

BREF31

VBG1N3

VBG1N2

VBG1N1

BUFVREF24

Note: Device sizes in microns (as measured from images) Device Type:InvenSense MPU-6050ES

Copyright (C) 2012 Chipworks Incorporated

18.0.0 Voltage Reference GeneratorDie Markings:

Date Code:

3-Axis Gyro/Accelerometer ASICMANTIS-B3 <InvenSense logo>REV.B.3 2011 CC1129Template: dsheetp

N16621.00u/8.00u

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55

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34

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74

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76

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20

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60u

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67

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P16

68

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69

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70

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P16

71

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P16

73

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77

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78

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8.00

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27

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88

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90

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75

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P15

76

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79

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82

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ngs:

Dat

e C

ode:

3-A

xis

Gyr

o/A

ccel

erom

eter

AS

ICM

AN

TIS

-B3

<Inv

enS

ense

logo

>R

EV

.B.3

201

1 C

C11

29C

opyr

ight

(C) 2

012

Chi

pwor

ks In

corp

orat

edcs

heet

Tem

plat

e:

R13

32

sq=3

2.8

RP

OLY

R13

36

sq=3

2.8

RP

OLY

R13

31

sq=0

.262

kR

PO

LY

P15

60

m=2

2.00

u/1.

00u

P15

61

m=2

2.00

u/1.

00u

P15

63

m=2

2.00

u/1.

00u

P15

64

m=2

2.00

u/1.

00u

P15

65

m=2

2.00

u/1.

00u

P15

66

m=2

2.00

u/1.

00u

P15

67

m=2

2.00

u/1.

00u

P15

68

m=2

2.00

u/1.

00u

P15

74

m=1

4.00

u/0.

60u

P16

10

m=4

8.00

u/8.

00u

P16

11

m=4

8.00

u/8.

00u

P16

12

m=4

8.00

u/8.

00u

P16

13

m=4

8.00

u/8.

00u

P16

14

m=4

8.00

u/8.

00u

P16

16

m=4

8.00

u/8.

00u

P16

19

m=4

8.00

u/8.

00u

P16

17

m=2

8.00

u/8.

00u

P16

18

m=2

8.00

u/8.

00u

X65

26

V1G

_BU

F2_1

5_7

X7210


GN

D

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

BR

EF1

SD

BP

1

BP

2

BR

EF4

BR

EF2

BR

EF3

IRE

F

Unused

Not

e: D

evic

e si

zes

in m

icro

ns (a

s m

easu

red

from

imag

es)

Dev

ice

Type

:In

venS

ense

MP

U-6

050E

S

Cop

yrig

ht (C

) 201

2 C

hipw

orks

Inco

rpor

ated

18.4

.0 B

ias

Gen

erat

orD

ie M

arki

ngs:

Dat

e C

ode:

3-A

xis

Gyr

o/A

ccel

erom

eter

AS

ICM

AN

TIS

-B3

<Inv

enS

ense

logo

>R

EV

.B.3

201

1 C

C11

29Te

mpl

ate:

bshe

et

VPP2

VPP2

VPP2

VPP2

N15

254.

20u/

0.60

um

=1

N15

314.

20u/

0.60

um

=1

N15

324.

20u/

0.60

um

=1

GN

DG

ND

GN

D

GN

DG

ND

R15

18

sq=6

7.2

RP

OLY

P15

21

m=3

4.00

u/0.

60u

N15

244.

20u/

0.60

um

=1

N15

261.

60u/

4.00

um

=4

N15

281.

60u/

4.00

um

=4

N15

291.

60u/

4.00

um

=4

N15

271.

60u/

4.00

um

=2

N15

301.

60u/

4.00

um

=8

P15

33

m=6

4.00

u/4.

00u

P15

34

m=6

4.00

u/4.

00u


P15

53

m=1

4.00

u/0.

60u

P15

54

m=6

4.00

u/8.

00u

P15

55

m=2

44.

00u/

8.00

uP

1556

m=3

64.

00u/

8.00

u


X72

77

V1V

SG

_IN

VD

IF_2

0L5_

60L6

LS

GN

DG

ND

GN

D

SD

N

SD

OU

T

BIA

S

NIN

V

VP

P2

INV

Not

e: D

evic

e si

zes

in m

icro

ns (a

s m

easu

red

from

imag

es)

Dev

ice

Type

:In

venS

ense

MP

U-6

050E

S

Cop

yrig

ht (C

) 201

2 C

hipw

orks

Inco

rpor

ated

18.5

.0 A

mpl

ifier

Die

Mar

king

s:

Dat

e C

ode:

3-A

xis

Gyr

o/A

ccel

erom

eter

AS

ICM

AN

TIS

-B3

<Inv

enS

ense

logo

>R

EV

.B.3

201

1 C

C11

29Te

mpl

ate:

bshe

et

N15696A1.40u/0.60um=1

N15697A1.40u/0.60u

m=1

V1G

_AN

D22

_14_

9

X15

56X

1455

V1G

_BU

FSE

R_1

4_9D

16

2 of

4 ...

X15

37

V1G

_BU

FSE

R_1

4_9D

16

2 of

4 ...

X15

57

V1G

_NA

ND

2_14

_9

VD

D

C13

17N

MO

SC

AP

area

=6.0

6n

C13

18N

MO

SC

AP

area

=0.2

02n

C13

19N

MO

SC

AP

area

=0.1

62n

R15

15

sq=2

2.4

RP

OLY

R15

19

sq=2

2.4

RP

OLY

C15

20N

MO

SC

AP

area

=2.0

n

C15

41M

ETA

LCA

Par

ea=4

.56n

C15

42M

ETA

LCA

Par

ea=2

.555

n

C15

43M

ETA

LCA

Par

ea=0

.192

n

C15

44M

ETA

LCA

Par

ea=3

.809

n

C15

52N

MO

SC

AP

area

=0.8

n

C15

58M

ETA

LCA

Par

ea=3

.864

n

C15

59M

ETA

LCA

Par

ea=7

.2n

C30

70N

MO

SC

AP

area

=0.1

6n

N15

693A

1.40

u/0.

60u

m=1

N15

695A

1.40

u/0.

60u

m=1

P15698

m=16.00u/0.50u

P15699

m=16.00u/0.50u

P15

700

m=1

6.00

u/0.

50u

P15

701

m=1

6.00

u/0.

50u

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

NDG

ND

VD

D

CK

CD

N

VP

P2

Unused

Not

e: D

evic

e si

zes

in m

icro

ns (a

s m

easu

red

from

imag

es)

Dev

ice

Type

:In

venS

ense

MP

U-6

050E

S18

.6.0

Cha

rge

Pum

pD

ie M

arki

ngs:

Dat

e C

ode:

3-A

xis

Gyr

o/A

ccel

erom

eter

AS

ICM

AN

TIS

-B3

<Inv

enS

ense

logo

>R

EV

.B.3

201

1 C

C11

29C

opyr

ight

(C) 2

012

Chi

pwor

ks In

corp

orat

edcs

heet

Tem

plat

e:

V1G

_AN

D22

_14_

9

X26

02

X29

84

V1G

_OR

2_14

_7

V1G

_DFC

_14_

9

X63

6

Q

QN

CP

D CD

NDFF

V1G

_IN

V_1

4_7

X32

26

V1G

_IN

V_1

4_7

X34

16

V1G

_DFC

_14_

9

X63

8

Q

QN

CP

D CD

NDFF

V1G

_DFC

_14_

9

X66

3

Q

QN

CP

D CD

NDFF

V1G

_DFC

_14_

9

X66

4

Q

QN

CP

D CD

NDFF

V1G

_DFC

_14_

9

X66

5

Q

QN

CP

D CD

NDFF

V1G

_DFC

_14_

9

X66

8

Q

QN

CP

D CD

NDFF

V1G

_DFC

_14_

9

X67

2

Q

QN

CP

D CD

NDFF

ZN

SE

GC

OR

E01

S3

X24

44

X23

537

V1G

_BU

F2_1

4_9

SD

NS

D

CK

CD

N

Not

e: D

evic

e si

zes

in m

icro

ns (a

s m

easu

red

from

imag

es)

Dev

ice

Type

:In

venS

ense

MP

U-6

050E

S18

.7.0

Clo

ck D

ivid

erD

ie M

arki

ngs:

Dat

e C

ode:

3-A

xis

Gyr

o/A

ccel

erom

eter

AS

ICM

AN

TIS

-B3

<Inv

enS

ense

logo

>R

EV

.B.3

201

1 C

C11

29C

opyr

ight

(C) 2

012

Chi

pwor

ks In

corp

orat

edcs

heet

Tem

plat

e:

VDD1!

VDD1! VDD1!

VDD1! VDD1!

VDD1! VDD1!

VDD1! VDD1!

VDD1!

VDD1!

VDD1!

GND!GND!

GND!

GND!GND!

GND!GND!

GND!GND!

GND!GND!

GND!

GND!GND!

GND!GND!

GND!

GND!

GND!

GND!

GND!

P14

13

m=3

2.00

u/0.

18u

P14

14

m=1

82.

00u/

4.00

uP

1417

m=1

2.00

u/4.

00u

P14

18

m=1

2.00

u/4.

00u

P14

19

m=1

2.00

u/4.

00u

P14

20

m=4

4.00

u/0.

18u

P14

21

4.00

u/0.

50u

m=8

P14

22

4.00

u/0.

50u

m=8

P14

40

4.00

u/0.

50u

m=8

P14

41

4.00

u/0.

50u

m=8

P14

29

m=1

4.00

u/1.

00u

P14

30

m=1

4.00

u/1.

00u

P14

39

m=1

4.00

u/1.

00u

P14

56

m=1

1.80

u/1.

00u

P14

57

m=1

1.00

u/1.

00u

N14

704.

00u/

0.30

um

=4

N14

714.

00u/

8.00

um

=8

N14

724.

00u/

8.00

um

=8

N14

884.

00u/

8.00

um

=2

N14

894.

00u/

8.00

um

=1

N14

914.

00u/

8.00

um

=1

N14

874.

00u/

0.30

um

=6

N14

920.

50u/

1.00

um

=1

N14

940.

50u/

1.00

um

=1

N14

930.

50u/

8.00

um

=1

N14

954.

00u/

0.30

um

=2

N14

962.

00u/

0.18

um

=2

N14

971.

00u/

0.18

um

=1

N14

981.

00u/

0.18

um

=1

N14

992.

00u/

0.50

um

=8

N15

002.

00u/

0.50

um

=8P

1416

m=2

2.00

u/0.

18u

P18

607

m=1

1.20

u/0.

18u

V1G

_IN

V_9

_6

X67

42 D OE

Z

V1G_DATAOUT_14_7D2

X825

VD

D1

VD

D1

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

D

VD

D1

SD

OU

T

BIA

S1

BIA

S2

NIN

V

Unused

Unused

Not

e: D

evic

e si

zes

in m

icro

ns (a

s m

easu

red

from

imag

es)

Dev

ice

Type

:In

venS

ense

MP

U-6

050E

S18

.8.0

Buf

fer

Die

Mar

king

s:

Dat

e C

ode:

3-A

xis

Gyr

o/A

ccel

erom

eter

AS

ICM

AN

TIS

-B3

<Inv

enS

ense

logo

>R

EV

.B.3

201

1 C

C11

29C

opyr

ight

(C) 2

012

Chi

pwor

ks In

corp

orat

edcs

heet

Tem

plat

e:

P1461

m=163.00u/0.18u

P1463

m=163.00u/0.18u

N1466A1.50u/0.18um=12

N1467A1.50u/0.18um=12

X64

59

V1G

_BU

FF_2

0_10

EN

P

Z2Z1

Not

e: D

evic

e si

zes

in m

icro

ns (a

s m

easu

red

from

pho

togr

aphs

)D

evic

e Ty

pe:

Inve

nSen

se M

PU

-605

0ES

Cop

yrig

ht (C

) 200

8 C

hipw

orks

Inco

rpor

ated

18.9

.0 S

witc

h

Die

Mar

king

s:

Dat

e C

ode:

3-A

xis

Gyr

o/A

ccel

erom

eter

AS

ICM

AN

TIS

-B3

<Inv

enS

ense

logo

>R

EV

.B.3

201

1 C

C11

29Te

mpl

ate:

ashe

et

R13

26

sq=3

2.8

RP

OLY

R13

29

sq=3

2.8

RP

OLY

R13

28

sq=0

.525

kR

PO

LY

R13

47

sq=4

6.4

RP

OLY

P13

48

m=2

1.60

u/1.

00u

N13

49A

1.50

u/1.

00u

m=1

P13

50

m=4

1.00

u/2.

00u

P13

51

m=4

1.00

u/2.

00u

P13

54

m=2

2.00

u/1.

00u

P13

55

m=2

2.00

u/1.

00u

P13

56

m=2

2.00

u/1.

00u

P13

57

m=2

2.00

u/1.

00u

P13

58

m=8

8.00

u/8.

00u

P13

59

m=2

8.00

u/8.

00u

P13

60

m=1

2.00

u/0.

18u

P13

61

m=2

4.00

u/8.

00u

P13

62

m=2

4.00

u/8.

00u

P13

64

m=4

1.50

u/1.

00u

P13

65

m=8

1.50

u/1.

00u

P13

66

m=4

1.50

u/1.

00u

N13

681.

00u/

8.00

um

=8

N13

691.

00u/

8.00

um

=8

N14

011.

00u/

8.00

um

=2

N13762.00u/8.00u

m=1

N13

772.

00u/

8.00

um

=1

N13

781.

50u/

2.00

um

=1

N13

882.

00u/

1.00

um

=2

N13

892.

00u/

1.00

um

=2

N13

902.

00u/

1.00

um

=2

N13

911.

50u/

1.00

um

=1


N13

982.

00u/

1.00

um

=2

N14021.00u/8.00u

m=6

P14

12

m=4

8.00

u/8.

00u

V1G

_IN

V_1

4_7

X56

09

GN

DG

ND

GN

D

VD

D1

GN

D

VD

D1

GN

DG

ND

GN

DG

ND

GN

D

GN

D

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

P13

63

m=1

61.

50u/

1.00

u

N13

921.

50u/

1.00

um

=3 GN

D

VD

D1

SD

2B

P1

BP

2

OU

T

NIN

V

BIA

S

INV

Unused

Not

e: D

evic

e si

zes

in m

icro

ns (a

s m

easu

red

from

imag

es)

Dev

ice

Type

:In

venS

ense

MP

U-6

050E

S18

.10.

0 A

mpl

ifier

Die

Mar

king

s:

Dat

e C

ode:

3-A

xis

Gyr

o/A

ccel

erom

eter

AS

ICM

AN

TIS

-B3

<Inv

enS

ense

logo

>R

EV

.B.3

201

1 C

C11

29C

opyr

ight

(C) 2

012

Chi

pwor

ks In

corp

orat

edcs

heet

Tem

plat

e:

R13

27

sq=0

.262

kR

PO

LY

P13

79

m=2

2.00

u/1.

00u

P13

80

m=2

2.00

u/1.

00u

P13

81

m=2

2.00

u/1.

00u

P13

83

m=2

2.00

u/1.

00u

P13

84

m=2

2.00

u/1.

00u

P13

85

m=2

2.00

u/1.

00u

P13

86

m=2

2.00

u/1.

00u

P13

87

m=2

2.00

u/1.

00u

P13

67

m=1

4.00

u/0.

60u

P1394

m=14.00u/0.60u

P13

95

m=1

4.00

u/0.

60u

P13

96

m=1

4.00

u/0.

60u

P1397

m=14.00u/0.60u

P14

03

m=4

8.00

u/8.

00u

P14

04

m=4

8.00

u/8.

00u

P14

05

m=4

8.00

u/8.

00u

P14

06

m=4

8.00

u/8.

00u

P14

07

m=4

8.00

u/8.

00u

P14

08

m=4

8.00

u/8.

00u

P14

10

m=2

8.00

u/8.

00u

P14

11

m=2

8.00

u/8.

00u

X48

74

V1G

_BU

F2_1

5_7

X56

08

V1G

_BU

F2_1

5_7

X7209


VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

VD

D1

P13

82

m=2

2.00

u/1.

00u

P14

09

m=2

8.00

u/8.

00u

VD

D1

BR

EF2

SD

2

SD

BA

MP

2

BP

1

BP

2

BA

MP

1B

AM

P3

BA

MP

4

BR

EF3

BR

EF4

BR

EF1

IRE

F

Not

e: D

evic

e si

zes

in m

icro

ns (a

s m

easu

red

from

imag

es)

Dev

ice

Type

:In

venS

ense

MP

U-6

050E

S

Cop

yrig

ht (C

) 201

2 C

hipw

orks

Inco

rpor

ated

18.1

1.0

Bia

s G

ener

ator

Die

Mar

king

s:

Dat

e C

ode:

3-A

xis

Gyr

o/A

ccel

erom

eter

AS

ICM

AN

TIS

-B3

<Inv

enS

ense

logo

>R

EV

.B.3

201

1 C

C11

29Te

mpl

ate:

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About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company’s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world’s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation – earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches.

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Chipworks 1891 Robertson Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T 1-613-829-0414 F 1-613-829-0515 Web site: www.chipworks.com Email: [email protected]

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InvenSense MPU-6050ES 3-Axis R-1208-901 … · 1.0.0 Top Level Diagram ... 12.1.0 Resistor Ladder...

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Transcript of InvenSense MPU-6050ES 3-Axis R-1208-901 … · 1.0.0 Top Level Diagram ... 12.1.0 Resistor Ladder...