Submitted By:

K.Jyothir Ganesh

1st Sem M.Tech

Dept of E&C SJCE

1

Content

Pre–Requiste

Canonical Method

Water fall vs. Spiral

Top Down vs. Bottom-Up

Top Level Methods

Design Specification & IP Design

2

Challenges Faced in Designing Time-to- market pressure

Quality of Results in performance, power

Increasing chip complexity leads to difficult in verification

Area of expertise is scattered

Constantly changing tools and guidelines for Designing

Organizational Challenges

3

Criteria followed in design

Design Reuse in key Factor in chip design.

Good Documentation of the design is very necessary.

Integration of Soft & Hard core in a SOC design.

Routing , Placement Verification & Timing

No Neglecting Software Part

Virtual Socket Interface Alliance

4

Good Design Technique Good Documentation Technique

Good Coding

Thorough Commenting

Well designed Verification

Robust Design

Correct Design

5

Design to Reuse Easily fitted for various applications

Soft & Hard Core should Support Multiple Technology

Should Support any Simulator

Designed for standard based Interfaces

Verification should be done highest confidence

Fully Documentated design

6

Economics of Reuse Will every design is made as reusable ?

Is it worth to purchase all IP core?

Whether it is viable to design all block as explicitly reusable ?

Whether there should be a dedicated team designing reusable blocks.

Not all IP are near to specification & correct .

7

Description It is also known as Basic or Generic form SOC design

Method.

Micro processor may 8-bit 8051 to 64 bit RISC.

Memory Sub System may Single or Multi Level like SRAM/DRAM.

I/O controller may be USB, PCI, Ethernet, IEEE 1394, A to D & D to A converter, Electro mechanical or Electro Optical converter.

Video decoder are may be AVI, MPEG or ASF.

External memory may be Flash.8

Canonical Design Methodology

9

System Design flow Methods

10

Water Fall &

Spiral Top - Down

Water Fall Design Method

11

Description of Water Fall design flow Design flow will take place from Phase to Phase without

interaction between team.

System Architecture : In this phase, specification & model of the system will take place.

Algorithm developed by specification is passed to design team to develop RTL for Soc .

Synthesis experts synthesizes the Asic into Gate-Level Net list.

12

Continued…. Time verification is done before physical placing &

routing is completed.

A prototype chip is built & tested

Prototype is chip is passed on to software team

Here testing & debugging is done

13

De – Merit Not suitable for Large & Deep

Submicron's design.

Physical design process should considered early in designing level to meet performance goals

Design transferred from one team to another may not have clarity & Clean

No concurrency in Software & Hardware designing

14

Characteristic of Spiral Method Parallelism & Concurrencies are maintained in H/W &

S/W development.

Verification & Synthesis are conducted parallely.

Floor Planning,Placing & Routing included in synthesis process.

Conditional Development of Modules.

Pre-planned Iteration

15

16

Spiral Method

Top Down Design Process Method Def: It’s a method start with Specification and

decomposition and wind up with Integration & verification.

First Complete set Specification is made ready before starting of subsystem & modules.

Architecture , Algorithms, Design including S/W & H/W are refined & co -simualtion if necessary.

Verify all aspect of design like functionality, Timing etc.

17

Design Specification Def: its expected behaviors shown by the System.

Different specifications are like Functional, Architecture.

H/W Specification: Functionality, External Interface to S/W, Timing, Performance, Physical Design.

S/W Specification: Functionality, Timing Performance,

S/W Structure, Kernel & Interface to hardware

18

Types of Specification

19

Formal Specification

Executable Specification

Widely not use in commercial

Presently used as research topic

VSPEC Language are used formal Specification

Design are defined Independently of any implementation

Presently used in all design.

It address only Functional Behavior of system .

C, C++ language are used for High Level Specification.

VERILOG used in Low Level Specification

Top Level Design Flow System/Preliminary Specification.

High Level Behavioral Model & Algorithm testing

Refine & Test Behavioral Model.

Hardware & Software Partition/ decomposition.

Hardware Architectural model. (co simulation).

Implementation Blocks (Hardware specification)

20

Top Level Design

21

IP Design

Well defined IP Design leads to Successful SOC Design.

Guidelines for the well defined IP Design is provided by the inputs IP integrator & Chip Designer.

Basic Guidelines are : Discipline, Simplicity & Locality

Soft IP & Hard IP

Synthesis Based Design & Full Costumed

22

References

“Reuse Methodology Manual “

By

Micheal Keating & Pierre Bricuad

23

Thank You

24