Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of...

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Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee

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Outline  Example of VHDL Coding in Xilinx ISE Design Suite  Basic Knowledge of VHDL

Transcript of Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of...

Page 1: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Introduction to VHDL Coding

Wenchao Cao, Teaching Assistant

Department of EECSUniversity of Tennessee

Page 2: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Outline Example of VHDL Coding in Xilinx ISE

Design Suite Basic Knowledge of VHDL

Page 3: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Outline Example of VHDL Coding in Xilinx ISE

Design Suite Basic Knowledge of VHDL

Page 4: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Example of VHDL Coding in Xilinx ISE Design Suite

Work Flow The figure shows the software tools in a logic design project

from schematic to VHDL code to *.bit file for download to BASYS or BASYS2 board.

Page 5: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Implementation of a Full Adder

Page 6: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Create A New Project

Page 7: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Project SettingsChoose TQ144 if you

are using a BASYS board

Page 8: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Create New Sauce Files

Page 9: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.
Page 10: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.
Page 11: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Generated VHDL file template by the software:

• Entity declaration (Entity name)

• Port definition (Port name and direction)

• Architecture body(Write the functions here!)

Page 12: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.
Page 13: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.
Page 14: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Outline Example of VHDL Coding in Xilinx ISE

Design Suite Basic Knowledge of VHDL

Page 15: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Entity declarations • Entity identifier: Lab00

Ports definition• Port names: A, B, Cin, S, Cout• Port directions“in” for input ports, “out” for output ports.

Architecture body• Architecture identifier: Behavioral

Behavioral descriptions• Signal assignment statementS <= A xor B xor Cin;• Logical operatorsand, or, not, xor, nand, nor, xnor (No difference between upper case and lower case.)• Use ( ) to make the statement clearly

expressed.

Basic Modeling Constructs

Page 16: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Example

Signal Assignment Statement

X ABCD ABCD

• Logical operators in lower case

• Logical operators in upper case

• Less parentheses ( )

Page 17: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Example

Assign Logic ‘1’ and Logic ‘0’

1X • Assign value of ‘1’

0Y

• Assign value of ‘0’

Page 18: Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

Introduction to VHDL Coding

QUESTIONS?


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