Introduction to SystemVerilog and Verification

8/11/2019 Introduction to SystemVerilog and Verification

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Introduction to SystemVerilog

and verification

Presented by :

Ritesh Desai

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Agenda

ASIC Flow

Where verification fits into ASIC flow?

Why verification?

HVLs

Why SystemVerilog?

SystemVerilog FeaturesWhat SV has to offer?

Primary objective is to get familiar with SV.

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ASIC Flow

Requirements

Arch Definition

Micro-Arch Definition

Design Entry

Design Verification Physical Design

IC Fabrication

IC Testing

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Verification FlowSpecification

Spec Understanding

Test Plan Development

Defining Verif Env

VE Development Test Case Development

Simulation

Test

Pass?

Bug in

Design?Modify Design

Cov

100%?

Find missing

scenarios Synthesis 4


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Levels Of Verification

RTL Verification : Functional

Gate level Verification : Functional

Transistor Level verification : Functional +Timing

Layout Verification : Functional + Timing

We will talk about RTL Verification only.

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HVLs

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Why SV?

SystemVerilog is a hardware description andVerification language(HDVL)

It is an extensive set of enhancements to IEEE

1364 Verilog-2001 standardsIt has features inherited from Verilog

HDL,VHDL,C,C++

System verilog is the superset of verilog

additional features of system verilog will bediscussed

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Why SV..

System Verilog

Assertions

OOP support

Constrained Randomization

New data types ie,logic

Coverage support

Easy c model integration

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OOP???

Classes

Encapsulation

Inheritance Polymorphism

What is virtual?

What is abstract class? Do we really need it?

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What SV has to offer.???

Data types Arrays Different Processes Constraint Randomization Inter-process sync/communication Program block Interfaces/Clocking block/Mod-ports

Assertions Coverage DPI

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Data types

regr; // 4-state Verilog-2001

logicw; // 4-valued logic, see below

bitb; // 2-state bit 0 or 1

integeri; // 4-state, 32-bits, signed Verilog-2001

byteb8; // 8 bit signed integer

inti; // 2-state, 32-bit signed integer

shortints;// 2-state, 16-bit signed integer

longintl; // 2-state, 64-bit signed integer

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Data types..

String.its same as C data type, operating withfollowing operators.

-> Eqality

-> Non-Eq

-> lt/lte/gt/gte-> Concatenation

-> Replication

-> Indexing

-> Different methods likelen(), putc(..), getc(..),toupper(), tolower(), compare(..), icompare(..),substr(..),atoi(..), atohex(..),atooct(..), atobin(..).

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Data types

User defined data types..

typedef enum {ethernet,ipv4,ipv6,tcp,udp} packet;

Variable declaration :

packet pkt;

Default value of first value of var is 0 if it is not specified.Subsequent variables having incremental value if not

specified.

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Data Types (class)

THISRefer to the current class properties.Ex.

class abc;

int x;

function new(int x);

x = x;

endfunction

task print();

$display(X = %0d,x);

endtask

endclass

module pqr;

abc a1;

initial begin

a1 = new(10);

a1.print();

end

endmodule

Q : what will be output here?15


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class abc;

int x;

function new(int x);

this.x = x;endfunction

task print();

$display(X = %0d,x);

endtaskendclass

module pqr;

abc a1;

initial begin

a1 = new(10);

a1.print();

end

endmodule

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Data Types (class)

Shallow CopyingEx.

class B;

int j = 10;

endclass

B b1;

B b2;

b1 = new;

b2 = b1;

b1.j = 20;

$display(J = %0d,b2.j);

Q : what will be the answer? Why?

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class B;

int j = 10;

endclass

B b1;

B b2;

b1 = new;

b1.j = 20;

b2.copy(b1); // Copies B1 into B2. Allocates separate memory.

$display(J= %0d,b2.j);

Q : what will be the answer? Why?Q : what is this copy method? How it overcomes the problem?

This is called deep copy.

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Data types (class)

Copy methodThis is not defined by SV. Thismethod is to be added by TB Developer.

task copy(B b);if(b != null)

this.j = b.j;

else

$display(ERROR : copy method : b is null,can not copy.);

endtask

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Assignment :Class A;

int i = 5;

Endclass

Class B;

int j = 10;

A a = new;

Endclass

B b1;

B b2;

b1 = new;b2 = b1.copy();

Q : what will be value of b2.i and b2.a.j?Write down code on paper.

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Data types (class)

Inheritance : deriving class from another class.Ex. Class Packet;

..

endclass

class ethPacket extends Packet;

..

endclass

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Data types (Class)

SUPER : refers to the parent class properties.Ex.

class A;

int j = 5;

endclass

class B extends A;

task print();

$display(J = %0d,super.j);endtask

endclass

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Assignment :Class A;

int j;

function init(int j = 5);

this.j = j;

endfunction

function int get();

get = this.j;endfunction

Endclass

Class B extends A;

int j;

//Write down function to get the j of A in calculation.

Endclass

Class C extends B;

int j;

//Write down function to get the j of A in calculation.

endclass

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Data type (class)

Polymorphism : Derived class instance canaccess parent class properties.

Abstract class

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Casting

What is casting??

- Casting is the process of converting onedata type to the other data type.

Three types of casting supported

1. Implicit casting

2. Explicit casting

3. Dynamic casting

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Casting..

Implicit casting

int a = 27;

bit [3:0] temp = a;

Tool takes care of this conversion from int to

4 bit nibble. This is automatic conversion.

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Casting

Explicit casting.

typedef struct {

int a;

} temp_st;

temp_st temp = {30};

logic [31:0] temp_int;

temp_int = temp_st(temp);

Qwhere it is useful?

It is applicable at the place where LHS and RHS, both have same width.

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ARRAYS

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Agenda

Packed arrays

Un-packed arrays

Fixed size arrays Dynamic size arrays

Associative arrays

Array manipulating methods

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Arrays

Unpacked arrays : Each element requirededicated amount of space.

Ex. Logic [3:0] abc [4];

-> Each element of abc occupies whole 32 bitspace to store 3:0.

Packed arrays : It is treated as vector.

Ex. Logic [3:0][3:0] abc;-> Each element of abc occupies only 16 bits of

space as a whole.

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Mix of packed and un-packed arrays :

logic [3:0][3:1] abc[100];

Q : What is the width of abc[55][2]?

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Arrays

Dynamic size array : Size of the array is not known at compile time.

Ex. Int abc [];

To allocate the memory,

abc = new[100];

This allocates memory of 100 integers to abc.

Now, to copy one array to another.

Int abc[];

Int pqr[];

Abc = new[100];

Pqr = new[200] (abc);

First 100 elements of pqr is same as abc.

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Arrays

Dynamic array methods.

-> newTo allocate the memory, which is

described in previous slide.-> sizeReturns size of the array.

$display(Size = %0d,abc.size());

-> DeleteDelete the whole array.abc.delete();

$display(Size = %0d,abc.size()); // Prints 0.

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Arrays

Associative arrays : Used at the place where size of the array is not knownat run time.

data_type [index];

data_type can be any native/user defined data type

index can be *, class name, native data type.

Ex. Int abc [string];

logic [31:0] abc [myClass]; //myClass is name of the class.

byte abc[*]; //Index can be any thing.

Ex. Int abc[*];abc*2b3+ = 1;

abc*16hFFFF+ = 2;

Ex. Int abc [string];

abc*Hello+ = 1;

abc*World+ = 5;

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Arrays

Associative array methods :

-> num()Returns no. of elements array holds.

-> delete(index)if index is specified then delete the specified elements otherwise deletes entire

array.

-> exists(index)Return 1 if element exist at the specified index else 0.

string index = hello;

if(abc.exists(index))

abc[index]++;

-> first(ref index)returns index of the first element of the array. 0 if array is empty else 1.

->last(ref index)returns index of the last element of the array. 0 if array is empty else 1.

-> next(ref index)returns index of the next element of the array. This is with respect to the

first() or last() used before.

-> prev(ref index)return index of the prev element of the array. This is with respect to the

first() or last() used before.

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Arrays

Associative array example :int asssoc_arr*string+ = Peter:20, Sam:30, Mary:40-;

string index,s;

$display(Num : %0d,assoc_arr.num());

index = assoc_arr.first();

for(int i=0;i


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QUEUE

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Queue

What is Queue? - A queue is a variable-size,ordered collection of homogeneous elements.

Ex. Int int_q[$];

Queue can be bounded as well as un-bounded.

Int_q is un-bounded.

Int int_q[$:255] is a bounded queue, which canhold 256 integers.

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Queue

Queue methods

-> sizeReturns no. of elements queue holds.

-> insert(index, item)insert item at the specified index.

-> delete(index)delete the element from the specified index. Size becomes

size-1.-> pop_front()Fetch the element from front.

-> pop_back()Fetch the element from last.

-> push_front()Insert the element at front.

-> push_back()insert element at last.

When you PUSH, element is inserted and size is incremented by 1.

When you POP, element is removed from queue and size is decremented by

1.

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Queue

Queue Example.

Int int_q[$];

task write(int element);

int_q.push_back(element);

Endtask

task read(output int element);

element = int_q.pop_front();

Endtask

Task delete_q();

int_q = {};

endtask

Task size_q();

$display(Size of the Queue is :%0d,int_q.size());

endtask

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Assignment :

Create a data class which has following fields.- typedef enum {untagged=0, singletagged, doubletagged} tagged

- typedef enum {Eth, ipv4, tcp} pkt;

- 8 bits preamble which has fixed pattern 8b10101010- 48 bits Destination Address

- 48 bits Source Address

- tagged tag

- bit [31:0] pktTag[]

- int length- bit [7:0] data[]

Name this file as Packet.sv.

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Process control

fork..join

fork..join_any

fork..join_none

disable

disable fork

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Process Control

fork..join

fork

begin

write(push_data);end

begin

read(element);

endjoin

$display(Both threads finished.);

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Process Control

fork..join_any

fork

begin


begin

#20;

endjoin_any

$display(Out of fork...join_any);

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Process Control

fork..join_none

fork

begin


begin

wait(flag == 1);

endjoin_none

$display(Out of fork...join_none);

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Process Control

disable

fork

begin : write_t

write(push_data);

disable read_t;end : write_t

begin : read_t

read(element);

disable write_t;

end : read_tjoin_any

$display(Both threads finished.);

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Process Control

disable fork

fork

begin


begin

#20;

endjoin_any

disable fork;

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Randomization

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Randomization

Why Randomization ?

Random generation of stimulus

Random setting of parameters

Hard-to-reach corner cases can be reached

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Randomization

Two types of random variable.

- rand

- randc

Ex. rand logic [3:0] addr;

randc logic [3:0] vector;

What is the difference between rand and randc?

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Randomization

Class A;

rand bit [3:0] addr;

constraint addr_c {

addr


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Setting membership.what if you want addr value tobe any of either 3 or 5 or 7 or between 10 to 12.

Class A;


constraint addr_c {

addr inside {3,5,7,[10:12]};}

endclass

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Distribution constraintwhat if user wants to give higherweight to particular value?

class A;


constraint addr_c {

addr dist {3 := 1, 5 := 2, 7:= 5};

}

endclass

What does this mean?

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Implication Constraints

class A;


rand bit flag;

constraint addr_c {

(flag == 1) -> addr inside {[1:5],[10:12]};

}

endclass

Note : It is bi-directional constraint.

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If.else constraint

class A;


rand bit flag;

constraint addr_c {if(flag == 1)

addr == 5;

else

addr == 14;

}

endclass

Note : It is bi-directional constraint.

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Iterative constraint

class A;

rand bit [3:0] addr[5];

constraint addr_c {foreach(addr[i])

addr[i] dist {1 := 1, 2 := 1, 3 := 1};

}

endclass

Multi-dimention arrays can be constrained like this.

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Variable ordering

class A;


rand bit flag;

constraint addr_c {

(flag == 1) -> (addr == 14);

solve flag before addr;}

endclass

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Guard Constraint

class A;

rand bit flagA, flagB;


constraint addr_c {

((flagA == 1) && (flagB == 0)) -> addr = 10;

}

endclass

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Q : How to generate constraint random value?

Using randomize method.

class A;


constraint addr_c {addr inside {2,3,4};

}

endclass

A a = new;

a.randomize();

$display(addr = %h,a.addr);

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pre_randomize/post_randomize

When you call randomize, pre_randomize iscalled before it and post_randomize is called

after it.

pre_randomize is used for pre-processingpurpose.

post_randomize is used for post_processing ofthe variables.

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Enabling/Disabling randomness of the random variable using rand_mode.


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class A;


rand bit flag;

constraint addr_c {

}

endclass

A a = new;

// Turning off random mode of all variables of A.a.rand_mode(0);

// Turning on rand_mode.

a.rand_mode(1);

// Turning off random mode of particular random variable.

a.addr.rand_mode(0);

By default all variables random mode is ON.

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Enabling/Disabling constraint mode.


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class A;

rand bit [3:0] addr

constraint addr_c {

..

}

endclass

A a = new;

a.addr_c.constraint_mode(0);

a.randomize();

a.addr_c.constraint_mode(1);

By default all constraint blocks are enabled.

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$urandomreturns 32 bit unsigned number.

$urandom_range(maxval, minval)returnsany value between [minval, maxval].

bit [63:0] addr = {$urandom,$urandom};

int addr = $urandom_range(0,23);

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Packet structure is as below.


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Packet structure is as below.

Preamble -> destAddr -> srcAddr -> No. of tags-> Length -> Data

Pack the packet in data in Packet.sv insidepost_randomize().

Define one more function [not task] asunpack() in Packet.sv to unpack the packet

into fields, whose input is dynamic array and itreturns instance of Packet.

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Class A;rand logic [3:0] addr;


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rand logic [3:0] addr;

constraint addr_c {

addr 12;

}

Endclass

B b1;b1 = new;

b1.randomize();

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MAILBOX

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Mailbox

A mailbox is a communication mechanism that allows messages to be exchangedbetween processes. Data can be sent to a mailbox by one process and retrieved byanother.

mailbox mbxTx;

Supports following methods :new(int bound = 0)creating unbounded mailbox.

numreturns no. of elements hold.

put(msg)put msg into mailbox.

try_put(msg)used for bounded mailboxes. Rturns 1 if msg is put successfully else 0.

get(ref msg)fetch msg from mailbox. Remove the msg.

try_get(ref msg)returns 1 if there is a msg else 0. Remove the msg.peek(ref msg)get the element without removing the msg.

try_peek(ref msg)returns 1 if the if the msg available else 0. Do not remove themsg.

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Fifo with flow control

passes data between two processes

put()stimgen calls put() to pass data to bfm

get()bfm calls get() to retrieve data from stimgen.Get is the blocking statement. Put is the blocking statement too for the

bounded mailboxes.

mailbox

stimgen bfm

put() get()

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Class stimgen;Packet pkt;

ilb b


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mailbox mbxGen;

function new();

pkt = new;

mbxGen = new;endfunction

task run;

pkt.randomize();

mbxGen.put(pkt);

endtask

Endclass

Class bfm;

Packet pktbfm;

mailbox mbxBfm;

function new();

mbxBfm = new;

endfunction

task run;

mbxBfm.get(pktbfm);

endtask 73


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SEMAPHORE

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Semaphore

A semaphore is a bucket. When a semaphore is allocated, a bucket thatcontains a fixed number of keys is created. Processes using semaphoresmust first procure a key from the bucket before they can continue toexecute.

semaphore smTx;

Following methods are supported.

new(int keyCount = 0)create a semaphore. Provide integral no. ofkeyCount.

put(int keyCount = 1)returns keyCount to semaphore.get(int keyCount = 1)get keyCount from semaphore. Blocking statement.

try_get(int keyCount = 1)get the keyCount without blocking. Return 1 ifsuccessful else 0.

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Used for Synchronization

Variable number of keys can be put and removed

controlled access to a shared object

think of two people wanting to drive the same carthe key is a semaphore

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Event

Event is mainly used for the synchronization purpose.

event ev;

fork

begin

#10;-> ev;

$display(Event triggered);

end

begin

@(ev); // Blocking statement. Keeps waiting here..

$display(Event triggered received at %t,$time);end

join

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INTERFACE

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Interface is bunch of signals. Used to connect RTL and Testbench.

interface bus_A (input bit clk);


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logic [31:0] addr;

logic [31:0] data;

logic wr_rd_n;

logic enable;

endinterface

module mod_Bus( bit clk, logic [31:0] addr, logic [31:0] data, logic wr_rd_n, logic enable);

.

endmodule

module TOP;

bus_A busA(clk);bit clk = 0;

// Clock generation logic.

mod_bus(.clk (clk),

.addr (busA.addr),

.data (busA.data),

.wr_rd_n (busA.wr_rd_n),

.enable (busA.enable)); // interface connected to RTL.

endmodule

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Modport


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interface i2;

wire a, b, c, d;

modport master (input a, b, output c, d);modport slave (output a, b, input c, d);

endinterface

module m (i2.master i);

...

endmodule

module s (i2.slave i);

...

endmodule

module top;

i2 i();

m u1(.i(i));

s u2(.i(i));

endmodule82


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interface bus_A (input bit clk);

logic [31:0] addr;


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logic [31:0] addr;

logic [31:0] data;

logic wr_rd_n;

logic enable;

clocking wr_cb @(posedge clk);

default output #1ns;

output addr;

output data;

output wr_rd_n;

output enable;endclocking

clocking rd_cb @(posedge clk);

default input #1ns output #1ns;

output addr;

input data;

output wr_rd_n;

output enable;

endclocking

endinterface

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Separate skews for input and output signals.

clocking rd_cb @(posedge clk);

output #2ns addr;

input #1ns data;

.

endclocking

Q : what if user dont specify the skew?

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Sampling and driving a signal using interface/clocking block.

-> Sync signals drive are processed as non-blockingassignment.

busA.wr_cb.addr Sampling a sync signals value depends upon the clock andskew.

addr = busA.addr; gives you a value at the time ofsampling where as

data = busA.rd_cb.dat will give you sync value of data.

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Vi t l I t f


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Virtual Interface

Virtual interface is pointer to the interface defined in the top module.

module top;

bus_A busA;

..

endmodule

class Driver;

virtual interface bus_A busA;

endclass

All signal drive/sampling should happen through virtual interface.

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Program Block

program test(interface bus_A);


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PktEnv env; //PktEnv is a class.

initial begin

env = new(bus_A);

env.build();

env.connect();

env.driver.no_of_pkts = 1; // driver is instance of the class Driver inside PktEnv.

fork

begin

env.start();

end

begin

#100us;

$display(ERROR : Timeout occurs);

$finish;

end

join_any

disable fork;

env.report();

$display(Test Finished);

$finish;

end

endprogram88

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Assignment

Draw verification env. Develop a class driver.sv and receiver.sv, Packet_intf.sv.

Driver.sv randomizes packet and drives out viainterface also send randomized packet to scoreboard.

Receiver.sv receives the packet driven by Driver viainterface. Display the received packet.

Packet_intf.sv define the interface signals, clockingblock.

Scoreboard.sv which does the data comparison. [Willyou guys be able to do this????]

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COVERAGE

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Coverpoint

logic [3:0] addr;

cover_addr : coverpoint addr;

This covers all 16 cases.

Covergroup

covergroup g1 @(posedge clk);

cover_addr : coverpoint addr;

endgroup

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Defining bins of coverpoint.

bit [9:0] v_a;

covergroup cg @(posedge clk);

coverpoint v_a

{bins a = { [0:63],65 };

bins b[] = { [127:150],[148:191] }; // note overlapping values

bins c[] = { 200,201,202 };

bins d = { [1000:$] };

bins others[] = default;

}

endgroup

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Transition coverage

bit [4:1] v_a;


coverpoint v_a{

bins sa = (4 => 5 => 6);

bins allother = default sequence ;

}endgroup

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bit [4:1] v_a;covergroup cg @(posedge clk);

coverpoint v_a

{

bins sa = (4 => 5 => 6), ([7:9],10=>11,12);

bins sb[] = (4=> 5 => 6), ([7:9],10=>11,12);

bins allother = default sequence ;

}endgroup

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Wildcard bins

wildcard bins g12_16 = { 4b11?? };

Wildcard transition bins

wildcard bins T0_3 = (2b0x => 2b1x);

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Ignore bins

covergroup cg23;

coverpoint a

{

ignore_bins ignore_vals = {7,8};

ignore_bins ignore_trans = (1=>3=>5);

}endgroup

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Illegal bins

covergroup cg3;

coverpoint b

{

illegal_bins bad_vals = {1,2,3};illegal_bins bad_trans = (4=>5=>6);

}

endgroup

Whenever illegal values are encountered run time thenERROR will be flagged by Simulator.

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Example :

bit [31:0] a_var;

bit [3:0] b_var;

covergroup cov3 @(posedge clk);A: coverpoint a_var { bins yy[] = { [0:9] }; }

CC: cross b_var, A;

endgroup

Q : How many possible cases for a_var, b_var and CC?

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bit [7:0] v_a, v_b;



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g p g (p g )

a: coverpoint v_a

{

bins a1 = { [0:63] };

bins a2 = { [64:127] };bins a3 = { [128:191] };

bins a4 = { [192:255] };

}

b: coverpoint v_b

{

bins b1 = {0};bins b2 = { [1:84] };

bins b3 = { [85:169] };

bins b4 = { [170:255] };

}

c : cross v_a, v_b

{

bins c1 = ! binsof(a) intersect {[100:200]};

bins c2 = binsof(a.a2) || binsof(b.b2);

bins c3 = binsof(a.a1) && binsof(b.b4);

}

endgroup102

Ignore Cross Productcovergroup yy;


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cross a, b

{

ignore_bins foo = binsof(a) intersect { 5, [1:3] };}

endgroup

Illegal Cross Product

covergroup zz(int bad);

cross x, y

{illegal_bins foo = binsof(y) intersect {bad};

}

endgroup103


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AssignmentDevelop PktCov.sv for Ethernet packet frame. Listdown all the required coverage points, bins.

Trigger them from monitor/receiver to samplethe coverage using an event(s).

Take instance of PktCov inside Monitor/Receiver,pass values to PktCov and trigger an event tosample the value.

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1. Now, we have Packet.sv, Driver.sv, Monitor.sv [Receiver.sv],Scoreboard.sv, PktCov.sv.

2. Develop PktEnv class into PktEnv.sv. Take instance of Driver, Monitor,Scoreboard, PktCov. Also take instance of Mailbox which is of typePacket.

3. Define following methods into Env. New, Build, connect, start, report.

4. Inside new, assign interface to the local virtual interface instance, whichis passed from testcase.

5. Inside Build, create all the instances.

6. Inside connect, pass scoreboard to Driver, PktCov to Monitor/Receiver,Mailbox between Driver and Scoreboard.

7. In Start, call run of Driver, Monitor, Scoreboard.

8. Develop a test case using program block. Pass instance of interface inargument. Call all the env threads from testcase [Only Me and Rutul willDevelop this].

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RTL Driver

Class

SeqcrReceiver

Scoreboard Model

Introduction to SystemVerilog and Verification

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