Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008 CHAPTER 10.

Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008

CH

AP

TE

R 1

0


Master Figure


Fig. 10.1

WLSOP

Build-up wiring and embedded components

Interconnections &.

Assembly

3D stacking &Silicon through Vias

Lead-free solders/UBM/Barriers

Copper Bumps

Through Silicon Vias

Silicon Thinning

Nano interconnections

Wiringand Redistribution

Stress relief structures

Test and burn-in

Self-assembly

Embedded components Wafer to Wafer Bonding


Rel

ativ

e C

omp

onen

ts/c

m2

1980 1990 2000

BGA

ConventionalCSP

Wafer Level CSP

1970 20101960

Compliant WLP

Nano WLP (CNT, Cu)

QFP

Flip Chip to Board with Underfill

Flip Chip on Board

SIPI/O

per cm

2

100

1,000

10,000

1000,000

DIP

First Flip Chip (IBM)

Cu-Cu

Stress BuffersRedistribution

WLP

WLS

IP

WLS

OP

100,000

Rel

ativ

e C

omp

onen

ts/c

m2

1980 1990 2000

BGABGA

ConventionalCSP

Wafer Level CSP

1970 20101960

Compliant WLP

Nano WLP (CNT, Cu)

QFP

Flip Chip to Board with Underfill

Flip Chip on Board

SIPI/O

per cm

2

100

1,000

10,000

1000,000

DIPDIP

First Flip Chip (IBM)First Flip Chip (IBM)

Cu-Cu

Stress BuffersRedistribution

WLP

WLS

IP

WLS

OP

100,000

Fig. 10.2


Fig. 10.3

Wafer Level Package

DicingDicing

WaferWafer

WaferWafer Packaged ICPackaged IC

Packaged ICPackaged ICPackagingPackagingPackaging

Conventional Packaging and Assembly

WLP Potential

• 10 – 50 x Size Reduction

• 10 x Cost Reduction

• Better Electrical Performance

• Acceptable Mechanical Performance

(B)

(A)


Figs. 10.4 a, b

(a) (b)


Fig. 10.5


Cu Surface Treatment CVD Dielectric

Via Lithography and Etch

Line Lithography and Etch, TaN barrier

Cu CMP

TaN Clean

Post CMP Clean

Cu Electrofill and Anneal

PVD Cu Seed

Fig. 10.6


Fig. 10.7


Fig. 10.8

Transmission line

Resistor

Capacitor

Double layer inductor coil

Single layer coil

SILICON

BEOL

SILICON

BEOL

Transmission line

Resistor

Capacitor

Double layer inductor coil

Single layer coil

SILICON

BEOL

SILICON

BEOL


Fig. 10.9


Fig. 10.10


Fig. 10.11


Fig. 10.12


Fig. 10.13


Fig. 10.14


Fig. 10.15R

esis

tanc

e (m

),

Cap

acita

nce

(fF

), In

duct

ance

(pH

)


Fig. 10.16

Lead-Free with Underfill

Compliant Interconnection

Copper Pillar Nano

Interconnection

(Cu,CNT)

50-100 micron pitch>100 micron pitch <1micron pitch

Bonding layer

Cu-Cu TSV Bonding

1-20 micron pitch

Lead-Free with Underfill

Compliant Interconnection

Copper Pillar Nano

Interconnection

(Cu,CNT)

50-100 micron pitch>100 micron pitch <1micron pitch

Bonding layer

Cu-Cu TSV Bonding

1-20 micron pitch


Fig. 10.17


Fig. 10.18


Fig. 10.19


Fig. 10.20

Substrate

Si Chip

Substrate

Si Chip

Critical failure site - strain concentration

Failure sites – no strain concentration


Fig. 10.21


Fig. 10.22


Fig. 10.23


Fig. 10.24


Fig. 10.25


Fig. 10.26

Stress Compensation Layer


Fig. 10.27


Fig. 10.28


Fig. 10.29

0

5

10

15

20

25

30

Cr/thin Cu Al/Ni(V)/Cu Thick Cu Thick Ni Cu/Thick Ni

UBM

Cu

rren

t C

row

din

g R

atio


Figs. 10.30 a, b, c

(a) (b)

(c)


Fig. 31


Fig. 10.32

Current Density

Additives

Conc.of noble nutal

% A

g or

% C

u in

side

Sn


Fig 10.33

Current crowding at solder

Less current crowding at solder

Passivation

UBM

Al trace


Fig. 10.34


Fig. 10.35

STUD BUMPIN

G COST

0

50

100

150,000 300,000

BUMPS PER WAFER

PR

ICE

PE

R B

UM

PE

D W

AF

ER

A

B

C

A:Electroless Ni- Immersion Au

B:Solder Plating

C:Gold Plating


Figs. 10.36 a, b

(a)

(b)


Fig. 10.37


Fig. 10.38


Fig. 10.39


Fig. 10.40


Fig. 10.41

10-6

10-5

10-4

10-3

10 100

– Measure of stress intensity at crack tip (MPa √m)

Cra

ck g

row

thra

te (

mm

/cyc

le)

Nano Cu

Micro Cu

10-6

10-5

10-4

10-3

10 100

– Measure of stress intensity at crack tip (MPa √m)

Cra

ck g

row

thra

te (

mm

/cyc

le)

Nano Cu

Micro Cu


Fig. 10.42

0

150

300

450

0.5 x104

umber of Cycles

Str

ess

Am

plitu

de

(MP

a)

Nano Cu

Micro Cu

2.0x1071.0 x 106

Finegrain Cu

0

150

300

450

0.5 x104

umber of Cycles

Str

ess

Am

plitu

de

(MP

a)

Nano Cu

Micro Cu

2.0x1071.0 x 106

Finegrain Cu


Fig. 10.43

Anisotropic Conductive Adhesive Isotropic Conductive AdhesiveAnisotropic Conductive Adhesive Isotropic Conductive Adhesive


Fig. 10.44


Fig. 10.45


Fig. 10.46


Fig. 10.47


Si

CNT

Substrate

Solder

UBM

Substrate

Substrate

Flip and reflow

Remove Si for CNT transfer

Sputter metal

Si

Substrate

Fig. 10.48


Fig. 10.49


Fig. 10.50

WLSOP for Wafer Stacking

Wafer ThinningThrough Silicon Vias Wafer BondingEmbedded Thin Si

Actives


Fig. 10.51


Fig. 10.52


Fig 10.53


Fig. 10.54


Fig. 10.55


Fig. 10.56

Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008 CHAPTER 10.

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Transcript of Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008 CHAPTER 10.