Introduction to Structured VLSI Design - LTH Preparation Read the lab manual carefully to understand...
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Transcript of Introduction to Structured VLSI Design - LTH Preparation Read the lab manual carefully to understand...
![Page 2: Introduction to Structured VLSI Design - LTH Preparation Read the lab manual carefully to understand all the details. Read the checklist file and prepare the requirements of Lab 3.](https://reader036.fdocuments.in/reader036/viewer/2022081521/5acf682d7f8b9ae2138c7c81/html5/thumbnails/2.jpg)
Introduction
Arithmetic Logic Unit (ALU) is the fundamentalbuilding block of the CPU in a computer.
“Heart” of a processor
Each processor needs at least one ALU
ALU is a digital circuit that performs:
Arithmetic operations (Add, Sub, . . .)
Logical operations (AND, OR, NOT)
2 Lund University / EITF35/ 2017
![Page 3: Introduction to Structured VLSI Design - LTH Preparation Read the lab manual carefully to understand all the details. Read the checklist file and prepare the requirements of Lab 3.](https://reader036.fdocuments.in/reader036/viewer/2022081521/5acf682d7f8b9ae2138c7c81/html5/thumbnails/3.jpg)
Objective of Lab3
Design a simple ALU to perform the followingfunctions for its inputs (i.e. A, B):
Addition: (A + B)
Subtraction: (A - B)
Modulo 3: (A mod 3)
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It should support:
Sign/unsigned operations
Overflow detection
![Page 4: Introduction to Structured VLSI Design - LTH Preparation Read the lab manual carefully to understand all the details. Read the checklist file and prepare the requirements of Lab 3.](https://reader036.fdocuments.in/reader036/viewer/2022081521/5acf682d7f8b9ae2138c7c81/html5/thumbnails/4.jpg)
Inputs/Outputs of Design
Inputs:
8 bits for input operand
DIP Switches (SW7..SW0)
3 bits for control signals
Push buttons (BTNL, BTNC, CPU Reset)
50 MHz Clock
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Outputs:
7-segment display
![Page 5: Introduction to Structured VLSI Design - LTH Preparation Read the lab manual carefully to understand all the details. Read the checklist file and prepare the requirements of Lab 3.](https://reader036.fdocuments.in/reader036/viewer/2022081521/5acf682d7f8b9ae2138c7c81/html5/thumbnails/5.jpg)
Top Module
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ALU_top.vhd
Generate a proper .xdc file
based on the I/Os.
Instantiate the Debouncer
block in the top design.
![Page 6: Introduction to Structured VLSI Design - LTH Preparation Read the lab manual carefully to understand all the details. Read the checklist file and prepare the requirements of Lab 3.](https://reader036.fdocuments.in/reader036/viewer/2022081521/5acf682d7f8b9ae2138c7c81/html5/thumbnails/6.jpg)
ALU Architecture
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ALU_ctrl.vhd
![Page 7: Introduction to Structured VLSI Design - LTH Preparation Read the lab manual carefully to understand all the details. Read the checklist file and prepare the requirements of Lab 3.](https://reader036.fdocuments.in/reader036/viewer/2022081521/5acf682d7f8b9ae2138c7c81/html5/thumbnails/7.jpg)
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FN [3 : 0] Operation
0000 Input A
0001 Input B
0010 Unsigned (A + B)
0011 Unsigned (A - B)
0100 Unsigned (A) mod 3
1010 Signed (A + B)
1011 Signed (A - B)
1100 Signed (A) mod 3
ALU Controller
![Page 8: Introduction to Structured VLSI Design - LTH Preparation Read the lab manual carefully to understand all the details. Read the checklist file and prepare the requirements of Lab 3.](https://reader036.fdocuments.in/reader036/viewer/2022081521/5acf682d7f8b9ae2138c7c81/html5/thumbnails/8.jpg)
ALU Architecture
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binary2BCD.vhd
To do Arithmetic Operations
ALU.vhd
Separate Seq. & Comb. Logic
regUpdate.vhd
Similar Blocks in Lab 2
7SegDriver.vhd
![Page 9: Introduction to Structured VLSI Design - LTH Preparation Read the lab manual carefully to understand all the details. Read the checklist file and prepare the requirements of Lab 3.](https://reader036.fdocuments.in/reader036/viewer/2022081521/5acf682d7f8b9ae2138c7c81/html5/thumbnails/9.jpg)
Lab Preparation
Read the lab manual carefully to understand all the details.
Read the checklist file and prepare the requirements of Lab 3.
Read the Modulo3.pdf paper to design the modulo 3 operation.
Design a hardware-friendly architecture for Binary to BCD
conversion.
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![Page 10: Introduction to Structured VLSI Design - LTH Preparation Read the lab manual carefully to understand all the details. Read the checklist file and prepare the requirements of Lab 3.](https://reader036.fdocuments.in/reader036/viewer/2022081521/5acf682d7f8b9ae2138c7c81/html5/thumbnails/10.jpg)
Some Notes
Think about each block and its functionality before coding!
Start early!
Do the simulation as much as possible for your design and
sub blocks.
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