Introduction to PCI System Architecture. Contents: Introduction to PCI System PCI Bus Arbitration...
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Transcript of Introduction to PCI System Architecture. Contents: Introduction to PCI System PCI Bus Arbitration...
Introduction to PCI System Architecture
Introduction to PCI System
Direct-Connect Approach(VESA)
CPU Cache
Main memory
Local Bus Memory Bus
Expansion Bridge
ExpansionConnectors
X-Bus Buffer
I/O Device I/O Device I/O Device
Local Bus Design Constraint:
1. Redesign is necessary for next generation processor.
2. Only one local device is permitted.
3. Design of local bus inter -face is difficult.
4. Transfer with one device is not permitted while the local bus is involved in a transfer with another device.
Expansion Bus
X-Bus
Local Bus Device
CPU CacheLocal Bus Memory Bus
Expansion Bridge
X-Bus Buffer
I/O Device I/O Device
Expansion Bus
X-Bus
Bus Buffer
I/O Device
I/ODevice
I/ODevice
I/ODevice
Buffered Approach(VESA)
Buffered Local Bus
A maximum of three local bus devices can be placed on the buffered local bus.
CPUHost/PCICache/Bridge
Workstation Approach(PCI)
Memory BusCPU Local Bus
Main Memory
Video Memory
Audio PeripheralMotion VideoPeripheral
SCSI Host Bus Adapter
SC
SI B
US
Disk
TapeCD ROM
Expansion Bus
Video Frame Buffer
Graphics Adapter
Expansion BusBridge
LANAdapter
PCI Bus
BusMaster
I/OSlave
MemorySlave
LAN
Transfer Rate Comparison:
Bus Bus Frequency Transfer Transfer Rate
ISA 8.33 MHz 2 byte / 2 clock 8.33 MB/s
EISA 8.33 MHz 4 byte / 1 clock 33 MB/s
( Burst Mode)
VESA 33 MHz 4 byte / 1 clock 132 MB/s
( Read, Burst )
4 byte / 2 clock 66 MB/s
( Write, Burst )
PCI 33 MHz 4 byte / 1 clock 132 MB/s
8 byte / 1 clock 264 MB/s
66 MHz 4 byte / 1 clock 264 MB/s
8 byte / 1 clock 528 MB/s
( Burst Mode )
• PCI: Peripheral Component Interconnect
• Major PCI Revision 2.1 Features
Processor Independence
Support for up to 256 PCI functions per PCI bus
Low power consumption ( Draw as little current as possible )
Burst used for all read and write transfers
Supports 66 MHz operation, 64bit bus width
Fast access ( 60ns at bus speed 33 MHz )
Concurrent bus operation
Bus master support
Hidden bus arbitration
Low pin count ( Initiator:49pins, Target:47 pins )
Transaction integrity check( Parity check)
Three address spaces ( Memory, I/O, Configuration )
Auto configuration( Configuration register )
Software Transparency
AD[31:00] AD[63:32]
C/BE[3:0]# C/BE[7:4]#
PAR
FRAM#
TRDY#IRDY#STOP#DEVSEL#IDSEL
SERR#
REQ#GNT#
CLKRST#
PAR64REQ64#ACK64#
LOCK#
INTA#INTB#INTC#INTD#
TDI
PCICOMPLIANT DEVICE
PERR#
PCI-Compliant Device Signals
TDOTCKTMSTRST#
CLKRUN#
Address/Dataand Command
Interface Control
Error Reporting
Arbitration
System
Required Signals Optional Signals
64-bit Extension
Atomic Access
Interrupt Request
Clock Control
SDONSnoop Result
JTAG
For Slave only
For Master only
SBO#
PCI Bus Arbitration
Initiator/ Target
Initiator ( Master ): The device that initiates a transfer
Target ( Slave ): The device that currently addressed by the initiator for
the purpose of performing a data transfer
PCI Device
PCI Device
PCI Device
PCI Device
PCI Arbiter
REQ0# REQ1# REQ2# REQ3#
GNT0#GNT1# GNT2# GNT3#
PCI Device
MASTER
SLAVE
Address, Command/
Data, Byte Enables/
Parity
DRAM
SLAVE
Bridge
SLAVE
PCI Bus Arbitration Algorithm
First Group
Second Group
Master A
Master B
Master X
Master Y Master Z
A B X A B Y A B Z A B X
• Fairness ( fixed, rotational )
• Bus Parking( on specified master, on last master that acquired the bus )
• Hidden Bus Arbitration( REQ#, GNT#)
• LT ( Latency Timer ): The minimum amount of time that the bus master is
permitted to retain ownership of the bus
AD
REQA#
REQB#
GNTA#
GNTB#
FRAME#
( Master B has higher priority than Master A)
IRDY#
TRDY#
Example of PCI Bus Arbitration Between Two Masters
1 2 3 4 5 6 8
ADDRESS DATA
9 10 11 127
DATA DATA DATAADDRESS DATAADDRESS
A B A
( Master A -> Arbiter )
( Master B -> Arbiter )
( Arbiter -> Master A )
( Arbiter -> Master B )
( Master -> Target )
( Target -> Master )
( Master -> Target )
( Master <-> Target )
CLK
LT not expired
REQ#-
GNT#
DEVSEL#
FRAME#
1 2 3 4 5 6 87CLK
IRDY#
TRDY#
AD ADDRESS DATA ADDRESS DATA
Arbitration for Fast Back-To-Back Accesses
Delayed Transaction
Delayed Transaction
Request Phase:
Completion Phase:
Target latches the request and issues retry
Transaction completes on the target bus
Master
PIIX4
ISA Device
1. Address, Command, Byte Enables latched by PIIX4
2. Retry issued to MTXC
( Request Phase )
3. Requested data fetched in buffer ( Completion Phase )
Target
MTXC
4. Master Retries the transaction with the
same address, command, data
OR no Retry within 215 clocks Discard the data
Target cannot respond within 16 clocks:
Commands That can Use Delayed Transactions
Interrupt Acknowledge I/O Read I/O Write
Memory Read
Memory Read Line
Memory Read Multiple
Configuration Read
Configuration Write
The PCI Commands
C/BE[3::0]# Command Type
0000 Interrupt Acknowledge0001 Special Cycle0010 I/O Read0011 I/O Write0100 Reserved0101 Reserved0110 Memory Read0111 Memory Write1000 Reserved1001 Reserved1010 Configuration Read1011 Configuration Write1100 Memory Read Multiple1101 Dual Address Cycle 1110 Memory Read Line1111 Memory Write and Invalidate
PCI Command Types
C/BE#[3:0] is used to indicate the command or transaction type during the address phase
VECTOR
INT ACK CMD Byte Enables
CLK
FRAME #
AD
C/BE #
IRDY #
TRDY #
1 2 3 4 5
DEVSEL #
GNT #
PCI Interrupt Acknowledge Transaction
Stable Pattern
( Host Bridge -> INT Controller )
( Host Bridge < -> INT Controller )
( Host Bridge -> INT Controller )
( INT Controller-> Host Bridge )
GNT#
DEVSEL#
FRAME#
CLK
IRDY#
TRDY#
AD[31:0]
1 2 3 4 5 6 87
Stable Pattern
Message
C/BE#[3:0] Special Cmd
Byte Enables
The Special Cycle Transaction( Halt / Shut Down)
Terminated with Master Abort
• For an initiator to
broad- cast a message
to one or more targets.
• Message type on AD[15:0] • Message-dependent data field on AD[31:16]
• Byte Enable on C/BE#[3:0] 7 clocks
Message Code Message Type
( on AD[15:0]
0000h Shut Down
0001h Halt
0002h x86-specific
message
0003h-ffffh Reserved
The Read and Write Transfers
Read Transaction( 33.33 Mb/s )
CLK1 2 3 4 5 6 7 8 9
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
ADDRESS DATA-1 DATA-2 DATA-3
BUS CMD
ADDRESS PHASE
DATA PHASE
DATA PHASE
DATA PHASE
BYTE ENABLES BYTE ENABLES BYTE ENABLES
Wait state for bus ownership
One more clock before initiator ready to receive data
Some time is needed for fetching data
Avoid bus contention
GNT#
DEVSEL#
FRAME#
CLK
IRDY#
TRDY#
AD
1 2 3 4 5 6 87
Address Data1
C/BE# BUSCMD
Byte Enables
Data2 Data3
ByteEnables
ByteEnables
Optimized Read Transaction
( 132 Mb/s)
Burst Transfer:
1. If target memory is
cacheable.
2. If target memory is
prefetchable
CLK1 2 3 4 5 6 7 8 9
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
ADDRESS DATA-1 DATA-2 DATA-3
BUS CMD BYTE ENABLESByte EN Byte EN
Write Transaction
( 44.44 Mb/s )
GNT#
DEVSEL#
FRAME#
CLK
IRDY#
TRDY#
AD
1 2 3 4 5 6 87
Address Data1
C/BE# BUSCMD
Data2 Data3
ByteEnables
ByteEnables
Optimized Write Transaction
( 132 Mb/s)
ByteEnables
Addressing
• Addressing Sequence During Memory Burst Linear ( or Sequential ) address mode
Cache Line wrap mode
AD1 AD0 Addressing Sequence
0 0 Linear
0 1 Reserved
1 0 Cacheline wrap
1 1 Reserved
• PCI I/O Addressing AD[31:2] : Target DW of I/O space
AD[1:0] : The Least-significant byte within the DW that the
initiator wishes to transfer with ( 00 = byte 0, 01 = byte 1 )
64 bit PCI Extension
REQ64#, ACK64#, PAR64, AD[64::32], C/BE[7::4]
1 2 3 4 5 6 7 8 9
ADDRESS
DATA-1 DATA-3 DATA-5
DATA-2 DATA-4 DATA-6
BUS CMD BE# ‘s
BE# ‘s
CLK
FRAME#
REQ64#
AD[31::00]
AD[63::32]
C/BE[3::0]#
C/BE[7::4]#
IRDY#
TRDY#
DEVSEL#
ACK64#
64-bit Read Request with 64-bit Transfer
64-bit Write Request with 32-bit Transfer
1 2 3 4 5 6 7 8 9
ADDRESS
DATA-1 DATA-3
DATA-2
BUS CMD BE# ‘s-1
CLK
FRAME#
REQ64#
AD[31::00]
AD[63::32]
C/BE[3::0]#
C/BE[7::4]#
IRDY#TRDY#
DEVSEL#
ACK64#
DATA-2
BE# ‘s-2 BE# ‘s-3
BE# ‘s-2
64-bit Dual Address Read Cycle
1 2 3 4 5 6 7 8
DUAL AD BE# [3::0]
CLK
FRAME#
IRDY#
TRDY#
LO-ADDR HI-ADDR DATA-1 DATA-3AD[31::00]
C/BE[3::0]# BUS CMD
AD[63::32]
C/BE[7::4]#
HI-ADDR DATA-2 DATA-4
BE# [7::4] BUS CMD
DEVSEL#
REQ64#
ACK64#
Premature Transaction Termination
Master Initiated TerminationMaster Initiated Termination
Reasons
Transaction completed normally ( Not premature transaction termination )
Initiator been preempted ( GNT# removed )
Preemption during timeslice by another bus master
Timeslice expiration followed by preemption
Master abort
No target respond to the address ( DEVSEL# not asserted)
No device resides at the address
Special cycle
Configuration accessing a non-existent target
GNT#
FRAME#
CLK
IRDY#
TRDY#
1 2 3 4 5 6 7
GNT#
FRAME#
CLK
IRDY#
TRDY#
Preempted
Internal LT time out sensed
Preempted
Time out sensed
Preemption
Example
Timer Expiration Example
DEVSEL#
FRAME#
CLK
IRDY#
TRDY#
1 2 3 4 5 6 87
Example of Master-abort on Single-Data Phase Transaction
Fast Medium Slow Bridge
Master Abort : Target doesn’t claim transaction
Target Initiated Termination( STOP# )
Disconnect
Target Initiated Termination( STOP# )
Disconnect
Target very slow to complete first data phase ( Greater than 16 PCI clocks )
Snoop hit on modified cache line
Resource busy
Memory target locked
Reasons Target slow to complete a data phase which is neither the first nor
the final data phase ( more than 8 PCI clocks )
Targets don’t support burst mode
Memory target doesn’t understand address sequence
Transfer cross over target’s address boundary
Burst memory transfer crosses cache line boundary
Retry Retry
Reasons
( if the target cannot permit any data to be transferred )
Broken Target
I/O addressing error
Address phase parity error
Master abort on other side of PCI-to-PCI bridge
Target Abort Target Abort
Reasons
( if the target detects fatal error )
DEVSEL#
FRAME#
CLK
IRDY#
TRDY#
1 2 3 4
Type A Disconnect
STOP#
Data Transfer
DEVSEL#
FRAME#
CLK
IRDY#
TRDY#
1 2 3 4
Type B Disconnect
STOP#
Data Transfer
TRDY# asserted, STOP# asserted,
DEVSEL# asserted, IRDY# deasserted
TRDY# asserted, STOP# asserted,
DEVSEL# asserted, IRDY# asserted
Know in advance that the next data transfer takes more than 8 PCI clock
DEVSEL#
FRAME#
CLK
IRDY#
TRDY#
1 2 3 4
Type C Disconnectwith IRDY# Asserted
STOP#
Data Transfer
DEVSEL#
FRAME#
CLK
IRDY#
TRDY#
1 2 3 4
Type C Disconnectwithout IRDY# Asserted
STOP#
Data Transfer
TRDY# deasserted, STOP# asserted
DEVSEL# asserted
Current data transfer takes more than 8 PCI clock
DEVSEL#
FRAME#
CLK
IRDY#
TRDY#
1 2 3 4
Retry ReceivedWith IRDY# Asserted
STOP#
DEVSEL#
FRAME#
CLK
IRDY#
TRDY#
1 2 3 4
Retry ReceivedWithout IRDY# Asserted
STOP#
No Data Transfer
No Data Transfer
TRDY# deasserted, STOP# asserted
DEVSEL# assertedOccurs in the first data phase
DEVSEL#
FRAME#
CLK
IRDY#
TRDY#
1 2 3 4
Target Abort Example
STOP#
Master’s response to target abort:
• Generates an interrupt to alert is related
device to check its status.
• Generates SERR#
TRDY# deasserted, STOP# asserted
DEVSEL# deasserted
Shared Resource Acquisition
Shared Resource Acquisition
• LOCK#
Usage : Perform read/modify/write of a memory
semaphore as an atomic series to avoid
Synchronization Problem.
Solutions:
Bus LOCK : Permissible but not preferred
Resource LOCK: Preferred
Starting an Exclusive Access( Establishing LOCK#)
1 2 3 4 5CLK
FRAME#
LOCK#
AD
IRDY#
TRDY#
DEVSEL#
ADDRESS DATA
GNT#
LOCK# Mechanism Availability: Do not assert REQ# if LOCK# is currently asserted. If FRAME# and LOCK# are deasserted, assert its REQ#. The master continue to monitor LOCK# while waiting for GNT#. If LOCK# is sampled asserted, the master deasserted its REQ#. When the master samples bus idle ( FRAME# & IRDY# deasserted) and LOCK# deasserted, it has acquisition of the bus and of the LOCK#.
( Master -> Target )
( Master -> Target )
( Master < -> Target )
( Master -> Target )
( Target -> Master )
( Target -> Master )
( Arbiter -> Target )
Accessing a Locked Agent : Retry
CLK
FRAME#
LOCK#
AD
IRDY#
TRDY#
STOP#
ADDRESS DATA
1 2 3 4 5
DEVSEL#
(driven low by master holding lock)
RetryGNT#
Continuing & Completing an Exclusive Access
CLK
FRAME#
LOCK#
AD
IRDY#
TRDY#
DEVSEL#
ADDRESS DATA
1 2 3 4 5
Continue
Release
GNT#
When Parity Error occurs:
Configuration status register : DETECTED PARITY ERROR
Configuration command register: PARITY ERROR RESPONSE
Assert PERR# Devices excluded from PERR# Requirement
Chipsets
Devices that don’t deal with OS/Application program or data
Error Detection and Handling
Parity on Read Transaction
TRDY#
DEVSEL#
FRAME#
CLK
PAR
PERR#
AD
1 2 3 4 5 6 87
Address 1st Data
C/BE# BUSCMD
3rd Data
2nd ByteEnables
3rd ByteEnables
1st ByteEnables
9
2nd Data
IRDY#
Add phase parity
1st Data parity 3rd Data Parity2nd Data
parity
1st phase PERR#
2nd phase PERR#
3rd phase PERR#earliest latest
Parity on Write Transaction
TRDY#
DEVSEL#
FRAME#
CLK
PAR
PERR#
AD
1 2 3 4 5 6 87
Address 1st Data
C/BE# BUSCMD
3rd Data
2nd ByteEnables 3rd Byte Enables1st Byte
Enables
9
2nd Data
IRDY#
Add phase parity
1st Data parity 3rd Data Parity2nd Data
parity
1st phase PERR#
2nd phase PERR#
3rd phase PERR#earliest latest
Configuration Related Issues
Configuration Address Space Format
Configuration Header Space
Device Specific Configuration
Registers
Byte Number
Dou
ble W
ord N
um
ber
00
1516
63
0123
Configuration Registers
00h
04h
08h
0Ch
10h
24h
28h
2Ch
30h
34h
38h
3Ch
0151631
BIST Cache LineSize
Base Address Registers
Cardbus CIS Pointer
Subsystem ID Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Reserved
Max_Lat Min_Gnt Interrupt PinInterrupt
Line
Type 0 Configuration Space Header
Status
Required configuration registers
Latency Timer
Device ID Vendor ID
Command
Revision IDClass Code
Header Type
Command Register Bit Assignment
Reserved
Fast Back-to-Back Enable
DEVSEL Timing
Data Parity Reported
Signaled Target Abort
Received Target Abort
Received Master Abort
5 06789 4
Status Register
5 3 2 1 0
Reserved
678910
Fast Back-to-Back Enable
SERR# Enable
Wait Cycle Control
Parity Error Response
Palette Snoop EnableMemory Write and Invalidate Enable
Special Cycle Monitoring
Enable Mastering
Memory Access Enable
4
I/O Access Enable
15
15 14 13 12 11 10
66MHz-Capable
UDF Supported
Signaled System Error
Detected Parity Error
Class Code Register
Class Code Sub-Class Code Prog I/F
o78151623
Basic function More specific device subclass
Device specific programming interface
Eg. 06h 01h 00h
Bridge device PCI/ISA bridge
Header Type Register
067
Header Type
Configuration Header Format
0 = single function device
1 = multi function device
BIST Register
Completion CodeReserved
Start BIST
BIST Capable
7 6 5 4 3 0
04 3 2 1 0
Base Address31
PrefetchableType
Memory space indicator
Memory Base Address Register
Bits 2-1 00 Base register is 32 bits wide and can be mapped anywhere in the 32-bit memory space. 01 Base register is 32 bits wide must be mapped below 1M in memory space. 10 Base register is 64 bits wide and can be mapped anywhere in the 64-bit memory space. 11 Reserved
Bit 3 : set 1 if prefetchable, set 0 otherwise
Expansion ROM Base Address (Upper 21 bits) Reserved
Expansion ROM Register
01101131
Address decode enable
I/O Base Address Register
12 1 0
Base Address31
ReservedI/O space indicator
Configuration Transactions
• Usage: Access PCI configuration registers
A PCI device or host/PCI bridge require 64 doubleword of config. register
Each PCI function requires 64 doubleword of config. register
• Transaction type:
1. Type 0 configuration read or write transaction
2. Type 1 configuration read or write transaction
3. Memory mapped configuration mechanism ( PowerPC )
• Configuration mechanism:
1. Mechanism 1 ( Preferred)
2. Mechanism 2
Processor
System Memory
Bridge A
Host Bus
Expansion Bridge PCI Bus 0
Memory controller
Bridge B
Bridge D Bridge EPCI Device
PCI Bus 0PCI Device Bridge C
Bridge C
PCI bus 1 PCI bus 3 PCI bus5
PCI bus 2
PCI Bus 4
Expansion bus
PCI Bus 0
Peer Host/PCI Bridges
Type 0 Configuration Transaction
CONFIG_ADDRESS PORT: 0CF8 h - 0CFB h
CONFIG_DATA PORT : 0CFC h - 0CFF h
• Two 32 bit I/O ports are utilized at I/O address:
00DW
Number
Function
Number
Device
Number
Bus
Number Reserved
31 30 24 23 16 15 11 10 8 7 2 1 0
• Configuration Address Register at 0CF8h
1 = Enable Configuration space mapping 0CF8h0CF9h0CFAh0CFBh
• Contents of the AD bus during address phase
00DW
Number
Function
Number Reserved
31 30 11 10 8 7 2 1 0
0CF8h0CF9h0CFAh0CFBh
00DW
Number
Function
Number
Device
Number
Bus
Number Reserved
31 30 24 23 16 15 11 10 8 7 2 1 0
00DW
Number
Function
Number
31 30 16 15 11 10 8 7 2 1 0
Implementation of IDSEL
Decoder
……..
……..
Device Number
16 15 14 ………. 1 0
IDSEL
PCI Slot 1
IDSEL
PCI Slot 2
IDSEL
PCI Slot 3
IDSEL
PCI Slot 4....
TRDY#
GNT#
FRAME#
CLK
AD
1 2 3 4 5 6 87
Address
C/BE# Byte Enables
9
IRDY#
Config Read CMD
IDSEL#
Type 0 Configuration Read Access
Data
Processor write to config. address reg. at I/O port 0CF8
Host/PCI bridge
Bus num the same
YES
Type 0 configuration read or write at config. data port 0CFC
NO
Type 1 config. transaction
START
Pass PCI-to-PCI bridge
Target bus in the range
Bus num the same
YES
NOType 0 configuration read or write at config. data port 0CFC
Type 1 config. transaction
Configuration Mechanism 1
Interrupt Related Issues
Interrupt Signal Bonded To Value Hardwired In Pin RegisterDevice doesn’t generate interrupts 00h
INTA# pin 01hINTB# pin 02hINTC# pin 03hINTD# pin 04h
System IRQ Line Interrupt Routed to Value to be Written In Line Register
IRQ0 0d
IRQ1 1d
IRQ2 2d
IRQ15 15d
• Value to be Hardwired into Interrupt Pin Register
• Interrupt Line Register Values
INTA#
INTA#INTB#
INTA# INTB# INTC# INTD#
INTA#
INTA#
INTA#INTB#
INTA#
INTA#
INTB#
INTC#
INTD#IRQ8-15
Slave
8259
Master
8259
IRQ0-7
Programmable Interrupt router
Interrupt Design
Interrupt Chaining
Entry 1 ISR 1
Entry 2 ISR 2
INT B Entry 2ISR 2 with Entry 1 embedded
IRQ 1
Device 8259
INT A
INT B
IRQ 1
IRQ 2
If INT A and INT B both routed to IRQ1:
PCI Cache Support
• Snoop
SDONE : snoop done
SBO# : snoop backoff. ( HITM when assert.)• The non-cacheable transaction is regardless of SDONE and SBO#.
• Write Through : only use SDONE
• Memory Target Interpretation of Snoop Result Signal from Bridge
SDONE SBO# Description
0 X Standby
1 1 Clean snoop
1 0 Hit on a modified line
Wait States Inserted Until Snoop Completes
CLK1 2 3 4 5 6
FRAME#
AD
SBO#
IRDY#
TRDY#
SDONE
ADDRESS DATA
Hit to a Modified Line Followed by the Writeback
CLK1 2 3 4 5 6
FRAME#
AD
SBO#
IRDY#
TRDY#
SDONE
ADDRESS DATA-1
B CA
ADDRESS DATA-1 DATA-2
STOP#
writeback transaction
HITM CLEANHITMHITMHITM STANDBYSTANDBY
DEVSEL#
Expansion ROMs
Purpose: device-specific power-on self-test code
device-specific initialization code
device-specific interrupt routine
device-specific BIOS routine
device-specific code to be executed during the system boot process
ROM Detection:
Check if Expansion ROM base address
register exist
yes Read if the first two locations on base address register contain 55AAh
yes ROM exist
Code image copied to system DRAM
Execute initialization code
Code Image Format
PCI Expansion ROM Header Format
Offset Length Value Description
0h 1h 55h ROM Signature,byte 1
1h 1h AAh ROM Signature,byte 2
2h-17h 16h XX Reserved(processor architecture unique data)
18h-19h 2h XX Pointer to PCI Data Structure
Header
Data structure
Runtime Code
Initialization Code
(Can be discarded after execution)
Checksum
Unused space
Runtime Module within the Image
Unique Data Area in ROM Header
Offset Length Description
02h 1 Overall size of the image
03h-05h 3 Entry point for the initialization code
( POST performs a far call to initialize the device)
06h-17h 18 Reserved
Offset Length Description
0 h 4 Signature, the string “PCIR”
4 h 2 Vendor Identification
6 h 2 Device Identification
8 h 2 Pointer to Vital Product Data
Ah 2 PCI Data Structure Length
Ch 1 PCI Data Structure Revision
Dh 3 Class Code
10h 2 Image Length
12h 2 Revision Level of Code/Data
14h 1 Code Type
15h 1 Indicator (Bit 7, “1” last image)
16h 2 Reserved
PCI Data Structure Format