Introduction to Microprocessors

AGENDA• Architecture• Microprocessor Communication and Bus Timings• Demultiplexing Address and Data Lines

Architecture of 8085

• Reveals the internal logic of a Microprocessor• 8085 Architecture consists of following blocks:

– ALU logic

– Register Logic

– Timing and Execution Logic

– Interrupt Logic

– Serial I/O Logic

Flag Register

S Z X AC X P X C

Sign

Zero

Carry

Parity

Auxiliary Carry

X - Unspecified

Register Section

• General Purpose Registers

• A, B, C, D, E, H, and L

• BC, DE, and HL

• Special Function Registers

• Program Counter

• Stack Pointer

Timing and Execution Logic

Instruction Register

Instruction Decoder

Timing and Control Unit

Control Signals

Interrupt Logic

• Consists of 5 interrupts with following properties:

• Priority

• Maskable and Non Maskable

• Vectored and Non – Vectored

• INTA is an output signal

Serial I/O Logic

• Supports serial I/O using 2 lines

• SID – Serial Input Data

• SOD – Serial Output Data

Mp communication and Bus Timings - 1

The instruction code 0100 1111 (4FH – MOV C, A) is stored in memory location 2005H. Illustrate the steps and the timing of data flow when it is being fetched

Mp Communication And Bus Timings - 2

B C

D E

H L

SP

PC

Internal Data Bus

ALUInstruction

Decoder4F

Memory2000

20052005

Address BusControl Logic

RD

4F

Data Bus

4F

Timing Diagram

Demultiplexing Address & Data Lines

Probable Questions..

Explain with a neat diagram, the architecture of 8085 microprocessor

Explain the flag register of 8085. With a neat diagram, explain how to separate

multiplexed address and data lines in 8085.Explain opcode fetch machine cycle. What Signals are activated when I/O port at

address ABCD H is read by 8085 ?