Introduction to microfabrication techniques...Introduction to microfabrication techniques....
Transcript of Introduction to microfabrication techniques...Introduction to microfabrication techniques....
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Introduction to microfabrication techniques.
Lithography= Producing of a desirable image in a
photoreisist layer
Photolithography with masks is widely used both in
research laboratories (diffraction limited resolution R~l/2) and
production of modern integrated circuits (ICs) (R~l/10).
For usual photolithography based on single mask process the
minimal size of an element is ~ 1mm
In the IC production, elements as small as 10 nm can be
produced.
One of the main tendencis is the use of sources with smaller l or image reversal
photoresist
Two types of the lithography:
(i) mask-based – fast
(ii) scanning – slow, however necessary for the mask production
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Production of a standard photomask (R>0.5 mm)
1. Producing a mask design file (Autocad, etc.)
2. Deposition of non-transparent material (Cr) on a transparent substrate (quartz).
3. Coating by a photo (electron) resist layer.
4. Creating a image in accordance with the mask design file using a scanning system
scanning beam
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Production of a standard photomask (L>0.5 mm)
5. Development of the exposed photoresist.
6. Etching of the chromium film.
7. Removal of the resist
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Exposition methods in optical lithography
Contact/proximity optical lithography.
Mask aligner MJB4
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Example of a standard processing (R>l) with the use of photomasks.
GaAs/AlGaAs wafer with 2DES -1.
1. Design of photomasks. Alignment marks.
2. Ordering of photomasks.
3. Cleaning of a wafer (aceton, isopropanol)
Superposed masks 1-4
mask1 – mesa etching, positive
mask 2 – contacts, image reversal
mask 3 – bonding pads, image reversal
mask 4 – gates, image reversal
mask 3,
opaque elements
mask 4,
opaque elements
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Example of a standard processing (R>l) with the use of
photomasks.
GaAs/AlGaAs wafer with 2DES -2.
I. Mesa formation.
1. Coating by a image reversal photoresist (AZ 5214 E) layer on a spinner. h~2mkm.
2. Baking (110o C, 50 s) – hot plate (positive resist mode)
3. Mask 1 aligning and exposure (MJB 4). Cr layer to wafer.
4. Development of the exposed photoresist.
6. Chemical etching (H2SO4/H2O2/H2O: 1/8/1000) ~1nm/s h~0.5 mkm.
7. Photoresist removal.
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Example of a standard processing (R>l) with the use of
photomasks.
FET on GaAs/AlGaAs wafer with 2DES -3.
II Producing of Ohmic contacts to 2DES
1. Coating by a image reversal photoresist (AZ 5214 E) layer on a
spinner. H~1.2 mkm.
2. Prebaking (110o C, 50 s) – hot plate
3. Mask 2 aligning and exposure (MJB 4). Cr layer to wafer.
4. Reversal bake (120o C, 120 s) to produce undercut profile appropriate
for lift off.
5. Flood exposure (without mask)
6. Development of the exposed photoresist.
7. Photoresist removal.
8. Cleaning of open ‘windows’ in oxygen plasma.
9. Successive thermal deposition of Ni/Ge/Au/Ni (~7/130/260/36 nm)
layers.
10. Lift off in aceton.
11. Alloying of the films (~60 s, 4400 C in He/N2 gas at pressure ~
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Example of a standard processing (R>l) with the use of
photomasks.
FET on GaAs/AlGaAs wafer with 2DES -4.
III Producing of contact pads and gates to 2DES
1. Coating by a image reversal photoresist (AZ 5214 E) layer on a
spinner. H~1.2 mkm.
2. Prebaking (110o C, 50 s) – hot plate
3. Mask 3 aligning and exposure (MJB 4). Cr layer to wafer.
4. Reversal bake (120o C, 120 s) to produce undercut profile appropriate
for lift off.
5. Flood exposure (without mask)
6. Development of the exposed photoresist.
7. Photoresist removal.
8. Successive thermal deposition of Cr/Au (~10/100 nm) layers.
10. Lift off in aceton.
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Two methods of processing thin films deposited on a substrate.
Etching
1 2
3 4
Lift off
1 2
3 4
Main limitation.
Material of the substrate should be insensitive
to the etching
Important limitation.
The film thickness should should not
exceed the thickness of the photoresist
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Etching
(-) Chemical etching occurs also under a photoresist. It results in an
image slightly different from that of in a photoresist. This makes
chemical etching inappropriate for production of small elements.
(+) Very chip method.
Reactive ion etching (RIE) occur in chemically active
plasma of high frequency electric discharge at a pressure of
the order of 10-2 Torr which is controlled by the gas flow.
Particular gas depends on an etched material and should
produce a volatile chemical compound with the material.
(++) RIE is able nearly perfectly reproduce the photoresist
image.
(-) Rather expansive systems.
(-) Thick enough photoresist to withstand the ion etching.
Otherwise additional masks (e.g., of Al film) should be
produced.
(-) RIE may be accompanied by a charge accumulation on
the wafer (substrate).
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Gases frequently used in RIE
Fluorine species SF6, CF4, CHF3, C4F8
Used mainly for etching silicon based materials and a few metals
Chlorine and bromine species Cl2, BCl3, HBr
Used for etching polysilicon, compound semiconductors, reactive metals
Oxygen O2 is used as a reactive species for etching polymers
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Lift off
(+) Lift-off is a cheap method especially essential in cases where a direct etching of
a material would have undesirable effects on the layer below.
(-) The main problem of the lift off method is possible retention of a material in
undesired places due to sticking to the material to be remained on the wafer or due to
poor access of a solvent to the photoresist. Undercut
Carrying out of the lift off process in the ultrasound
bath partially eliminate this problem.
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Photoresist
There are three basic types of a photoresist: positive, negative and image reversal
(either positive or negative depending on the treatment after the first exposure).
Image reversal photoresist is especially
appropriate for the lift-off process
Image reversal photoresist
Positive photoresist
A wafer is covered with a uniform photoresist layer with the use of
a spinner. The layer thickness is determined by the photoresist
viscosity and the velocity of the spinner rotation.
The desired thickness is determined by the following process:
chemical or ion etching, material deposition, etc.
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Photoresist
Photoresist AZ 5214 E is normally used in ISSP RAN. It is also sensitive to the white light,
but insensitive to the yellow light.
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Electron beam lithography (EBL)
Scanning electron microscope
JEOL 7000 adapted for EBL and
working in the vector scan mode.
Basic parts of an EBL system
Pattern generator sets an electron beam in a desired
point and sends commands to the blanker
Beam blanker interrupts and restores an exposure by
deflecting the electron beam.
Typical parameters of EBL
V=10-100 kV
d>~3 nm - spot diameter
I=0.1-100 nA – beam current
Scanning field
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Scanning modes
Raster scan Vector scan
Vector scanning mode
Pixel size = field size / max. number of points =
minimal step size.
There no relation between the pixel size and
a size of the electron spot. For practical reasons
the latter should be larger.
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Increasing of exposed field
Increasing of the exposed field is usually with the use of precisely moving stages (usually based
on piezo drives and controlled by the laser beam interferometry. The stitching accuracy ~20 nm
can be obtained.
Scanning fields I, II, III, and IV are stitched by moving the precise stage.
Stitching of two subfields is shown in field I. Division into smaller subfields eliminates effects
related to the beam astigmatism.
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JEOL JBX-8100FS Series Electron Beam Lithography System
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Proximity effect in EBL - the main limitation of the resolution/half-
pitch
Proximity effect is a result of the resist exposure by scattered and secondary electrons
Produced in both, a resist and substrate. It strongly affects resolution of EBL, especially in the
case of high density of elements.
Simulated resist profiles for 20 keV electron beam exposure of 1 μm
PMMA resist layer on silicon substrate, the shaded area represents the ideal
resist profile and the contours represent the actual resist profiles at exposure
doses from 80 to 120 μC/cm2 with 10 μC/cm2 increment
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Reduction of the proximity effect in EBL
1. The use of high accelerating voltage ~ 100 kV.
2. The use of a thin photoresist layer.
3. Correction of the exposed area in comparison with desired one.
4. Variation of the exposure dose along the image in accordance with appropriate software.
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A Hall bar structure made of gold
films on oxidized Si wafer.
EBL in the machine with a spot
size~30x50 nm2
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Reduction of the proximity effect in EBL
An ultra-high resolution obtained on 10 nm resist placed on 10-nm-thick Si3N4 membrane
with the use of 100 kV scanning transmission electron microscope.
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A role of the dose
An Au bridge with
(i) completely exposed resist area at the bridge supports,
(ii) Incompletely exposed resist at the bridge deck,
(iii)Unexposed resist elsewhere
A bridge contact in an electronic
Mach–Zehnder interferometer
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Resists for EBL
The main positive resist is polymethyl methacrylate (PMMA) of different molecular
weight (chain length) from a diapason 50x103 – 2x106 . Usually used are 495x103 and 950x103
resists. Resins of different concentration (2-12 %) in chlorbenzene or anisole are used. Typical
doses are 50 - 500 μC/cm2
Negative resist Hydrogen silsesquioxane (HSQ) with the chemical formula [SiO3/2]n allows for as
thin as 10 nm resist layer.
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The use of a double-layer EBL resists
The copolymer is an electron beam resist which needs much smaller dose than the main resist
layer.
Also a layout for
tilt-angle deposition
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Acceleration methods in the mask production
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High electron mobility transistor (HEMT) = heterostructure FET (HFET) = modulation-doped FET (MODFET)
2)(/*)( eVnmVR gsg
Example of a static I-V charachteristic.
At small voltages between drain and source
I-V nonlinearity is the result of the
potential drop along the current carrying channel,
which leads to coordinate dependence of the
electron density ns.
Such transistors can be produced on other semiconductior
materials: InGaAs/AlGaAs, AlGaN/InGaN, etc. However the
modulation doping is the common method to produce high
electron mobility.
If HEMTs are used for amplification of high
frequency signals, MOSFETS in ICs work
as switches
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Metal-oxide-semiconductor field-effect transistors (MOSFETs)
G-gate, B- contact to the bulk (substrate)
S, D – source and drain contacts
n+ and p+ are highly doped regions
with donors and acceptors, respectively.
NMOS - MOSFET with electron channel
induced by a positive gate voltage
PMOS – MOSFET with hole channel
induced by a negative gate voltage.
]1[
]0[0
VVin
]0[0
]1[VVout
]1[VVs
open
closed
closed
open
]1[VVs
Ground [0]
outVinV
Complementary metal–oxide–semiconductor (CMOS) inverter
Complementary metal–oxide–
semiconductor (CMOS) layout = pair of
MOSFETs with different channel type
is a basic element of modern integrated
circuits due to its very small power
consumption.
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Main steps of the CMOS processing on p-Si
NAND gate circuit and its layout.
Polysilicon gates of and metal films are
in different planes and do not contact
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Below the diffraction limit (R
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Below the diffraction limit (R
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Final remarks