Introduction to FPGA - RWTH Aachen...
Transcript of Introduction to FPGA - RWTH Aachen...
Introduction to FPGA
Jens Hahne, Hongrui Deng,Arne Doring, Daniele Mele
High-Performance and Automatic Computing groupin RWTH-Aachen
[email protected]@[email protected]@rwth-aachen.de
January 29, 2015
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Outline
1 FPGA ArchitectureOverviewLogic Block ArchitectureRouting ArchitectureInput / Output ArchitectureComparision with CPU
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FPGA Architecture – Overview
1 Pre-fabricated silicon devices electrically programmable
2 Ad/dis-advantages to Application Specific Integrated Circuit (ASIC)technologies:
3 From small enterprises to large corporations FPGAs is the onlysolution for scalability and performance of Moore’s law
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FPGA –Components overview
1 Array of programmable logic blocks, including general logic, memoryand multiplier blocks
2 Programmable routing fabric for interconnection
3 Programmable input/output blocks (1/0)
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Outline
1 FPGA ArchitectureOverviewLogic Block ArchitectureRouting ArchitectureInput / Output ArchitectureComparision with CPU
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FPGA Architecture – Logic Block Architecture
Logic Block Architecture
1 What is Logic Block Architecture?
2 Categories of Logic Block Architecture
3 Some Examples
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FPGA Architecture – Logic Block Architecture
Logic Block Architecture
1 What is Logic Block Architecture?
2 Categories of Logic Block Architecture
3 Some Examples
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FPGA Architecture – Logic Block Architecture
What is Logic Block Architecture?
1 A logic Block is the basic functional unit of the FPGA
2 Capable of implementing many different combinational and sequentiallogic functions
3 Consist of some combination of these basic functional units:
Transistor pairsBasic small gates (such as two-input NAND’s or exclusive-OR’s)MultiplexersLook-up tables (LUT’s)Wide-fanin AND-OR structures
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FPGA Architecture – Logic Block Architecture
Logic Block Architecture
1 What is Logic Block Architecture?
2 Categories of Logic Block Architecture
3 Some Examples
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FPGA Architecture – Logic Block Architecture
Categories of Logic Block Architecture
1 fine-grain
2 coarse-grain
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FPGA Architecture – Logic Block Architecture
Categories of Logic Block Architecture1 fine-grain
consists of just a couple transistors, a couple logic gates liketwo-input NAND gate.
Such as, The Plessey FPGA uses two-input NAND gate as its basicblock.
Figure: The Plessey logic block.[1]
2 coarse-grainJens Hahne, Hongrui Deng, Arne Doring, Daniele Mele (RWTH)FPGA January 29, 2015 11 / 26
FPGA Architecture – Logic Block Architecture
Categories of Logic Block Architecture1 fine-grain2 coarse-grain
consists of fairly large logic blocks, often containing multiplexer,look-up tables(LUT), or flip-flops.
Such as, The Xilinx Logic Block uses an SRAM(Static Random-accessMemory) functioning as a loop-up table as its basic block.
Figure: Lookup table-based logic.[1]
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FPGA Architecture – Logic Block Architecture
Logic Block Architecture
1 What is Logic Block Architecture?
2 Categories of Logic Block Architecture
3 Some Examples
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Example
Taking a logic function f = ab + c as an example,
using two-input NAND gate:
Figure: Two-input NAND gateimplementation.[1]
using LUT:
Figure: Lookup table-basedimplementation.[1]
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Outline
1 FPGA ArchitectureOverviewLogic Block ArchitectureRouting ArchitectureInput / Output ArchitectureComparision with CPU
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FPGA Architecture – Routing Architecture
Provides communications among Configurable Logic Blocks(CLB)and I/O units
Global routing
Macroscopic allocation of wires
Interconnection of CLBs
Two approaches: hierarchical and island-style
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FPGA Architecture – Hierarchical routing architecture
More predictable inter-logic block delay
Adjacent CLB incurs significant and distinct delay penalty
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FPGA Architecture – Island-style routing architecture
Routing channels on 4 sides of logic blocks
# of wires in a channel pre-setted
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FPGA Architecture – Routing example
Example
a ∧ (b ∨ c)
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FPGA – Addressed features FPGA description parameters
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Outline
1 FPGA ArchitectureOverviewLogic Block ArchitectureRouting ArchitectureInput / Output ArchitectureComparision with CPU
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FPGA Architecture – Input/Output architecture
I/O cells includes I/O pad and surrounding supporting logic andcircuitry
Occupies large area in an FPGA (≈ 25%÷ 45%)
Different standard influences flexibility and silicon-area
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Outline
1 FPGA ArchitectureOverviewLogic Block ArchitectureRouting ArchitectureInput / Output ArchitectureComparision with CPU
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Comparison to CPU
FPGA CPU
-No fixed hardware structure -Fixed hardware structure(fixed: logic cells (peripheral structures, connections,not fixed: function, interconnection) operation predefine)
-Control over the hardware -Control over the software-Hardware Description Language -C, Java, ....
-Good for: -Good for:Intensive data processing Routine control operations
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References
Johathan Rose, Abbas El Gamal and Alberto Sangiovanni (1993)[1] Architecture of Field-Programmable Gate Arrays
http://fpgacenter.com/fpga/fpga or cpu.php
https://embeddedmicro.com/tutorials/mojo/what-is-an-fpga
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Credits
Overview (FPGA 1)
Logic Block Architecture (Hongrui Deng)
Routing Architecture (FPGA 1)
Input / Output Arch. and Capabilities (FPGA 1)
Comparison with CPU (Jens Hahne)
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