Introduction to Design Tools COE 1502. Review: Tools, functions, design flow Four tools we will use...
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Transcript of Introduction to Design Tools COE 1502. Review: Tools, functions, design flow Four tools we will use...
Review: Tools, functions, design flow
Four tools we will use in this course– HDL Designer Suite
FPGA Advantage (aka Renoir)– IDE to create hierarchical designs and generate HDL
ModelSim– Robust logic simulator
– Xilinx XST synthesis Place-and-route netlists onto FPGAs
Review: Tools, functions, design flow
VHDL code
Generate
Proprietary binary format
Compile
Simulate using ModelSim
EDIF “gate-level” netlist using Xilinx CLBs
Synthesize using XST
Xilinx .BIN binary
Place-and-route
Load onto FPGA and test using LA
FPGA Advantage
Create symbolic designs
Proprietary text format
Libraries in FPGA Advantage
A library is a collection of components– Components have one or more views (implementations)
Block diagram, truth table, flow chart, state machine, VHDL architecture
– Each view has representations: Graphics, VHDL, simulator netlist, synthesis netlist
CPU control_unit
CPU_lib
VHDL arch state diagram
gen. VHDL sim. binary synth. netlist
library
component
view
representation graphics
block diagram 2block diagram 1
ALU
Components
Library components can be instantiated in other designs
– Shown as green blocks For bottom-up design
– Libraries also contain “blocks” Attached to the design they
were created in Shown as blue blocks For top-down design
– Embedded blocks – embedded into block diagram
Shown as yellow blocks Embeds behavior into
structure
Libraries in FPGA Advantage
Libraries are stored in four subdirectories in your group directory (e.g. I:\alpha)
– For each library you use or create, library mappings to these directories must be specified
– The mappings for your set of libraries are stored in your project file Lives in your group directory
I:\alpha
\ALU_lib
\CPU_lib
\hds
\hdl
\work
\ls
source directory
HDL directory
simulation directory
synthesis directory
Projects
A project in FPGA Advantage is a set of library mappings
Create a new project in your user workspace– “tutorial”
Projects, Libraries, Components, Views
tutorial
ALU_Lib
ALU
Src (hds)(graphical view)
HDL(generated)
Downstream
(compiled for sim)
Downstream
(compiled for synth)
Project
Library
Component
Projects, Libraries, Components, Views
ALU CPU
ALU_Lib COELib CPU_Lib
Shared Project
ieee
src files hdl files sim files synth files
Example design: ALU
Specifications for ALU– GOAL: implement all logical, arithmetic, shift, and comparison
operations in MIPS instruction set Operations
– Bit-wise AND, OR, XOR, and NOR– Signed and unsigned addition, subtraction
Overflow detection, zero-result detection– Signed and unsigned set-on-less-than comparison– Logical shift left and right, arithmetic shift right
– Must accept 2 x 64-bit operands and produce a 64-bit result
Example design: ALU
Inputs– A, B (64 bits)– SHAMT (how many bits?)– ALUOP (how many bits?)
13 total operations
Outputs– C (64 bits)– Overflow– Zero
Example design: ALU
We will work top-down to design the ALU– First step is to create top-level design– Need to choose a view which will implement a
VHDL architecture– View type: block diagram
Implements structural VHDL
– From design browser… File | New | Graphical View | Block Diagram
Example design: ALU
First, let’s discuss the block diagram toolbars…
One level up/Save
Add block/component
Add embedded block
Add signal/bus
Add ports
Generate VHDL and simulate
Example design: ALU
First, add interface signals with ports (using the toolbar tool, “wire with port”)…
Note signal widths (in wire
properties)
Example design: ALU
Save the block diagram into the ALU library
– The component name will be “ALU”
Let’s look at the ALU symbol…– Click “up” in BD, or– Use the design
browser
Source file
Symbol file
Example design: ALU
The symbol looks something like this…
– We can change the shape and pin locations here
Right click, then “Autoshapes”
Make the symbol look like an ALU symbol
Example design: ALU
Go back to the block diagram window and let’s generate VHDL for our design…
Next, let’s take a look at the VHDL that we generated…
Example design: ALU
-- VHDL Entity ALU.ALU.symbol---- Created:-- by - ajnoyola.UNKNOWN (TWEETY)-- at - 23:46:41 03/10/2006---- Generated by Mentor Graphics' HDL Designer(TM) 2005.1 (Build 83)--LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ENTITY ALU IS PORT( A : IN std_logic_vector (63 DOWNTO 0); ALUOp : IN std_logic_vector (3 DOWNTO 0); B : IN std_logic_vector (63 DOWNTO 0); SHAMT : IN std_logic_vector (4 DOWNTO 0); SHAMT_HIGH : IN std_logic; Overflow : OUT std_logic; R : OUT std_logic_vector (63 DOWNTO 0); Zero : OUT std_logic );
-- Declarations
END ALU ;
---- VHDL Architecture ALU.ALU.struct---- Created:-- by - ajnoyola.UNKNOWN (TWEETY)-- at - 23:46:42 03/10/2006---- Generated by Mentor Graphics' HDL Designer(TM) 2005.1 (Build 83)--LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF ALU IS
-- Architecture declarations
-- Internal signal declarations
BEGIN -- Instance port mappings.
END struct;