Introduction to DACs_ Tutorial
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Transcript of Introduction to DACs_ Tutorial
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The World Leader in High-Performance Signal Processing Solutions
Data Conversion Fundamentals
Digital-Analog Converters
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The World Leader in High-Performance Signal Processing Solutions
Introduction to D/A Converters
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D/A Converter Introduction
D/A Fundamentals Transfer Function Quantization
Factors Affecting D/A Converter Performance Static Performance Dynamic Performance
DAC Architectures Resistor String R-2R Switched Current
High Speed DAC Application Considerations
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Digital to Analog Converters
MUXANALOGSIGNAL
PROCESSOR
A - DCONVERTER
D - ACONVERTER
ANALOGSIGNAL
PROCESSORMUX
MICROPROCESSOR
ORDSP
PROCESSOR
REFERENCE• Multiplier/Divider• Log Amplifier• Rms-Dc Converter• F-V/V-F Converter
• Operational Amp• Differential Amp• Instrumentation Amp• Isolation Amp
nbits
nbits
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ADC SAMPLED ANDQUANTIZED WAVEFORM
DAC RECONSTRUCTEDWAVEFORM
ADC
DAC
DSP MemoryChannel
Analog Digital
timetime
Ana
log
Digita
l
Amplitu
de
Value
“Real World” Sampled Data Systems Consist Of ADCs and DACs
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ANALOGOUTPUT
DIGITALINPUT
REFERENCEINPUT
Digital Input Analog Output = x Reference Input
(2N - 1)
What is a Digital-Analog Converter?
Produces a Quantized (Discrete Step) Analog Output (Voltage or Current) in Response to Binary Digital Input Code
Digital Inputs May Be TTL, ECL, CMOS, LVDS… A reference quantity (either voltage or current) is accurately divided into binary
and/or linear segments. The digital input drives switches that connect an appropriate number of segments to
the output. Finite Number of Discrete Values : 2N Resulting in Quantization Uncertainty Sampling and Quantization Impose Fundamental yet Predictable Limitations
RESOLUTION= N BITS
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Sampling Process Representing a continuous time domain signal at discrete and
uniform time intervals Determines maximum bandwidth of sampled (ADC) or
reconstructed (DAC) signal (Nyquist Criteria) Frequency Domain- “Aliasing” for an ADC and “Images” for a DAC
DISCRETETIME SAMPLING
AMPLITUDEQUANTIZATION
y(t)
y(n)
y(n+1)
n-1 n n+1 n+3 ts t
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Quantization Process Quantization Process
Representing an analog signal having infinite resolution with a digital word having finite resolution and an analog output which only exists in discrete levels
Determines Maximum Achievable Dynamic Range Results in Quantization Error/Noise
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DIGITAL INPUT
1/8
001 010 011 100 101 110 111
1 LSB
AN
ALO
G O
UTP
UT
2/8
3/8
4/8
5/8
6/8
7/8
Conversion Relationship for an Ideal D/A Converter
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DAC Resolution, LSBs and More...
Resolution, Bits (n)
2n
LSB, mV (10V FS)
% Full Scale
ppm Full Scale
dB Full Scale
8 256 39.1 0.391 3906 -48.0
10 1024 9.77 0.098 977 -60.0
12 4096 2.44 0.024 244 -72.0
14 16,384 0.610 0.006 61 -84.0
16 65,536 0.153 0.0015 15 -96.0
18 262,164 0.038 0.00038 3.8 -108.0
20 1,048,576 0.0095 0.00010 1.0 -120.0
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Unipolar and Bipolar Converter Codes
0 0 0
FS - 1LSB FS - 1LSB FS - 1LSB
ALL"1"s 1 AND ALL "0"S
ALL"1"s
UNIPOLAR OFFSET BINARY 2’s COMPLEMENT
-FS -(FS - 1LSB)
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Factors Affecting D/A Converter Performance- Offset And Gain for Unipolar Ranges
ACTUAL
OFFSET
ERROR
WITH GAIN ERROR:OFFSET ERROR = 0
ACTUAL
IDEAL IDEAL
ZERO ERROR
NO GAIN ERROR:ZERO ERROR = OFFSET ERROR
0 0
GAIN
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ACTUAL
OFFSETERROR
WITH GAIN ERROR:OFFSET ERROR = 0ZERO ERROR RESULTSFROM GAIN ERROR
ACTUAL
IDEAL IDEAL
ZERO ERROR ZERO ERROR
NO GAIN ERROR:ZERO ERROR = OFFSET ERROR
0 0
Factors Affecting D/A Converter Performance- Offset And Gain for Bipolar Ranges
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DC Specifications (DNL & Montonicity)
Differential Non-Linearity (DNL) is the deviation of an actual step size from the ideal 1 LSB step.
DNL error results in smaller or larger step sizes than ideal DNL error esults in additive noise/spurs beyond the effects
of quantizationA DAC Is Monotonic If Its Output Increases or Remains the
Same for an Increment in the Digital CodeConversely, a DAC Is Non-Monotonic If the Output Decreases
for an Increment in the Digital Code
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Monotonicity
n n+1 n+2 n+3 n n+1 n+2 n+3
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Monotonicity
ANALOGOUTPUT
DIGITAL INPUT
FS
000 001 010 011 100 101 110 111
NON-MONOTONIC
IDEAL
ACTUAL
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DC Specifications (INL)
Integral Non-Linearity (INL) is the deviation of an actual output voltage from the ideal output voltage on a straight line drawn between the end points of the transfer function.
INL is calculated after offset and gain errors are removed INL error results in additive harmonics and spurs
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AD5554, 14-Bit DAC, INL and DNL PLOTs
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Frequency Domain Performance
SFDR
Frequency
THD
Mag
nitu
de
SNR
SFDR = The difference between the rms power of the fundamental and the largest spurious signal in a given bandwidth
THD = The ratio of the rms sum of the first six harmonics to the amplitude of the fundamental
SNR = The ratio of the rms value of the fundamental to the rms sum of all noise components in the Nyquist bandwidth (excluding harmonics)
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Correlation Between DC and AC Performance
Output Frequency - MHz
SFD
R-d
Bc
Low Frequency PerformanceDominated by Linearity (DNL)
High Frequency PerformanceDominated by Dynamic Errors
DNL can be closely correlated to SFDR for low frequencies below the “knee”
Dynamic errors include: Nonlinear output impedance Digital Feedthrough Signal-dependant glitching
or settling
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Correlation Between DC and AC Performance
AD9754: Linearity Calibration and Impact on AC Performance
78 dB SFDR 83 dB SFDR
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Settling Issues
DNLError
Clock / DataFeedthrough
Time
NonlinearSlewing
GlitchImpulse
NonidealResponse
IdealResponse
Clock toOutput Delay
DA
CO
utpu
tVol
tage
Static Errors (INL, DNL) occur after transition, resulting in low-frequency distortion
Dynamic Errors happen during transition and are typically proportional to step size (i.e. worse for high frequencies and/or large amplitudes)
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A Simple D-A Converter Using a Kelvin Divider
Not a Practical ApproachOutput is MonotonicFor N Bit Resolution, 2N Resistors (Taps) are Required
VREF
R1 R2 R3 R4 RN
+
-VOUT
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Voltage Segment DAC
VOUT
VREF
R1
R2
R3
R4
RN
R1
R2
R3
R4
RN
x1
x1
x1
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STRING DAC Architecture
Traditional String DAC requires 2n Resistors.
Main DAC and Sub-DAC leads to 2N/2 + (2N/2 -1) Resistors
Vsubdac=Rll(3R)=3R/4. VREF=1 Rtotal=R/4+(3R)/4+3R = 4R LSB = Vsubdac/3=R/4 Size, Power, and Cost
Reduction. Resistor Matching Excellent-
DPDM, no Trimming. Guaranteed Monotonic Voltage Output
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Infinite Sample and Hold Architecture
DAC
SAR
VREF
AIN
SW1SW2
SW3+
-
SW1
SW2SW3
Acquire Hold1=Closed
DAC
SAR
VREF
AIN
SW1SW2
SW3+
-
DAC
SAR
VREF
AIN
SW1SW2
SW3+
- VOUT
OFFS+
+
-
-
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A Simple Binary-Weighted D-A Converter
A Simple Binary-Weighted Network. The Current I is the Sum of the Individual Currents Through R, 2R and 4R.
R+
-
4R
2R
S1
S3
S2
V
RFI
VOUT= -IRF
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R-2R Ladder Network
R and 2R Values Easy to Trim in ProductionMatch to 1 Part in 2n Will Yield n MonotonicityAbsolute Value Not Important (typ. 10-20 k, +/-20%)Voltage vs. Current Switching Mode
R R R R R
2R 2R 2R 2R 2R
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Current Steering Mode
Current Steering Mode Constant Input Impedance Output Impedance Varies with Code Vout = -D X Vref REF Bandwidths < 1 MHz Nonlinearity Increases with Decreasing Reference
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Segmented R-2R
3, 4 or 5 Fully Decoded MSBs followed by R2R Ladder for LSBs
Less Trimming in Production for Higher Resolution DACs Linearity Specs more readily achievable Lower Input Impedance - Less Distortion. Fixed Input Impedance.
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“Multiplying” DAC
DIGITALINPUT
VREF
V or IOUTPUTR-2R
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Voltage Switching Mode
Output Voltage is Same Polarity as Input Constant Output Impedance Input Impedance Varies With Code VREF Limited to 2.0-2.5 Volts Allows Single Supply Operation
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CMOS R-2R DAC Equivalent Circuit
+
-
DVREF
R RSR CO
VREF
RFBCFB
DAC
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CMOS DAC Equivalent Circuit (con’t)
R is the Ladder Resistance Seen By The Reference (typ 10-20 kilohms).
VREF/R = Full Scale Current OutputD = Digital Code RatioRO, CO = Code-Dependent Output Resistance and
CapacitanceRFB = DAC Internal Feedback Resistor For Use With External
Amplifier. Matched and Tracking With R-2R Ladder.CFB = Compensation Capacitance for CO.
= CO
2 x pi x BW; BW = Unity Gain Bandwidth
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Bipolar Switched Current DACIout
Good device matching results in good DC performanceDevice scaling difficult, requires R-2R for higher resolutionTypically higher power, can’t integrate Digital Signal
Processing
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CMOS Switched Current DACScaling issues are simplified, no need for R-2RAllows Integration of Digital Signal ProcessingGood Device Matching for 12-bit linearity, calibration
required for higher resolutionPopular in Communications applications
Current Sources are binarily weighted
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Terminating a Current Output DAC
IOUT
RLOAD
+
-VOUT
Best AC performance
Compliance Voltage
VCC
VCOMP
+
-RFB
Best DC Performance
Virtual Ground
IOUT
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Architecture Pros and Cons
Summary: Resistor String
Inherent Monotonicity Compact Design Leading to the basis of Multi-Channel DACs Difficult to get High performance INL
R-2R Ladder Good DC performance Suffer from distributed R-C effects and signal-dependant loading in
frequency-domain applications Multiplying Capability Can Operate in Voltage Mode for Single Supply Applications
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Architecture Pros and Cons
Summary (con’t): Bipolar Switched Current
Suffers AC limitations because R-2R is typically required to create LSB currents
CMOS Switched Current Best Choice for frequency-domain applications:
No R-2R to limit AC performance Good matching for DC specifications (calibration sometimes needed) Allows for integration with discrete signal processing blocks to ease
implementation and improve performance
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Dynamic Testing of D/A Converters
Digital DataGenerator
Low Noise/Jitter Clock Source
Low Noise/JitterPulse Generator
RF OUT
Trig IN
CH 1 CH 2
Clock IN
16 TxDAC ®
Evaluation Board
High PerformanceSpectrum Analyzer
Output(Diff. or S/E)
RF IN
Ext. Clk.
Note: AD9772, AD9751/53/55, AD9773/75/77can accept a sine wave clock input.
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Static Testing of D/A Converters
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Example of Data Sheet Specifications for DAC
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Example of Data Sheet Specifications for DAC
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For complete informationon the World’s most extensive line of
D/A converters visit
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