Introduction to Computer Engineering ECE...
Transcript of Introduction to Computer Engineering ECE...
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Introduction to Computer Engineering
ECE 203
Northwestern University
Department of Electrical Engineering and Computer Science
Teacher: Robert DickOffice: L477 TechEmail: [email protected]: 467–2298Webpage: http://www.ece.northwestern.edu/˜dickrp/ece203Teaching Assistants Zhenyu Gu (L470)
Debasish Das (M314)
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Homework index
1 How to get lab supplies . . . . . . . . . . . . . 18
2 Mailing list . . . . . . . . . . . . . . . . . . . 19
3 Reading assignment (for next class) . . . . . . 67
4 Reading assignment . . . . . . . . . . . . . . 155
5 Reading assignment . . . . . . . . . . . . . . 176
6 Reading assignment . . . . . . . . . . . . . . 286
7 Reading assignment . . . . . . . . . . . . . . 326
8 Reading assignment . . . . . . . . . . . . . . 395
9 Reading assignment . . . . . . . . . . . . . . 411
10Homework assignment two . . . . . . . . . . . 412
11Reading assignment . . . . . . . . . . . . . . 478
12Reading assignment . . . . . . . . . . . . . . 490
13Homework three . . . . . . . . . . . . . . . . 562
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14Reading assignment . . . . . . . . . . . . . . 563
15Reading assignment . . . . . . . . . . . . . . 582
16Assigned reading . . . . . . . . . . . . . . . . 635
17Assigned reading . . . . . . . . . . . . . . . . 663
18Assigned reading . . . . . . . . . . . . . . . . 664
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Topics covered
• Analog vs. digital signals, thresholds
• Switch model
• NMOS and PMOS transistors as switches, reason for
NMOS/PMOS difference
• Basic logic gates and transmission gates from CMOS
• More complex devices from basic gates and transmission gates
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Topics covered
• Truth tables
• Basic facts about TTL use (lab kits)
• Boolean algebra, De Morgan’s Laws = bubble pushing
• Two-level logic forms
• Karnaugh maps
• Quine-McCluskey algorithm
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Topics covered
• Encoders, decoders, MUXs, DMUXs
• Safe implementation with TGs
• Number bases: decimal, binary, hex, etc.
• High-level understanding of ASCII and Unicode
• Signed and unsigned numbers, different signed representations,
Gray code
• Arithmetic units in digital logic, carry select, main idea of carry
lookahead
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Assigned reading
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
– Sections 1.1–1.7
– Sections 2.1–2.10
– Sections 4.1–4.6
– Sections 5.1–5.6
– Sections 6.1–6.3
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Assigned reading
• CMOS handout from M. M. Mano, Digital Design. Prentice-Hall,
Englewood Cliffs, NJ, third ed., 2002
• TTL handout from D. Lancaster, TTL Cookbook. Howard W.
Sams & Co., Inc., 1974
• Quine–McCluskey from R. H. Katz, Contemporary Logic Design.
The Benjamin/Cummings Publishing Company, Inc., 1994 and
J. P. Hayes, Introduction to Digital Logic Design. Addison-Wesley,
Reading, MA, 1993
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Today’s topics
• Reason for late start
• Brief course overview
• Majors
• Administrative stuff
– The fun stuff starts on Monday!
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Brief course overview
• Hardware design
• Low-level programming
• Computer geek culture
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What’s your major?
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Computer geek already?
• Good!
• You’ll still probably see a lot of new things in this course
• Go ahead and ask questions that push beyond the basic material
• If you want to go beyond the normal labs, I’ll be happy to make
suggestions
• ECE 203 should lay the foundations for logic design and
understanding the connections between electrons and software
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Not a computer geek yet? Good!
• You’re going to be working with computers in almost any field
• Understanding how they work at the lowest levels and knowing
how to build them will put you ahead your peers
• If you’re not a computer geek yet, sit in the front of the classroom
and ask questions!
– It’s the best way to keep the course’s pace sane
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Backgrounds
• Different backgrounds
• ECE 203 can be a hard course
• However, if you work hard, I’m totally confident that you will learn
how to build useful computers
– TAs and I will help
• In the past, many Materials Science, BME, and IEMS did
absolutely amazing work
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Rules
• If something in lecture doesn’t make sense, please ask
– If it doesn’t make sense to you, others have the same
question!
• Do you feel like there is a gap in your background, e.g., forgot
about resistance and capacitance?
– It’s O.K. I have handouts and office hours to help but don’t fall
behind!
• You’re paying a huge amount of money for this
• I expect a lot
• However, I’ll do whatever I can to make sure you get as much out
of this course as you put in
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Core course goal
By the end of this course,
I want every one of you to be capable of
designing and building simple but useful
computer systems from integrated circuits, wires, and
assembly language instructions
In fact, it’s a requirement
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Administrative stuff
• How to get lab supplies
• How to subscribe to mailing list
• Some good references
• Decide grading policies
• Plan office hours
• Course overview (if time permits)
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How to get lab supplies
• Each student is required to pay $20 for lab supplies
– Integrated circuits, wires, capacitors, resistors, etc.
• Make check to Northwestern University
• Take the check to the Bursar’s office
• Take the receipt to Albert Lyerla in EG27 to pick up lab kits after
class on Monday
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Mailing list
• Please subscribe to the ECE203 mailing list by sending an email
to [email protected] with no subject and a
body of “SUBSCRIBE ECE203 Firstname Lastname”.
• I encourage you to use the mailing list for discussion.
• Please don’t hesitate to use the list. If anybody thinks the traffic is
too high, I’ll set up separate “Announce” and “Discuss” lists.
• In general, if I answer somebody’s question via email, I will also
post the answer to the mailing list (without including the person’s
name).
• Do this today! The mailing list is an important and required
component of the course – used for announcements.
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References
• Primary reference: M. M. Mano and C. R. Kime, Logic and
Computer Design Fundamentals. Prentice-Hall, Englewood
Cliffs, NJ, third ed., 2004
• Z. Kohavi, Switching and Finite Automata Theory. McGraw-Hill
Book Company, NY, 1978
• R. H. Katz, Contemporary Logic Design. The
Benjamin/Cummings Publishing Company, Inc., 1994
• J. Hennessy and D. Patterson, Computer Architecture: A
Quantitative Approach. Morgan Kaufmann Publishers, CA, 1995
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Grading
• I’m open to reasonable options
• Class needs to agree on scheme within the first week
• Once an option is chosen, it’ll be my job to stick to it
• One possible option follows
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Possible grading scheme
• 15% homeworks
• 35% labs
• 20% midterm exam
• 30% final exam
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Late homework assignments
• After the class, on the due date: -5%
• After that, 10% per day penalty
• Three or more working days late: No credit
– I’ll hand out solutions
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Late lab assignments
• Late lab verifications will be done at the discretion of the TAs
• In other words, although this will sometimes be possible, I’m not
going to force the TA to skip their classes, research work, or
meals to hold extra lab verification hours
• Late lab checks (without prior approval): -20%
• Three or more working days late: No credit
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When to start labs
• The TAs spend a huge amount of time checking labs
• Having them do lab checks outside of the scheduled hours
makes it difficult to keep up in their own classes and research
• Start labs early to see if you have questions
• The TAs and I will be happy to help
• Will need time to finish after pointed in right direction
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Labs
• Open labs
• Tech EG27
• The TAs and I may leave a note and go from our offices to EG27
during office hours to answer lab questions
• You will need to sign up for a lab time slot
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Lab check times
• Labs will be assigned on Fridays
• Can lab checks be held on Wednesday and Thursday throughout
the day?
• Thursday and Friday would give you more time but might make it
more difficult for those checked on Friday to attend the help
sessions
• First lab much quicker than others
• Need to get go to get kit by Monday, though
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Office hours options
1. Tuesday/Thursday throughout day
2. Monday/Thursday throughout day
3. Every day in morning
4. Every day in evening
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Course overview
• Know what is computer engineering is
• Know some reasons to learn computer engineering
• Understand course goals
• Know which future courses ECE 203 can prepare you for
• Know course topics
• Start learning basic logic definitions
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What is computer engineering?
• Design and implementation of computer systems
• Hardware and software design
• Related to electrical engineering and computer science with an
emphasis on digital circuits
• The best computer engineers are also good at electrical
engineers and computer science
• Knowing fundamentals helps in fields where computers are used
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What is computer engineering?
• You need something solid to stand on
• Applications make more sense if you understand programming
• Programming makes more sense if you understand processors
• Processor make more sense if you understand logic design
• Logic design makes more sense if you understand circuits and
discrete math
• Circuits make more sense if you understand transistors
• Every understanding rests on others
• Computer engineering requires understanding the many levels
and the ways they fit together
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Why computer engineering
• Why are you taking this class?
• What do you want to learn?
• What kind of background do you have?
– When you see something cool do you reach for a screwdriver?
– Who was electrocuted as a young child trying to figure out
how something works?
– Who has written code?
– Who has designed something complicated for the fun of it?
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Why computer engineering? Fun
• Computers are almost magical
– You’ll learn how they work and how to build new ones
• You’ll learn (discrete) math, semiconductor physics, and the
theory of algorithms
• You’ll be able to use your knowledge creatively
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Why computer engineering? Fun
• In the end, your creations will be tested against unforgiving
physical laws in the real world
• There are many right ways (ways that work) to design a computer
but there are also many wrong ways (ways that don’t work)
– There are measurable and clear differences between the
quality of different designs
• You’ll spend a lot of time with hard-working people who share
your interest in designing machines that make life better
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Why computer engineering? Flexible
Learn hardware and software design, can move in either direction
• Embedded system design
• Computer architecture
• VLSI design
• Digital circuit design
• Software engineering
• Algorithm design
• Information technology
If you finish a Ph.D., many other doors also open
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Why computer engineering? Money
• 2004 CNN survey: Most lucrative undergraduate degree
• 2005 National Association of Colleges and Employers survey
Field Average salary ($)
Computer Engineering 52,464
Electrical Engineering 51,888
Computer Science 50,820
Mechanical Engineering 50,236
Biomedical Engineering 48,503
Civil Engineering 43,679
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Why computer engineering? Money
• Also compare to business administration ($37,368) and
psychology ($25,032)
• Of course, this alone is not a good reason to pick a major
• Do what you love!
– . . . but if you love computer engineering, the financial stuff
might make it easier to justify to your relatives
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Future courses
• Advanced digital logic design
• Computer architecture
• Design and analysis of algorithms
• Fundamentals of computer system software
• Introduction to computer networks
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Future courses
• Introduction to VLSI CAD
• Introduction to mechatronics
• Microprocessor system design
• Programming for computer engineers
• VLSI systems design
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Course topics in context
• Logic gates
– Basic units of digital logic design
• Truth tables
– Simple Boolean function representation
• Boolean algebra
– Another way of representing and manipulating Boolean
functions
• Two-level logic forms
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Course topics
• Logic minimization: Boolean algebra, Karnaugh maps, and
Quine-McCluskey’s method (if time permits)
– Reduce area, power consumption, or improve performance
• Hazards
• Implementation in CMOS
• Number systems: decimal, binary, octal, hex, and Gray codes
• Signed and unsigned numbers
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Course topics
• Arithmetic circuits, decoders, encoders, and multiplexers
• Sequential logic: Latches, flip-flops
• Finite state machines
• Assembly language programming
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Course topics
• Overview of compilation of higher-level languages
• Computer organization
• Microcontrollers
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Software
• Easy to change and design
• Usually has low performance compared to hardware
implementation
• High power consumption
• General-purpose processor
• Digital signal processor (DSP)
• Field programmable gate array (FPGA)
• Application specific integrated circuit (ASIC)
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Hardware
• Usually difficult to design and implement compared to software
– Hardware description languages can make this easier
• Necessary (all software runs on hardware)
• High performance
• Low power
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Hardware/software rules of thumb
• If you can do it in software, do it in software
– However, some things can’t be done in a sane way with
software
• If you can’t do it in software but you can do it with an HDL, do it
with an HDL
– Sometimes the results of automation aren’t good enough
• If you’re tired, don’t do hardware implementation
– Software design errors usually mean wasted time
– Hardware design errors often mean fried chips
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Embedded systems
• Special-purpose computers, computers within devices which are
generally not seen to be computers
• Larger market than general-purpose computers by volume and
monetary value
• Microcontrollers rule
• Cool application-specific optimizations
– Power
– Size
– Reliability
– Hard deadlines
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Market
• How large is the semiconductor market?
• $164.4×109 for 2003 and growing fast
– Semiconductor Industry Association
• $213×109 in 2004
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Market
• How large is the semiconductor market?
• $164.4×109 for 2003 and growing fast
– Semiconductor Industry Association
• $213×109 in 2004
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Market
• How large is the semiconductor market?
• $164.4×109 for 2003 and growing fast
– Semiconductor Industry Association
• $213×109 in 2004
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Digital and analog signals
+3.3
V
0
time (µs)
• Analog: Continuously varying signal
• Digital: Discrete values, assumed instantaneous transition
• In reality, digital assumption is approximation
• Use thresholds
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Digital and analog signals
+3.3
V
0
time (µs)
• Analog: Continuously varying signal
• Digital: Discrete values, assumed instantaneous transition
• In reality, digital assumption is approximation
• Use thresholds
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Digital and analog signals
+3.3
V
0
time (µs)
• Analog: Continuously varying signal
• Digital: Discrete values, assumed instantaneous transition
• In reality, digital assumption is approximation
• Use thresholds
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Digital and analog signals
+3.3
V
0
high
low
undefined
time (µs)
• Analog: Continuously varying signal
• Digital: Discrete values, assumed instantaneous transition
• In reality, digital assumption is approximation
• Use thresholds
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Digital voltage regeneration
VOUT
3.3
0VIN 3.30
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Digital voltage regeneration
VOUT
3.3
0VIN 3.30
Error in input appears on output
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Digital voltage regeneration
VOUT
3.3
0VIN 3.30
Voltage regeneration hides input variation
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Boolean algebra
• The only values are 0 (or false) and 1 (or true)
• One can define operations/functions/gates
– Boolean values as input and output
• A truth table enumerates output values for all input value
combinations
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AND
a b a · b
0 0 0
0 1 0
1 0 0
1 1 1
ba a b
a AND b = a ∧ b = a · b = a b
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OR
a b a + b
0 0 0
0 1 1
1 0 1
1 1 1
ab a + b
a OR b = a ∨ b = a + b
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NOT
a a
0 1
1 0
a a
NOT a = a’ = a
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Combinational vs. sequential logic
clock
plain old combinational logicq
D flip−flopsa b
a+ b+
• No feedback between inputs and outputs – combinational
– Outputs a function of the current inputs, only
• Feedback – sequential
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Combinational vs. sequential logic
clock
plain old combinational logicq
D flip−flopsa b
a+ b+
• No feedback between inputs and outputs – combinational
– Outputs a function of the current inputs, only
• Feedback – sequential
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Combinational vs. sequential logic
clock
plain old combinational logicq
D flip−flopsa b
a+ b+
• No feedback between inputs and outputs – combinational
– Outputs a function of the current inputs, only
• Feedback – sequential
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Sequential logic
• Outputs depend on current state and (maybe) current inputs
• Next state depends on current state and input
• For implementable machines, there are a finite number of states
• Synchronous
– State changes upon clock event (transition) occurs
• Asynchronous
– State changes upon inputs change, subject to circuit delays
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Summary
• Brief overview
• Administrative stuff
• Introduction and definitions
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Reading assignment (for next class)
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Sections 1.1, 2.1, and 2.2
• CMOS handout from M. M. Mano and C. R. Kime, Web
supplements to Logic and Computer Design Fundamentals.
Prentice-Hall, Englewood Cliffs, NJ, 2004.
http://www.writphotec.com/mano/Supplements
• Read these by the next class
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Computer geek culture references
• Zi+1 = Z2i+K
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Mandelbrot set display code
threshold = 1000
iter = 500
def f(c, iter):
a = (0 + 0j)
for i in xrange(iter):
a = a**2 + c
if abs(a) > threshold:
break
return a
desc = [[complex(x, y) for x in xfrange(-2, 2, 0.0015)]
for y in xfrange(1, -1, -0.0015)]
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Mandelbrot set image produced by code
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Computers enabled many inventions
• Simulation, automation, knowledge discovery
• In astrophysics, chemistry, biology, medicine, etc.
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Today’s goals
• Adminstrative stuff
• Review
• Combinational logic design example
• Understand switch model and CMOS
• Be capable of manipulating Boolean formulas
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Possible grading scheme
• 15% homeworks
• 35% labs
• 20% midterm exam
• 30% final exam
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Grading
Some requested additional homework weight
• 20% homeworks
• 35% labs
• 18% midterm exam
• 27% final exam
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Planned schedule
• Mondays: Labs assigned and collected
• Wednesdays: Homeworks collected and assigned
• Friday’s class will normally focus on the lab and homework of the
week, and will be given by Zhenyu Gu
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Review
• What is a truth table?
• Combinational vs. sequential logic?
• Symbol and notation for AND, OR, NOT?
• Other gates also exist, e.g., NAND, NOR, XOR, XNOR
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Case study of simple combinational logic design
Seven-segment display
• Given: A four-bit binary input
• Display a decimal digit ranging from zero to nine
• Use a seven-segment display
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Case study of simple combinational logic design
Seven-segment display
• Given: A four-bit binary input
• Display a decimal digit ranging from zero to nine
• Use a seven-segment display
L1
L2
L3
L4
L5
L6
L7
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Case study – Seven-segment
i3 i2 i1 i0 dec
0 0 0 0 00 0 0 1 10 0 1 0 20 0 1 1 30 1 0 0 40 1 0 1 50 1 1 0 60 1 1 1 71 0 0 0 81 0 0 1 9
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Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 0 1 0 1 1
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Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 0 1 0 1 1
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Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 0 1 0 1 1
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Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 0 1 0 1 1
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Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 0 1 0 1 1
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Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 0 1 0 1 1
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Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 0 1 0 1 1
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Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 0 1 0 1 1
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Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 0 1 0 1 1
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Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 0 1 0 1 1
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Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 0 1 0 1 1
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Implement L4
i3 i2 i1 i0 dec L4
0 0 0 0 0 1
0 0 0 1 1 0
0 0 1 0 2 0
0 0 1 1 3 0
0 1 0 0 4 1
0 1 0 1 5 1
0 1 1 0 6 1
0 1 1 1 7 0
1 0 0 0 8 1
1 0 0 1 9 1
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L4 implementation
L4
i3
i0
i0
i1
i1
i2
i2
In a future lecture, I’ll explain how to do this sort of design.
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L4 implementation
L4
i3
i0
i0
i1
i1
i2
i2
In a future lecture, I’ll explain how to do this sort of design.
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Switch-based design representation
• A switch shorts or opens two points dependant on a control signal
• Used as models for digital transistors
• Why is using normally open and normally closed particularly
useful for CMOS?
– NMOS and PMOS transistors easy to model
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Switch-based design representation
• A switch shorts or opens two points dependant on a control signal
• Used as models for digital transistors
• Why is using normally open and normally closed particularly
useful for CMOS?
– NMOS and PMOS transistors easy to model
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Switch-based definitions
control
normally openswitch
true
closed switch
false
open switch
control
switch
open switch
closed switch
normally closed
true
false
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Microwave control example
haltmicrowave
water vaporsensed
at least fiveminutes elapsed
cancel buttonpressed
true
• What happens if the cancel button is not pressed and five
minutes haven’t yet passed?
– The output value is undefined.
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Microwave control example
haltmicrowave
water vaporsensed
at least fiveminutes elapsed
cancel buttonpressed
true
• What happens if the cancel button is not pressed and five
minutes haven’t yet passed?
– The output value is undefined.
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Constraints on network output
Under all possible combinations of input values
• Each output must be connected to an input value
• No output may be connected to conflicting input values
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Switch-based AND
ba
false
output
true
Note that this requires
• Normally closed switches that transmit false signals well
• Normally open switches that transmit true signals well
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Switch-based AND
ba
false
output
true
Note that this requires
• Normally closed switches that transmit false signals well
• Normally open switches that transmit true signals well
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Relationship with CMOS
• Metal Oxide Semiconductor
• Positive and negative carriers
• Complimentary MOS
• PMOS gates are like normally closed switches that are good at
transmitting only true (high) signals
• NMOS gates are like normally open switches that are good at
transmitting only false (low) signals
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Relationship with CMOS
• Metal Oxide Semiconductor
• Positive and negative carriers
• Complimentary MOS
• PMOS gates are like normally closed switches that are good at
transmitting only true (high) signals
• NMOS gates are like normally open switches that are good at
transmitting only false (low) signals
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Relationship with CMOS
• Metal Oxide Semiconductor
• Positive and negative carriers
• Complimentary MOS
• PMOS gates are like normally closed switches that are good at
transmitting only true (high) signals
• NMOS gates are like normally open switches that are good at
transmitting only false (low) signals
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NAND gate
• Therefore, NAND and NOR gates are used in CMOS design
instead of AND and OR gates
ba
output
true
false
=
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NAND gate
• Therefore, NAND and NOR gates are used in CMOS design
instead of AND and OR gates
ba
output
true
false
=NMOS
PMOS
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Transistors
• Basic device in NMOS and PMOS (CMOS) technologies
• Can be used to construct any logic gate
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NMOS transistor
gate
silicon bulk (P)
drain (N)source (N)
oxide
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NMOS transistor
gate
silicon bulk (P)
drain (N)source (N) channeloxide
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NMOS transistor
• Metal–oxide semiconductor (MOS)
– Now, it’s actually polysilicon–oxide semiconductor
• P-type bulk silicon doped with positively charged ions
• N-type diffusion regions doped with negatively charged ions
• Gate can be used to pull a few electrons near the oxide
– Forms channel region, conduction from source to drain starts
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CMOS
• NMOS turns on when the gate is high
• PMOS just like NMOS, with N and P regions swapped
• PMOS turns on when the gate is low
• NMOS good at conducting low (0s)
• PMOS good at conducting high (1s)
• Use NMOS and PMOS transistors together to build circuits
– Complementary metal oxide silicon (CMOS)
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CMOS NAND gate
VSS
VDD
A B
Z
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CMOS NAND gate
VSS
VDD
A B
Z
PMOS
NMOS
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CMOS NAND gate
VSS
VDD
A B
Z
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CMOS NAND gate
VSS
VDD
A B
Z
pull−up network
pull−down network
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CMOS NAND gate layout
VSS
VDD
b
a z
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CMOS inverter operation
VDD
VSS
A B
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CMOS inverter operation
VDD
VSS
A=0B=1
A B
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CMOS inverter operation
VDD
VSS
A B
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CMOS inverter operation
VDD
VSS
A=1
B=0A B
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NAND operation
VSS
VDD
A B
Z
121
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NAND operation
VSS
VDD
A B
Z
Z=1
B=0A=0
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NAND operation
VSS
VDD
A B
Z
123
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NAND operation
B=1
VSS
VDD
A B
Z
Z=1A=0
blocked
124
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NAND operation
VSS
VDD
A B
Z
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NAND operation
A=1
VSS
VDD
A B
Z
Z=1
B=0
blocked
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NAND operation
VSS
VDD
A B
Z
127
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NAND operation
Z=0
B=1
A=1
VSS
VDD
A B
Z
128
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NOR operation
VSS
VDD
A B
Z
129
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NOR operation
VSS
VDD
A B
Z
Z=1
B=0
A=0
130
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NOR operation
VSS
VDD
A B
Z
131
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NOR operation
B=1Z=0
VSS
VDD
A B
Z
blocked
A=0
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NOR operation
VSS
VDD
A B
Z
133
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NOR operation
A=1Z=0
VSS
VDD
A B
Z
B=0
blocked
134
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NOR operation
VSS
VDD
A B
Z
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NOR operation
A=1 B=1Z=0
VSS
VDD
A B
Z
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Threshold effect on NMOS/PMOS transistors
• Recall that NMOS transmits low values easily. . .
• . . . transmits high values poorly
• PMOS transmits high values easily. . .
• . . . transmits low values poorly
• This is due to the effect of the transistors’ thresholds
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Threshold effect on NMOS/PMOS transistors
• VT, or threshold voltage, is commonly 0.7 V
• NMOS conducts when VGS > VT
• PMOS conducts when VGS < −VT
• What happens if an NMOS transistor’s source is high?
• Or a PMOS transistor’s source is low?
• Alternatively, if one states that VTN = 0.7 V and VTP = −0.7 V
then NMOS conducts when VGS > VTN and PMOS conducts
when VGS < VTP
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NMOS transistor
gate
silicon bulk (P)
drain (N)source (N)
oxide
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Threshold effect on NMOS/PMOS transistors
• If an NMOS transistor’s input were VDD (high), for VGS > VTN,
the gate would require a higher voltage than VDD
• If an PMOS transistor’s input were VSS (low), for VGS < VTP, the
gate would require a lower voltage than VSS
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Implications of threshold
VSS
VDD
A B
Z
NAND/NOR easy to build in CMOS
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Implications of threshold
AND/OR requires more area, power, time
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CMOS transmission gates (switches)
• NMOS is good at transmitting 0s
– Bad at transmitting 1s
• PMOS is good at transmitting 1s
– Bad at transmitting 0s
• To build a switch, use both: CMOS
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CMOS transmission gate (TG)
B
C
A
C
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CMOS transmission gate (TG)
B
C
A
C
C = 1
C = 0
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CMOS transmission gate (TG)
B
C
A
C
C = 1
C = 0
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CMOS transmission gate (TG)
B
C
A
C
C = 1
C = 0
B = A
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CMOS transmission gate (TG)
B
C
A
C
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CMOS transmission gate (TG)
B
C
A
C
C = 0
C = 1
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CMOS transmission gate (TG)
B
C
A
C
C = 0
C = 1blocked
blocked
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CMOS transmission gate (TG)
B
C
A
C
C = 0
C = 1blocked
blockedB =High-Z
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Other TG diagram
B
C
A
C
A B
C
C
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What can we build with TGs?
• Anything. . . try some examples.
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Summary
• Administrative details
• Combinational logic design example
• Logic gates can be implemented with physical devices, e.g,
CMOS
• Underlying technology influences higher-level representation
– NAND, NOR vs. AND, OR
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Reading assignment
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Section 2.3
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Computer geek culture reference
• http://slashdot.org
• http://www.python.org
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Today’s topics
• Administrative details
• Quiz (ungraded)
• Finish CMOS and basic gates
• Boolean algebra
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Quiz (ungraded)
• What is the relationship between a truth table and a Boolean
formula?
• What is the relationship between a Boolean formula and a
combinational circuit?
• What quirks does the CMOS implementation technology have?
• What is voltage regeneration?
• What practices are unsafe in switch-based design? Why?
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Boolean algebra
• Set of elements, B
• Binary operators, [ AND, ∧, *, · ], [ OR, ∨, + ]
– We’ll prefer · and +
– · frequently omitted
• Unary operator, [ NOT, ’, o ]
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Axioms of Boolean algebra
∃x,y∈ B s.t. x 6= y
closure ∀x,y∈ B xy∈ B
x+y∈ B
commutative laws ∀x,y∈ B xy= yx
x+y = y+x
identities 0,1 ∈ B,∀x∈ B x1 = x
x+0 = x
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Axioms of Boolean algebra
∃x,y∈ B s.t. x 6= y
distributive laws ∀x,y,z∈ B x+(yz) = (x+y)(x+z)
x(y+z) = xy+xz
complement x∈ B xx = 0
x+ x = 1
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De Morgan’s laws
(a+b) = a b
ab = a + b
f (x1,x2, . . . ,xn, ·,+) = f (x1 , x2 , . . . , xn ,+, ·)
• Those xs could be functions
• Apply in stages
– Top-down
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De Morgan’s laws example
a+bc
a · (bc)
a · (b + c)
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Representations of Boolean functions
• Truth table
• Expression using only ·, +, and ’
• Symbolic
• Karnaugh map
– More useful as visualization and optimization tool
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Review: AND
a b a b
0 0 0
0 1 0
1 0 0
1 1 1
ba a b
a AND b = a b
Will show Karnaugh map later
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Review: OR
a b a + b
0 0 0
0 1 1
1 0 1
1 1 1
ab a + b
a OR b = a + b
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Review: NOT
a a
0 1
1 0
a a
NOT a = a
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Different representations possible
A
B
C
D T
2
T 1
Z
Z = ((C+D) B) A
Z
A
B
C
D
Z = (C+D) A B
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Different representations possible
A
B
C
D T
2
T 1
Z
Z = ((C+D) B) A
Z
A
B
C
D
Z = (C+D) A B
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Simplifying logic functions
• Minimize literal count (related to gate count, delay)
• Minimize gate count
• Minimize levels (delay)
• Trade off delay for area
– Sometimes no real cost
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Proving theorems = simplification
Prove XY+XY = X
XY+XY = X(Y+ Y ) distributive law
X(Y + Y ) = X(1) complementary law
X(1) = X identity law
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Proving theorems = simplification
Prove X +XY = X
X +XY = X1+XY identity law
X1+XY = X(1+Y) distributive law
X(1+Y) = X1 identity law
X1 = X identity law
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Literals
• Each appearance of a variable (complement) in expression
• Fewer literals usually implies simpler to implement
• E.g., Z = ABC+ A B+ A BC + BC
– Three variables, ten literals
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NANDs and NORs
• Can be implemented in CMOS
• X NAND Y = XY
• X NOR Y = X +Y
• Do we need inverters?
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Summary
• Administrative details
• Finished CMOS and basic gates
• Boolean algebra
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Reading assignment
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Sections 2.4 and 2.5
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Next lectures
• Karnaugh maps
• Visual minimization
• We’ll also learn the optimal Quine-McCluskey method
– Optimal two-level minimization is fun!
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Breadboard
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Breadboard
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Breadboard
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Breadboard
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Breadboard
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Breadboard
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Breadboard
74LS00
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Logic probe
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Light emitting diodes (LEDs)
Never drive an LED without a series current-limiting resistor
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Light emitting diodes (LEDs)
Never drive an LED without a series current-limiting resistor
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Light emitting diodes (LEDs)
Never drive an LED without a series current-limiting resistor
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Light emitting diodes (LEDs)
flat
rounded
Never drive an LED without a series current-limiting resistor
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Light emitting diodes (LEDs)
flat
rounded
330Ω
Never drive an LED without a series current-limiting resistor
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Resistors
• Color code sheet in your orange box
• Colored bands indicate numbers
• Black (0), brown (1), red (2), orange (3), yellow (4), etc.
• What is Orange, Orange, Black?
• What about Orange, Orange, Brown?
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Transistor to transistor logic (TTL)
• Consumes more power than CMOS
• Generally more difficult to damage than CMOS (ESD)
• Inputs “float high”
• What does this imply?
• Why is it good for prototyping?
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Guidelines
• Connect all inputs to some signal, best not to rely on floating
– Good practice for CMOS, where it’s essential
• Color-code wiring in complicated circuits
– Learn how to strip wire
• Don’t cross wire over chips
• Double-check VDD and VSSwiring
• Watch for hot chips
• Use current-limiting resistors on LEDs
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Circuit diagram example
input circuit
ix
510Ω
green
output circuit
330Ω
330Ω
qx red
i0i1
i2q0
13
12
11
10
9
8
(A) 74LS00
A
A
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Incomplete circuit diagram example
i0i1
i2q0
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Summary
• Demo to put prototyping in context
• Breadboarding lecture and demo
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Prototypeing trends
• Surface mount
• FPGAs
• Virtual prototypeing
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Computer geek culture references
• http://www.digikey.com
• http://www.mouser.com
• http://www.jameco.com
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Summary
• Transmission gates review
• Two-level logic
• Karnaugh maps
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CMOS transmission gate (TG)
B
C
A
C
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CMOS transmission gate (TG)
B
C
A
C
C = 1
C = 0
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CMOS transmission gate (TG)
B
C
A
C
C = 1
C = 0
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CMOS transmission gate (TG)
B
C
A
C
C = 1
C = 0
B = A
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CMOS transmission gate (TG)
B
C
A
C
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CMOS transmission gate (TG)
B
C
A
C
C = 0
C = 1
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CMOS transmission gate (TG)
B
C
A
C
C = 0
C = 1blocked
blocked
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CMOS transmission gate (TG)
B
C
A
C
C = 0
C = 1blocked
blockedB =High-Z
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Other TG diagram
B
C
A
C
A B
C
C
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TG examplea a b b
1
0 f
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Impact of control on input
1
0
0
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Impact of control on input
1
0
0
=
TG’s resistance
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Impact of control on input
=
TG’s resistance
1
1
a
0
0
0
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Impact of control on input
=
=
a’s internal resistanceTG’s resistance
TG’s resistance
1
1
a
0
0
0
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Logic minimization motivation
• Want to reduce area, power consumption, delay of circuits
• Hard to exactly predict circuit area from equations
• Can approximate area with SOP cubes
• Minimize number of cubes and literals in each cube
• Algebraic simplification difficult
– Hard to guarantee optimality
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Logic minimization motivation
• K-maps work well for small problems
– Too error-prone for large problems
– Don’t ensure optimal prime implicant selection
• Quine-McCluskey optimal and can be run by a computer
– Too slow on large problems
• Some advanced heuristics usually get good results fast on large
problems
• Want to learn how these work and how to use them?
• Take Advanced Digital Logic Design
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Boolean function minimization
• Algebraic simplification
– Not systematic
– How do you know when optimal solution has been reached?
• Optimal algorithm, e.g., Quine-McCluskey
– Only fast enough for small problems
– Understanding these is foundation for understanding more
advanced methods
• Not necessarily optimal heuristics
– Fast enough to handle large problems
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Karnaugh maps (K-maps)
• Fundamental attribute is adjacency
• Useful for logic synthesis
• Helps logic function visualization
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Karnaugh maps
0 1aa
0 1
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Karnaugh maps
0 1aa
0 1
b
a
00 01
10 11
01
1a
b0
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Karnaugh maps
0 1aa
0 1
b
a
00 01
10 11
01
1a
b0
bc
0
1a
c
a
b10110100
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Karnaugh maps
0 1aa
0 1
b
a
00 01
10 11
01
1a
b0
bc
0
1a
c
a
b10110100
ab
1011010000
01
11
10
cd
a
b
c
d
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Sum of products (SOP)
0 110
1 10
0
bf(a,b)
a
(
a b)
+(a b)
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Sum of products (SOP)
0 110
1 10
0
bf(a,b)
a
(
a b)
+(a b)
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Sum of products (SOP)
0 110
1 10
0
bf(a,b)
a
(
a b)
+(a b)
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Sum of products (SOP)
0 110
1 10
0
bf(a,b)
a
(
a b)
+(a b)
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Implicants
0
1
0010
1 1 1 1
101 11 10
f(a,b,c)
a
bc
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Implicants
implicant
0
1
0010
1 1 1 1
101 11 10
f(a,b,c)
a
bc
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Implicants
implicant
0
1
0010
1 1 1 1
101 11 10
f(a,b,c)
a
bc
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Implicants
implicant
0
1
0010
1 1 1 1
101 11 10
f(a,b,c)
a
bc
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Implicants
prime implicant
0
1
0010
1 1 1 1
101 11 10
f(a,b,c)
a
bc
Prime implicants are not covered by other implicants
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Implicants
essential prime implicant
0
1
0010
1 1 1 1
101 11 10
f(a,b,c)
a
bc
Essential prime implicants uniquely cover minterms
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Implicants
0
1
0010
1 1 1 1
101 11 10
f(a,b,c)
a
bc
Essential prime implicants uniquely cover minterms
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Implicants
0
1
0010
1 1 1 1
101 11 10
f(a,b,c)
a
bc
Essential prime implicants uniquely cover minterms
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K-map example
• Minimize f (a,b,c,d) = ∑(1,3,8,9,10,11,13)
• f(a, b, c, d) = a b + b d+a c d
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K-map example
• Minimize f (a,b,c,d) = ∑(1,3,8,9,10,11,13)
• f(a, b, c, d) = a b + b d+a c d
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K-map simplification technique
For all minterms
• Find maximal groupings of 1’s and X’s adjacent to that minterm.
• Remember to consider top/bottom row, left/right column, and
corner adjacencies.
• These are the prime implicants.
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K-map simplification technique
• Revisit the 1’s elements in the K-map.
• If covered by single prime implicant, the prime is essential, and
participates in final cover.
• The 1’s it covers do not need to be revisited.
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K-map simplification technique
• If there remain 1’s not covered by essential prime implicants,
• Then select the smallest number of prime implicants that cover
the remaining 1’s.
• This can be difficult for complicated functions.
• Will present an algorithm for this in a future lecture.
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Product of sums (POS)
0 110
1 10
0
bf(a,b)
a
(a +b)·(
a+ b)
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Product of sums (POS)
0 110
1 10
0
bf(a,b)
a
(a +b)·(
a+ b)
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Product of sums (POS)
0 110
1 10
0
bf(a,b)
a
(a +b)·(
a+ b)
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Product of sums (POS)
0 110
1 10
0
bf(a,b)
a
(a +b)·(
a+ b)
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Product of sums (POS)
0 110
1 10
0
bf(a,b)
a
(a +b)·(
a+ b)
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POS K-map techniques
• Direct reading by covering zeros and inverting variables
Or
• Invert function
• Do SOP
• Invert again
• Apply De Morgan’s laws
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POS K-map example
• Minimize f (a,b,c) = ∏(2,4,5,6)
• f (a,b,c) = (b +c)(a +b)
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POS K-map example
• Minimize f (a,b,c) = ∏(2,4,5,6)
• f (a,b,c) = (b +c)(a +b)
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
b c
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
b d
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
abd
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
bcd
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
abc
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
acd
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
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SOP from Karnaugh map
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)cd
ab
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Six-variable K-map example
z(a,b,c,d,e, f ) = ∑(2,8,10,18,24,26,34,37,42,45,50,53,58,61)
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Six-variable K-map exampleCD
EF
CD EF
AB =00
AB =01
00 01 11 10 00
01
11
10
00 01 11 10 00
01
11
10
0 4 12 8
1 5 13 9
3 7 15 11
2 6 14 10
16 20 28 24
17 21 29 25
19 23 31 27
18 22 30 26
CD EF
AB =11
00 01 11 10 00
01
11
10
48 52 60 56
49 53 61 57
51 55 63 59
50 54 62 58
CD EF
AB =10
00 01 11 10 00
01
11
10
32 36 44 40
33 37 45 41
35 39 47 43
34 38 46 42
CD EF
CD EF
AB =00
AB =01
00 01 11 10
00
01
11
10
00 01 11 10 00
01
11
10
CD EF
AB =11
00 01 11 10 00
01
11
10
CD EF
AB =10
00 01 11 10
00
01
11
10
1
1 1
1
1 1
1 1
1 1
1 1
1 1
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Six-variable K-map example
z(a,b,c,d,e, f ) = d e f +ad e f + a C d f
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DON’T CARE logic
• All specified Boolean values are 0 or 1
• However, during design some values may be unspecified
– Don’t care values (×)
• ×s allow circuit optimization, i.e.,
– Incompletely specified functions allow optimization
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DON’T CARE values
0 110
1 1a
bf(a,b)
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DON’T CARE values
0
0
0 110
1 1a
bf(a,b)
Can let the undefined values be zero
• Correct. . .
• . . . however, complicated
•(
a b)
+(a b)
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DON’T CARE values
0
0
0 110
1 1a
bf(a,b)
Can let the undefined values be zero
• Correct. . .
• . . . however, complicated
•(
a b)
+(a b)
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DON’T CARE values
0 110
1 1a
bf(a,b)
Instead, leave these values undefined (×)
• Also called DON’T CARE values
• Allows any function implementing the specified values to be used
• E.g., could use(
a b)
+(a b)
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DON’T CARE values
0 110
1 1a
bf(a,b)
Instead, leave these values undefined (×)
• Also called DON’T CARE values
• Allows any function implementing the specified values to be used
• E.g., could use(
a b)
+(a b)
• However, best to use simpler 1
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Don’t care K-map example
• Minimize f (a,b,c,d) = ∑(1,3,8,9,10,11,13)+d(5,7,15)
• f (a,b,c,d) = a b +d
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Don’t care K-map example
• Minimize f (a,b,c,d) = ∑(1,3,8,9,10,11,13)+d(5,7,15)
• f (a,b,c,d) = a b +d
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Two-level logic is necessary
0 110
1 1
0
0
bf(a,b)
a
Some Boolean functions can not be represented with one logic level
(
a b)
+(a b)
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Two-level logic is necessary
0 110
1 1
0
0
bf(a,b)
a
Some Boolean functions can not be represented with one logic level
(
a b)
+(a b)
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Two-level logic is necessary
0 110
1 1
0
0
bf(a,b)
a
Some Boolean functions can not be represented with one logic level
(
a b)
+(a b)
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Two-level logic is necessary
0 110
1 1
0
0
bf(a,b)
a
Some Boolean functions can not be represented with one logic level
(
a b)
+(a b)
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Two-level logic is necessary
0 110
1 1
0
0
bf(a,b)
a
Some Boolean functions can not be represented with one logic level
(
a b)
+(a b)
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Two-level logic is sufficient
0 110
1 1
0
0
bf(a,b)
a
• All Boolean functions can be represented with two logic levels
• Given k variables, 2K minterm functions exist
• Select arbitrary union of minterms
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Two-level well-understood
• As we will see later, optimal minimization techniques known for
two-level
• However, optimal two-level solution may not be optimal solution
– Sometimes a suboptimal solution to the right problem is better
than the optimal solution to the wrong problem
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Two-level sometimes impractical
00 11 10010 1
1
1
01
00
11
10 1
0
0
0
00
0 0
1
1 1
1
f(a,b,c,d)cd
ab
Consider a 4-term XOR (parity) gate: a⊕b⊕c⊕d(
a b c d)
+(
a b c d)
+(
a b c d)
+(a b c d)+(a b c d)+(
a b c d)
+(
a b c d)
+(
a b c d)
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Two-level sometimes impractical
00 11 10010 1
1
1
01
00
11
10 1
0
0
0
00
0 0
1
1 1
1
f(a,b,c,d)cd
ab
Consider a 4-term XOR (parity) gate: a⊕b⊕c⊕d(
a b c d)
+(
a b c d)
+(
a b c d)
+(a b c d)+(a b c d)+(
a b c d)
+(
a b c d)
+(
a b c d)
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Two-level weakness
• Two-level representation is exponential
• However, it’s a simple concept
– Is ∑ni xi odd?
• Problem with representation, not function
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Two-level weakness
Two-level representations also have other weaknesses
• Conversion from SOP to POS is difficult
– Inverting functions is difficult
– ·-ing two SOPs or +ing two POSs is difficult
• Neither general POS or SOP are canonical
– Equivalence checking difficult
• POS satisfiability ∈ NP-complete
– Basically, it can’t be solved quickly for large problem instances
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Summary
• Transmission gate review
• Two-level logic
• Karnaugh maps
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Reading assignment
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Section 2.6
• Also read TTL reference, D. Lancaster, TTL Cookbook. Howard
W. Sams & Co., Inc., 1974, as needed
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Today’s topics
• Lab and lecture comments
• Review: Minimization overview
• Review: Karnaugh map SOP minimization
• POS using SOP K-map trick
• Quine-McCluskey optimal two-level minimization method
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Lab and lecture comments
• Anybody falling behind?
• If something isn’t making sense, stop me and I’ll elaborate using
the chalkboard
– I’m glad to do it!
• Lab expectations (lab two and above)
– Complete schematics
– Easy to debug, color-coded wiring
– Terse but clear description
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Review: Minimization techniques
Advantages and disadvantages?
• Algebraic manipulation
• Karnaugh maps
• Quine-McCluskey
• Advanced topic: Kernel extraction
• Advanced topic: Heuristic minimization, e.g., Espresso
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Deriving POS
00 11 1001
01
00
11
10
1 1 1
11
11 1
0 0
0
0 0
10
0
f(a,b,c,d)ab
cd
Find SOP form for zeros:
f = abz + cd+ a bd
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Deriving POS
Apply De Morgan’s theorem
f = abd + c d+ a bd (1)
f = abd + c d+ a bd (2)
f =(
abd)
· (cd) ·(
a bd)
(3)
f =(
a + b +d)(
c+ d)(
a+b+ d)
(4)
• Advanced topic: Read the POS expression directly from the
Karnaugh map
– More difficult
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Quine-McCluskey two-level logic minimization
• Compute prime implicants with a well-defined algorithm
– Start from minterms
– Merge adjacent implicants until further merging impossible
• Select minimal cover from prime implicants
– Unate covering problem
• What is happening?
– ab+ab = a
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Computing prime implicants
0000
000100101000
10011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
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Computing prime implicants
000X0000
000100101000
10011010
1111
11011110
0000
0001
0000 000X
0001
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
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Computing prime implicants
000X0000
000100101000
10011010
1111
11011110
0000
0001
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
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Computing prime implicants
00X0000X0000
000100101000
10011010
1111
11011110
0000
00010010
000000X0
0010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
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Computing prime implicants
00X0000X0000
000100101000
10011010
1111
11011110
0000
00010010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
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Computing prime implicants
00X0X000
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
0000
X000
1000
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
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Computing prime implicants
00X0X000
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
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Computing prime implicants
00X0X000X001
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
1001
X0010001
1001
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
300
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Computing prime implicants
00X0X000X001
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
1001
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
301
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Computing prime implicants
00X0X000X001X010
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
0010 X010
1010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
302
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Computing prime implicants
00X0X000X001X010
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
303
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Computing prime implicants
00X0X000X001X010100X
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
1000 100X
1001
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
304
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Computing prime implicants
00X0X000X001X010100X
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
305
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Computing prime implicants
00X0X000X001X010100X10X0
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
100010X0
1010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
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Computing prime implicants
00X0X000X001X010100X10X0
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
307
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Computing prime implicants
00X0X000X001X010100X10X01X01
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
100110101101
1001 1X01
1101
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
308
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Computing prime implicants
00X0X000X001X010100X10X01X01
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
100110101101
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
309
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Computing prime implicants
00X0X000X001X010100X10X01X011X10
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
1001101011011110
1010 1X10
1110∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
310
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Computing prime implicants
00X0X000X001X010100X10X01X011X10
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
1001101011011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
311
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Computing prime implicants
00X0X000X001X010100X10X01X011X10111X
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
1111
110111101111
111X1110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
312
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Computing prime implicants
00X0X000X001X010100X10X01X011X10111X
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
313
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Computing prime implicants
00X0X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
1111
110111101111
11X11101
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
314
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Computing prime implicants
00X0X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
315
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Computing prime implicants
X00X00X0X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X
000100101000 100X
10011010
1111
11011110
000X
100X
X00X
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
316
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Computing prime implicants
X00X00X0X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X
000100101000 100X
10011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
317
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Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0
000100101000 100X
10X010011010
1111
11011110
00X0
10X0
X0X0
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
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Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0
000100101000 100X
10X010011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
319
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Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0X000X0010001
00101000 100X
10X010011010
1111
11011110
X000X001
X00X
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
320
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Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0X000X0010001
00101000 100X
10X010011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
321
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Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0X000X0010001
00101000
X010100X10X0
10011010
1111
11011110
X000
X010
X0X0
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
322
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Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0X000X0010001
00101000
X010100X10X0
10011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
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Summary
• Review: Minimization overview
• Review: Karnaugh map SOP minimization
• POS using SOP K-map trick
• Quine-McCluskey optimal two-level minimization method
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Next lecture – More advanced building blocks
• Encoders and decoders
• MUXs
• Advanced TG techniques
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Reading assignment
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Sections 2.7–2.10
• Sections 4.1–4.5
• Section 4.6 (decoders and multiplexers only)
• M. M. Mano and C. R. Kime, Web supplements to Logic and
Computer Design Fundamentals. Prentice-Hall, Englewood
Cliffs, NJ, 2004. http://www.writphotec.com/mano/Supplements
handout on tabular method (Quine-McCluskey)
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Additional references
• If QM doesn’t click, please also see the following references
• R. H. Katz, Contemporary Logic Design. The
Benjamin/Cummings Publishing Company, Inc., 1994: pp. 85–88
• J. P. Hayes, Introduction to Digital Logic Design. Addison-Wesley,
Reading, MA, 1993 pp. 320, 321
• You can get these from me or the library
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Computer geek culture reference
• http://www.deepchip.com
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Today’s topics
• Ungraded quiz
• ∑ for minterms, ∏ for maxterms
• Review: Quine-McCluskey
• Prime implicant selection in Quine-McCluskey
• Encoders and decoders
• Review: Transmission gates
• Multiplexers and demultiplexers
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Review: Quine-McCluskey two-level logic
minimization
• Compute prime implicants with a well-defined algorithm
– Start from minterms
– Merge adjacent implicants until further merging impossible
• Select minimal cover from prime implicants
– Unate covering problem
• What is happening?
– ab+ab = a
330
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Review: Computing prime implicants
0000
000100101000
10011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
331
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Review: Computing prime implicants
000X0000
000100101000
10011010
1111
11011110
0000
0001
0000 000X
0001
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
332
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Review: Computing prime implicants
000X0000
000100101000
10011010
1111
11011110
0000
0001
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
333
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Review: Computing prime implicants
00X0000X0000
000100101000
10011010
1111
11011110
0000
00010010
000000X0
0010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
334
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Review: Computing prime implicants
00X0000X0000
000100101000
10011010
1111
11011110
0000
00010010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
335
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Review: Computing prime implicants
00X0X000
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
0000
X000
1000
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
336
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Review: Computing prime implicants
00X0X000
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
337
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Review: Computing prime implicants
00X0X000X001
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
1001
X0010001
1001
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
338
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Review: Computing prime implicants
00X0X000X001
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
1001
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
339
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Review: Computing prime implicants
00X0X000X001X010
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
0010 X010
1010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
340
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Review: Computing prime implicants
00X0X000X001X010
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
341
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Review: Computing prime implicants
00X0X000X001X010100X
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
1000 100X
1001
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
342
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Review: Computing prime implicants
00X0X000X001X010100X
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
343
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Review: Computing prime implicants
00X0X000X001X010100X10X0
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
100010X0
1010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
344
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Review: Computing prime implicants
00X0X000X001X010100X10X0
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
345
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Review: Computing prime implicants
00X0X000X001X010100X10X01X01
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
100110101101
1001 1X01
1101
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
346
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Review: Computing prime implicants
00X0X000X001X010100X10X01X01
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
100110101101
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
347
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Review: Computing prime implicants
00X0X000X001X010100X10X01X011X10
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
1001101011011110
1010 1X10
1110∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
348
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Review: Computing prime implicants
00X0X000X001X010100X10X01X011X10
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
1001101011011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
349
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Review: Computing prime implicants
00X0X000X001X010100X10X01X011X10111X
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
1111
110111101111
111X1110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
350
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Review: Computing prime implicants
00X0X000X001X010100X10X01X011X10111X
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
351
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Review: Computing prime implicants
00X0X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
1111
110111101111
11X11101
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
352
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Review: Computing prime implicants
00X0X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000
000100101000
10011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
353
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Review: Computing prime implicants
X00X00X0X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X
000100101000 100X
10011010
1111
11011110
000X
100X
X00X
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
354
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Review: Computing prime implicants
X00X00X0X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X
000100101000 100X
10011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
355
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Review: Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0
000100101000 100X
10X010011010
1111
11011110
00X0
10X0
X0X0
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
356
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Review: Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0
000100101000 100X
10X010011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
357
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Review: Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0X000X0010001
00101000 100X
10X010011010
1111
11011110
X000X001
X00X
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
358
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Review: Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0X000X0010001
00101000 100X
10X010011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
359
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Review: Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0X000X0010001
00101000
X010100X10X0
10011010
1111
11011110
X000
X010
X0X0
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
360
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Review: Computing prime implicants
X00XX0X000X0
X000X001X010100X10X01X011X10111X11X1
000X0000
000100101000
10011010
1111
11011110
0000 000X00X0X000X0010001
00101000
X010100X10X0
10011010
1111
11011110
∑ = 4
∑ = 0
∑ = 1
∑ = 2
∑ = 3
361
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Definition: Unate covering
Given a matrix for which all entries are 0 or 1, find the minimum
cardinality subset of columns such that, for every row, at least one
column in the subset contains a 1.
I’ll give an example
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Definition: Unate covering
Given a matrix for which all entries are 0 or 1, find the minimum
cardinality subset of columns such that, for every row, at least one
column in the subset contains a 1.
I’ll give an example
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Prime implicant selection
0X001X X00 X11
100
111
011
010
000 1 1
1 1
1 1
1
1
On-setminterms
Prime implicants
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Prime implicant selection
0X001X X00 X11
100
111
011
010
000 1 1
1 1
1 1
1
1
On-setminterms
these... cover
Use these to...Prime implicants
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Prime implicant selection
0X001X X00 X11
100
111
011
010
000 1 1
1 1
1 1
1
1
On-setminterms
these... cover
Use these to...Prime implicants
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Prime implicant selection
0X001X X00 X11
100
111
011
010
000 1 1
1 1
1 1
1
1
On-setminterms
these... cover
Use these to...Prime implicants
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Prime implicant selection
0X001X X00 X11
100
111
011
010
000 1 1
1 1
1 1
1
1
On-setminterms
these... cover
Use these to...Prime implicants
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Cyclic core
0
0
1 1 1
111
0
00 01 11 10
1
bc
a
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Cyclic core
0
0
1 1 1
111
0
00 01 11 10
1
bc
a
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Cyclic core
0
0
1 1 1
111
0
00 01 11 10
1
bc
a
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Cyclic core
0
0
1 1 1
111
0
00 01 11 10
1
bc
a
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Cyclic core
1
1 1
1
1
1
1
1
1
1
1
1
0
0
1 1 1
111
0 011
001
010
100
101
110
0X1 01X X01 X10 1X010X
00 01 11 10
1
bc
a
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Cyclic core
1
1 1
1
1
1
1
1
1
1
1
1
0
0
1 1 1
111
0 011
001
010
100
101
110
0X1 01X X01 X10 1X010X
00 01 11 10
1
bc
a
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Cyclic core
1
1 1
1
1
1
1
1
1
1
1
1
0
0
1 1 1
111
0 011
001
010
100
101
110
0X1 01X X01 X10 1X010X
00 01 11 10
1
bc
a
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Cyclic core
1
1 1
1
1
1
1
1
1
1
1
1
0
0
1 1 1
111
0 011
001
010
100
101
110
0X1 01X X01 X10 1X010X
00 01 11 10
1
bc
a
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Implicant selection reduction
• Eliminate rows covered by essential columns
• Eliminate rows dominated by other rows
• Eliminate columns dominated by other columns
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Eliminate rows covered by essential columns
A B C
H 1
I 1 1
J 1 1
K 1 1
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Eliminate rows covered by essential columns
A B C
H 1
I 1 1
J 1 1
K 1 1
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Eliminate rows covered by essential columns
A B C
H 1
I 1 1
J 1 1
K 1 1
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Eliminate rows covered by essential columns
A B C
H 1
I 1 1
J 1 1
K 1 1
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Eliminate rows dominated by other rows
A B C
H 1
I 1 1
J 1 1
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Eliminate rows dominated by other rows
A B C
H 1
I 1 1
J 1 1
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Eliminate rows dominated by other rows
A B C
H 1
I 1 1
J 1 1
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Eliminate rows dominated by other rows
A B C
H 1
I 1 1
J 1 1
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Eliminate columns dominated by other columns
A B C
H 1
I 1 1
J 1 1
K 1
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Eliminate columns dominated by other columns
A B C
H 1
I 1 1
J 1 1
K 1
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Eliminate columns dominated by other columns
A B C
H 1
I 1 1
J 1 1
K 1
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Eliminate columns dominated by other columns
A B C
H 1
I 1 1
J 1 1
K 1
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Backtracking
• Will proceed to complete solution unless cyclic
• If cyclic, backtrack
– Try all possible options to completion
• Advanced topic: Can use a number of tricks to simplify this
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Use bound to constrain search space
• Eliminate rows covered by essential columns
• Eliminate rows dominated by other rows
• Eliminate columns dominated by other columns
• Speed improved, still ∈NP-complete
– Too slow to solve for large problem instances
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Loose end – Don’t cares
• What should be done about Xs in QM?
• Should they be included in the initial minterms?
• Should they be required in the Unate Covering problem?
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Another example
f (a,b,c) = ∑(1,2,6)+d(3)
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Summary
• Review
• Prime implicant selection in Quine-McCluskey
• Encoders and decoders
• Review: Transmission gates
• Multiplexers and demultiplexers
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Reading assignment
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Rest of Section 4.6
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Computer geek culture reference
• Complexity classes
• M. R. Garey and D. S. Johnson, Computers and Intractability: A
Guide to the Theory of NP-Completeness. W. H. Freeman &
Company, NY, 1979
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Today’s topics
• Encoders
• Decoders
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Encoders
• Assume you have n one-bit signals
• Only one signal can be 1 at a time
• How many states can you be in?
• How many signals are required to encode all those states?
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Encoder example
Pressed (i2, i1, i0) Code (o1,o0)
000 00
001 01
010 10
011 XX
100 11
101 XX
110 XX
111 XX
Implementation?
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Priority encoder
What if we want the highest-order high signal to dominate?
Pressed (i3, i2, i1) Code (o1,o0)
000 00
001 01
010 10
011 10
100 11
101 11
110 11
111 11
What impact on implementation efficiency?
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Decoders
Need to map back from encoded signal to state
Pressed (i1, i0) Code (o3,o2,o1,o0)
00 0001
01 0010
10 0100
11 1000
o0 isn’t always used. Why?
Most straightforward implementation?
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Straight-forward decoder implementation
i0 i0
o2
o1
o0
i1 i1
o3
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Straight-forward decoder implementation
n NOTs
i0 i0
o2
o1
o0
i1 i1
o3
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Straight-forward decoder implementation
n NOTs n inputs
i0 i0
o2
o1
o0
i1 i1
o3
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Straight-forward decoder implementation
n NOTs n inputs
2n ANDs
i0 i0
o2
o1
o0
i1 i1
o3
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Decoder implementation efficiency
• n NOTs
• n2 n-input ANDS
• O(
n2)
• Can’t do this for large number of inputs!
• Instead, decompose into multi-level implementation
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Multilevel decoder implementation
Starting point
o0 = i2 i1 i0
o1 = i2 i1 i0
o2 = i2 i1 i0
o3 = i2 i1i0
o4 = i2 i1 i0
o5 = i2 i1 i0
o6 = i2i1 i0
o7 = i2i1i0
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Multilevel decoder implementation
o0 = i2 ( i1 i0 )
o1 = i2 ( i1 i0)
o2 = i2 (i1 i0 )
o3 = i2 (i1i0)
o4 = i2( i1 i0 )
o5 = i2( i1 i0)
o6 = i2(i1 i0 )
o7 = i2(i1i0)
Reuse terms! Schematic?
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Multilevel decoder implementation
o0 = i2 ( i1 i0 )
o1 = i2 ( i1 i0)
o2 = i2 (i1 i0 )
o3 = i2 (i1i0)
o4 = i2( i1 i0 )
o5 = i2( i1 i0)
o6 = i2(i1 i0 )
o7 = i2(i1i0)
Reuse terms! Schematic?
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Summary
• Encoders
• Decoders
410
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Reading assignment
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Sections 1.2–1.7
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Homework assignment two
• Due 12 October
• Brief CMOS and TTL review
• Lab preparation questions
• Two-level logic
• Karnaugh maps
• Quine-McCluskey
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Computer geek culture reference
• C. Stoll, The Cukoo’s Egg. Bantam Doubleday Dell Publishing
Group, 1989
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Today’s topics
• Review: Transmission gates
• Multiplexers
• Demultiplexers
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Multiplexers or selectors
• Routes one of 2n inputs to one output
• n control lines
• Can implement with logic gates
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Logic gate MUX
Decoder
s1
s0
i0
i1
i2
i3
o
However, there is another way. . .
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MUX functional table
C Z
0 I0
1 I1
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MUX truth table
I1 I0 C Z
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
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Review: CMOS transmission gate (TG)
B
C
A
C
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Review: CMOS transmission gate (TG)
B
C
A
C
C = 1
C = 0
420
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Review: CMOS transmission gate (TG)
B
C
A
C
C = 1
C = 0
421
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Review: CMOS transmission gate (TG)
B
C
A
C
C = 1
C = 0
B = A
422
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Review: CMOS transmission gate (TG)
B
C
A
C
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Review: CMOS transmission gate (TG)
B
C
A
C
C = 0
C = 1
424
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Review: CMOS transmission gate (TG)
B
C
A
C
C = 0
C = 1blocked
blocked
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Review: CMOS transmission gate (TG)
B
C
A
C
C = 0
C = 1blocked
blockedB =High-Z
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Review: Other TG diagram
B
C
A
C
A B
C
C
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MUX
C
C
C
C
A
B
D
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MUX
C
C
C
C
A
B
DC = 1
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MUX
C
C
C
C
A
B
DC = 1
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MUX
C
C
C
C
A
B
D
D = A
C = 1
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MUX
C
C
C
C
A
B
D
432
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MUX
C
C
C
C
A
B
D
C = 0
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MUX
C
C
C
C
A
B
D
C = 0
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MUX
C
C
C
C
A
B
D
D = BC = 0
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MUX
C
C
C
C
A
B
D D
B
A
C C
2:1 MUX
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MUX using TGs
I3
I0
I2
I1
AA BB
ZZ
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Hierarchical MUX implementation
4 :1mux
4 :1mux
8 :1mux
2 :1mux
0123
0123
S
S 1 S 0
S 1 S 0
Z
ACB
I 0
I 1
I 2
I 3
I 4
I 5
I 6I 7
0
1
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Alternative hierarchical MUX implementation
00
11 SS
00
11 SS
00
11 SS
00
11 SS
00
11
S 1
22
33 S 0
AA BB
II 00
II 11
II 22
II 33
II 44
II 55
II 66
II 77
CC
CC
CC
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MUX examples
2:1m ux
I0
I1
A
Z
Z = A I0 +AI1
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MUX examples
I 0
A
I 1I 2I 3
B
Z4:1
m ux
Z = A B I0 + A BI1 +ABI2 +ABI3
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MUX examples
I 0
A
I 1I 2I 3
B
Z8:1m ux
C
I 4I 5I 6
I 7
Z = A B C I0 + A BCI1 + ABC I2 + ABCI3+
AB C I4 +ABCI5 +ABC I6 +ABCI7
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MUX properties
• A 2n : 1 MUX can implement any function of n variables
• A 2n−1 : 1 can also be used
– Use remaining variable as an input to the MUX
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MUX example
F(A,B,C) = ∑(0,2,6,7)
= A B C + A BC +ABC +ABC
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Truth table
A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
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Lookup table implementation
8:1MUX
101000111
012345677 S2 S1 S0
AA BB CC
FF
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MUX example
F(A,B,C) = ∑(0,2,6,7)
= A B C + A BC +ABC +ABC
Therefore,
A B → F = C
A B→ F = C
AB → F = 0
AB→ F = 1
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Truth table
A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
F= C
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Truth table
A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
F= C
449
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Lookup table implementation
S1 S0
AA BB
4:1MUX
01233
0011
FFC
C
450
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Demultiplexer (DMUX) definitions
• Closely related to decoders
• n control signals
• Single data input can be routed to one of 2n outputs
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Recall decoders
n NOTs
i0 i0
o2
o1
o0
i1 i1
o3
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DMUXs similar to decoders
i1 i1
o0
o1
o2
o3
oei0 i0
Use extra input to control output signal
453
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Demultiplexer
C
C
C
CA
D
E
However, this implementation is dangerous
454
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Demultiplexer
C
C
C
CA
D
E
C = 1
However, this implementation is dangerous
455
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Demultiplexer
C
C
C
CA
D
E
C = 1
However, this implementation is dangerous
456
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Demultiplexer
C
C
C
CA
D
E
D = A
C = 1
E=High-Z
However, this implementation is dangerous
457
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Demultiplexer
C
C
C
CA
D
E
However, this implementation is dangerous
458
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Demultiplexer
C
C
C
CA
D
E
C = 0
However, this implementation is dangerous
459
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Demultiplexer
C
C
C
CA
D
E
C = 0
However, this implementation is dangerous
460
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Demultiplexer
C
C
C
CA
D
E
E = A
C = 0
D=High-Z
However, this implementation is dangerous
461
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Demultiplexer
C
C
C
CA
D
ECC
A
E
D
However, this implementation is dangerous
462
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Dangers when implementing with TGs
C
C
C
CA
D
E
463
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Dangers when implementing with TGs
C
C
C
CA
D
E
What if an output is not connected to any input?
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Review: Consider undriven inverter inputs
VDD
VSS
A B
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Review: Consider undriven inverter inputs
VDD
VSS
A=0B=1
A B
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Review: Consider undriven inverter inputs
VDD
VSS
A B
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Review: Consider undriven inverter inputs
VDD
VSS
A=1
B=0A B
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Review: Consider undriven inverter inputs
VDD
VSS
A B
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Review: Consider undriven inverter inputs
VDD
VSS
A B
A=?
B=?
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Set all outputs
A
D
E
0
0
C
C
C
C
C
C
C
C
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Demultiplexers as building blocks
3 :8dec
0
1
2
3
4
5
6
7
A B C
Enb
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABCS2 S1 S 0
Generate minterm based on control signals
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Example function
F1 = A BCD+ A BC D+ABCD
F2 = ABC D +ABC= ABC D +ABCD +ABCD
F3 = A + B + C + D = ABCD
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Demultiplexers as building blocks
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
F 1
F 3
0
1
2
3
4
5
6
7
8
9
10
1 1
12
13
14
15
A
S3 S 2 S1 S0
4:16dec
Enb
B C D
F 2
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Status
• CMOS
• Switch-based and gate-based design
• Two-level minimization
• Encoders
• Decoder
• Multiplexers
• Demultiplexers
Is anything still unclear? Then let’s do some examples!
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Lab three
• Requires error detection
• Read Section 1.4 in the book
• How to build an error injector, i.e., a conditional inverter?
• How to build a two-input parity gate?
• How to build a three-input parity gate from two-input parity gates?
• How to detect even number of ones?
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Summary
• CMOS review
• Review: Transmission gates
• Multiplexers
• Demultiplexers
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Reading assignment
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Finish Sections 1.2–1.7
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Today’s topics
• Practice midterm
• Questions on MUXs and DMUXs?
• Questions about lab three?
• Number systems
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Arithmetic circuits
• Administration
• Number systems
• Adders
– Ripple carry
– Carry lookahead
– Carry select
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Introduction to number systems
Consider a base-10 number: 1,293
1,293 = 1 ·103 +2 ·102 +9 ·101 +3 ·100
For base-10, given an n-digit number in which di is the ith digit, the
number is
n
∑i=0
10i−1 ·di
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Introduction to number systems
This works for any base. Convert 2,0123 from base-3 to base-10.
2 ·33 +0 ·32 +1 ·31 +2 ·30
2 ·27+0 ·9+1 ·3+2 ·1
54+0+3+2
5910
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Introduction to number systems
Convert 5910 from base-10 to base-3. Repeatedly divide by the
greatest power of b (the base) that is less than the number.
Remainder Try dividing Digit Comment
59 34 = 81 0 Too big
59−0 ·81 = 59 33 = 27 2 O.K.
59−2 ·27 = 5 32 = 9 0 Too big
5−0 ·9 = 5 31 = 3 1 O.K.
5−1 ·3 = 2 30 2 O.K.
020123 = 20123
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Conversion works for any base
Review: For base-10, given an n-digit number in which di is the ith
digit, the number isn
∑i=1
10i−1 ·di
For base-b, given an n-digit number in which di is the ith digit, the
number isn
∑i=1
·bi−1 ·di
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Useful bases
• 2: Also called binary. Most fundamental base in digital logic.
Know this like the back of your hand.
• 8: Also called octal. Sometimes used by programmers. Prefer
base 16.
• 10: Also called decimal or Arabic.
• 16: Also called hexadecimal or simple hex. One of the most
compact and beautiful representations for digital computer
programmers.
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Binary
1 2 4 8 16 32 64 128 256 512 1,024 (1K)
20 21 22 23 24 25 26 27 28 29 210
k 6= K
1 k = 103 = 1,000
1 K = 210 = 1,024
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Decimal
• Most commonly used by human beings.
• Also called Arabic.
– Actually developed in India and brought to Europe via Arabian
empire.
• Largely replaced Roman numerals, which were more
cumbersome when writing the large and complicated numbers
used in astronomy and wide-spread trade.
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Number systems
• Representation of positive numbers same in most systems
• A few special-purpose alternatives exist, e.g., Gray code
• Alternatives exist for signed numbers
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Base-16: Hex
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7 8 9 A B C D E F
Often prefixed with 0x.
What is 0xFF?
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Reading assignment
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Sections 5.1–5.6
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Computer geek culture reference
• Spelling things in ASCII (hex or binary)
• This is one of the lower forms of geek culture, akin to bad puns
• However, at least one university has things written into its
buildings with subtle brick patterns in ASCII binary
4a6934207375616e34206a6931207368653420
6a69342068656e332068616f332077616e3221
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Today’s topics
• Number systems
• Adders and subtracters
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Other number/encoding systems
• Binary-coded decimal
– Wastes fractional bit for alignment
• ASCII: 7-bit characters
– Parity
– Best to see a chart
– 0x61 = 97 = ‘a’
– 0x47 = 71 = ‘G’
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Other number/encoding systems
Unicode: 16-bit
• Similar to ASCII
• International
• Allows about 216 = 65,536 characters
• Enough for symbolic writing systems
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Standard unsigned binary numbers
0000
0001
0010
0011
0100
0101
0110
01111000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
78
9
10 (a)
11 (b)
12 (c)
13 (d)
14 (e)
15 (f)
Given an n-bit number in which di is the ith digit, the number is
∑ni=1 2i−1di
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Unsigned addition
Consider adding 9 (1001) and 3 (0011)
1 1
1 0 0 1
+ 0 0 1 1
1 1 0 0
Why an extra column?
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Unsigned addition
Consider adding 9 (1001) and 3 (0011)
1 1
1 0 0 1
+ 0 0 1 1
1 1 0 0
Why an extra column?
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Unsigned addition
Consider adding 9 (1001) and 3 (0011)
1 1
1 0 0 1
+ 0 0 1 1
1 1 0 0
Why an extra column?
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Unsigned addition
Consider adding 9 (1001) and 3 (0011)
1 1
1 0 0 1
+ 0 0 1 1
1 1 0 0
Why an extra column?
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Unsigned addition
Consider adding 9 (1001) and 3 (0011)
1 1
1 0 0 1
+ 0 0 1 1
1 1 0 0
Why an extra column?
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Unsigned addition
Consider adding 9 (1001) and 3 (0011)
1 1
1 0 0 1
+ 0 0 1 1
1 1 0 0
Why an extra column?
501
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Overflow
• If the result of an operation can’t be represented in the available
number of bits, an overflow occurs
• E.g., 0110+1011 = 10001
• Need to detect overflow
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Overflow
• If the result of an operation can’t be represented in the available
number of bits, an overflow occurs
• E.g., 0110+1011 = 10001
• Need to detect overflow
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Gray code
0000
0001
0010
0011
0100
0101
0110
01111000
1001
1010
1011
1100
1101
1110
1111
0
1
3
2
7
6
4
515 (f)
14 (e)
12 (c)
13 (d)
8
9
11 (b)
10 (a)
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Useful for shaft encoding
Sequence?
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Gray code
• To convert from a standard binary number to a Gray code
number XOR the number by it’s half (right-shift it)
• To convert from a Gray code number to a standard binary
number, XOR each binary digit with the parity of the higher digits
Given that a number contains n digits and each digit, di , contributes
2i−1 to the number
Pkj = d j ⊕d j+1 · · ·⊕dk−1 ⊕dk
di = di ⊕Pni+1
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Gray code
• Converting from Gray code to standard binary is difficult
– Take time approximately proportional to n
• Doing standard arithmetic operations using Gray coded numbers
is difficult
• Generally slower than using standard binary representation
• E.g., addition requires two carries
• Why use Gray coded numbers?
– Analog to digital conversion
– Reduced bus switching activity
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Signed number systems
• Three major schemes
– Sign and magnitude
– One’s complement
– Two’s complement
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Number system assumptions
• Four-bit machine word
• 16 values can be represented
• Approximately half are positive
• Approximately half are negative
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Sign and magnitude
0000
0001
0010
0011
0100
0101
0110
01111000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
−1
−2
−4
−5
−7
−0
−3
−6
510
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Sign and magnitude
• dn represents sign
– 0 is positive, 1 is negative
• Two representations for zero
• What is the range for such numbers?
– Range: [−2n−1 +1,2n−1 −1]
511
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Sign and magnitude
• dn represents sign
– 0 is positive, 1 is negative
• Two representations for zero
• What is the range for such numbers?
– Range: [−2n−1 +1,2n−1 −1]
512
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Sign and magnitude
• How is addition done?
• If both numbers have the same sign, add them like unsigned
numbers and preserve sign
• If numbers have differing signs, subtract smaller magnitude from
larger magnitude and use sign of large magnitude number
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Sign and magnitude
• Consider 5+−6
• Note that signs differ
• Use magnitude comparison to determine large magnitude: 6−5
• Subtract smaller magnitude from larger magnitude: 1
• Use sign of large magnitude number: −1
514
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Direct subtraction
Consider subtracting 5 (0101) from 6 (0110)
b
0 1 1 0
− 0 1 0 1
0 0 0 1
• Note that this operation is different from addition
• Sign and magnitude addition is complicated
515
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Direct subtraction
Consider subtracting 5 (0101) from 6 (0110)
b
0 1 1 0
− 0 1 0 1
0 0 0 1
• Note that this operation is different from addition
• Sign and magnitude addition is complicated
516
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Direct subtraction
Consider subtracting 5 (0101) from 6 (0110)
b
0 1 1 0
− 0 1 0 1
0 0 0 1
• Note that this operation is different from addition
• Sign and magnitude addition is complicated
517
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Direct subtraction
Consider subtracting 5 (0101) from 6 (0110)
b
0 1 1 0
− 0 1 0 1
0 0 0 1
• Note that this operation is different from addition
• Sign and magnitude addition is complicated
518
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Direct subtraction
Consider subtracting 5 (0101) from 6 (0110)
b
0 1 1 0
− 0 1 0 1
0 0 0 1
• Note that this operation is different from addition
• Sign and magnitude addition is complicated
519
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One’s compliment
0000
0001
0010
0011
0100
0101
0110
01111000
1001
1010
1011
1100
1101
1110
1111 1
2
3
4
5
6
7
−6
−5
−3
−2
−7
−4
−10 0
520
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One’s compliment
• If negative, complement all bits
• Addition somewhat simplified
• Do standard addition except wrap around carry back to the 0th bit
• Potentially requires two additions of the whole width
– Slow
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One’s complement addition
Consider adding -5 (1010) and 7 (0111)
1 1
1 0 1 0
+ 0 1 1 1
522
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One’s complement addition
Consider adding -5 (1010) and 7 (0111)
1 1
1 0 1 0
+ 0 1 1 1
1
523
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One’s complement addition
Consider adding -5 (1010) and 7 (0111)
1 1
1 0 1 0
+ 0 1 1 1
0 1
524
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One’s complement addition
Consider adding -5 (1010) and 7 (0111)
1 1
1 0 1 0
+ 0 1 1 1
0 0 1
525
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One’s complement addition
Consider adding -5 (1010) and 7 (0111)
1 1 1
1 0 1 0
+ 0 1 1 1
0 0 0 1
526
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One’s complement addition
Consider adding -5 (1010) and 7 (0111)
1 1 1 1
1 0 1 0
+ 0 1 1 1
0 0 0 0
527
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One’s complement addition
Consider adding -5 (1010) and 7 (0111)
1 1 1 1
1 0 1 0
+ 0 1 1 1
0 0 1 0
528
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Two’s complement
• To negate a number, invert all its bits and add 1
• Like one’s complement, however, rotated by one bit
• Counter-intuitive
– However, has some excellent properties
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Two’s complement
0000
0001
0010
0011
0100
0101
0110
01111000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
−6
−4
−3
−1
−8
−5
7
−7
−2
530
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Two’s complement
• Only one zero
– Leads to more natural comparisons
• One more negative than positive number
– This difference is irrelevant as n increases
• Substantial advantage – Addition is easy!
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Two’s complement addition
Consider adding -4 (1100) and 6 (0110)
1
1 1 0 0
+ 0 1 1 0
0 0 1 0
532
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Two’s complement addition
Consider adding -4 (1100) and 6 (0110)
1
1 1 0 0
+ 0 1 1 0
0 0 1 0
533
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Two’s complement addition
Consider adding -4 (1100) and 6 (0110)
1
1 1 0 0
+ 0 1 1 0
0 0 1 0
534
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Two’s complement addition
Consider adding -4 (1100) and 6 (0110)
1
1 1 0 0
+ 0 1 1 0
0 0 1 0
535
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Two’s complement addition
Consider adding -4 (1100) and 6 (0110)
1 1
1 1 0 0
+ 0 1 1 0
0 0 1 0
536
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Two’s complement
• No looped carry – Only one addition necessary
• If carry-in to most-significant bit 6= carry-out to most-significant
bit, overflow occurs
• What does this represent?
• Both operands positive and have carry-in to sign bit
• Both operands negative and don’t have carry-in to sign bit
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Two’s complement overflow
a b cin cout
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
538
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Two’s complement overflow
a b cin cout
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
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Half adder
For two’s complement, don’t need subtracter
A B cout sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
cout= AB
sum= A⊕B
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Half adder
cout
sumB
A
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Full adder
Need to deal with carry-inA B cin cout sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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Full adder
sum= A⊕B⊕cin
cout= AB+A ci+B ci
543
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Cascaded full-adders
sum
A B A Bcout cincincout
sum
A Bcincout
sum
A1A2A3 B1B2B3
sum1sum2sum3
0
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Full adder standard implementation
AA
AAAA
BB
BBBB
CI
CISS
CO
Six logic gates
545
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Full adder composed of half-adders
Ha lfAdder
AA
BB
HalfAdder
A + B
CI
A + B + CISS SS
COCOCI (A + B)A B
SS
CO++
AB+ci(A⊕B) = AB+B ci+A ci
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Adder/subtracter
A B
sum sum sumsum
A B A B A B
0 1
Add/Subtract
A3 B3 B3
0 1
A 2 B2 B2
0 1
A1
B1
B1
0 1
A0 B0 B0
Sel Sel Sel Sel
S3 S2 S1
S0
Overflow
cin cin cin cincout coutcoutcout
Consider input to cin
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Ripple-carry delay analysis
• The critical path (to cout) is two gate delays per stage
• Consider adding two 32-bit numbers
• 64 gate delays
– Too slow!
• Consider faster alternatives
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Carry lookahead adder
• Lecture notes give detail for completeness
• However, primarily important to understand that carry lookahead
compresses many levels of a carry chain into fewer levels for
speed
• Will need to understand carry select adders in detail
• Carry generate: G = AB
• Carry propagate: P = A⊕B
• Represent sumand cout in terms of G and P
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Overview: Carry lookahead adder
sum= A⊕B⊕cin
= P⊕cin
cout= AB+A cin+B cin
= AB+cin(A+B)
= AB+cin(A⊕B)
= G+cin P
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Overview: Carry lookahead adder
Flatten carry equations
cin1 = G0 +P0 cout0
cin2 = G1 +P1 cout1 = G1 +P1G0 +P1P0 cout0
cin3 = G2 +P2 cout2 = G2 +P2G1 +P2P1G0 +P2P1P0 cout0
cin4 = G3 +P3C3 = G3 +P3G2 +P3P2G1+
P3P2P1G0 +P3P2P1P0 cout0
Each cin can be implemented in three-level logic
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Carry lookahead building block
Pi 1 gate delay
Ci Si 2 gate delays
BiAi
G i 1 gate delay
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Carry lookahead adder
C0C0
C0
C0P0P0
P0
P0
G0G0
G0
G0
C1
P1
P1
P1
P1
P1
P1G1
G1
G1
C2P2
P2
P2
P2
P2
P2
G2
G2
C3
P3
P3
P3
P3
G3
C4
553
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Carry lookahead delay analysis
• Assume a 4-stage adder with CLA
• Propagate and generate signals available after 1 gate delays
• Carry signals for slices 1 to 4 available after 3 gate delays
• Sum signal for slices 1 to 4 after 4 gate delays
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Carry lookahead
• No carry chain slowing down computation of most-significant bit
– Computation in parallel
• More area required
• Each bit has more complicated logic than the last
• Therefore, limited bit width for this type of adder
• Can chain multiple carry lookahead adders to do wide additions
• Note that even this chain can be accelerated with lookahead
– Use internal and external carry lookahead units
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Cascaded carry lookahead adder
4−bit Adder
4 4
4
A [15−12] B[15−12] C12C16
S[15−12]
P G4−bit Adder
4 4
4
A [11−8] B[11−8] C8
S[11−8]
P G4−bit Adder
4 4
4
A [7−4] B[7−4] C4
S[7−4]
P G4−bit Adder
4 4
4
A [3−0] B[3−0] C0
S[3−0]
P G
Lookahead Carry UnitC0
P0 G0P1 G1P2 G2P3 G3 C3 C2 C1
C0
P3−0 G3−0
C4
@3@2
@0
@4
@4@3@2@5
@7
@3@2@5
@8@8
@3@2
@5
@5@3
@0
C16
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Delay analysis for cascaded carry lookahead
• Four-stage 16-bit adder
• cin for MSB available after five gate delays
• sumfor MSB available after eight gate delays
• 16-bit ripple-carry adder takes 32 gate delays
• Note that not all gate delays are equivalent
• Depends on wiring, driven load
• However, carry lookahead is usually much faster than ripple-carry
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Carry select adders
• Trade even more hardware for faster carry propagation
• Break a ripple carry adder into two chunks, low and high
• Implement two high versions
– high0 computes the result if the carry-out from low is 0
– high1 computes the result if the carry-out from low is 1
• Use a MUX to select a result once the carry-out of low is known
– high0’s cout is never greater than high1’s cout so special-case
MUX can be used
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Carry select adder
4−Bit Adder[3:0]
C0C4
4−Bit Adder[7:4]
0C8
1C8
2:1 Mspecial−case
UX
010101
4−Bit Adder[7:4]
C8 S7 S6 S5 S4 S3 S2 S1 S0
01
C4
AdderH
MUX MUX MUX MUX
igh
AdderLow
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Delay analysis of carry select adder
• Consider 8-bit adder divided into 4-bit stages
• Each 4-bit stage uses carry lookahead
• The 2:1 MUX adds two gate delays
• 8-bit sum computed after 6 gate delays
• 7 gate delays for carry lookahead
• 16 gate delays for ripple carry
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Summary
• Number systems
• Adders and subtracters
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Homework three
• Review of a few concepts (should be quick for most of you)
• QM problems
• Encoders, decoders, MUXs, and DMUXs
• Number systems
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Reading assignment
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Finish Sections 5.1–5.6
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Today’s topics
• Memory
• Latches
• Flip-flops
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Memory
• Combinational logic outputs a function of inputs, only
• Sequential logic outputs a function of inputs and state
• State is remembered
• Consider a sequential vending machine
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Flip-flop introduction
• Stores, and outputs, a value
• Puts a special clock signal in charge of timing
• Allows output to change in response to clock transition
– Timing and sequential circuits
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Feedback and memory
AA
• Feedback is the root of memory
• Can compose a simple loop from NOT gates
• However, there is no way to switch the value
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Feedback and memory
AA
• Feedback is the root of memory
• Can compose a simple loop from NOT gates
• However, there is no way to switch the value
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TG and NOT-based memory
AA
C
• Can break feedback path to load new value
• However, potential for timing problems
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Ring oscillators
A
B C D E
1 0 0 0 1
X
Like pulse shaping circuits with memory
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Ring oscillators
A (=X) B C D EE
Period of Repeating Waveform (tp ))Gate Delay (td ))
00
11
00
11
00
11
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Reset/set latch
R
R
S
S
Q
Q
Q
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Reset/set timing
100
Reset Hold Set Reset Set Race
R
S
Q
Q
Unstable state Unstable state
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RS latch state diagram
01
0010
0001
1111
10
10 01
11
1001
00
output=Q Qinput=R S
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Clocking terms
Input
Clock
T su T h
• Clock – Rising edge, falling edge, high level, low level, period
• Setup time: Minimum time before clocking event by which input
must be stable (TSU)
• Hold time: Minimum time after clocking event for which input
must remain stable (TH)
• Window: From setup time to hold time
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Gated RS latch
S
R
ENB
Q
Q
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Gated RS latch
S
R
ENB
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Memory element properties
Type Inputs sampled Outputs valid
Unclocked latch Always LFT
Level-sensitive latch Clock high LFT
(TSU to TH ) around falling clock edge
Edge-triggered flip-flop Clock low-to-high transition Delay from rising edge
(TSU to TH ) around rising clock edge
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Clocking conventions
Active-high transparent Active-low transparent
Positive (rising) edge Negative (falling) edge
DD
D D
Q Q
CLK CLK
CLK CLK
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Timing for edge and level-sensitive latches
D
Clk
Q edge
Q level
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Summary
• Memory
• Latches
• Flip-flops (more on these later)
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Reading assignment
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Sections 6.1–6.3
• Sections 6.4 and 6.5
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Computer geek culture reference
Computer security
• PGP
• (Open)SSH
• (Type II) remailers
• Ethereal
• Crack
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Today’s topics
• Administrative
• Review: Build a multiplier
• Finite state machines
• Back to latches
• Debouncing
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Multiplication
• Already went through this on the blackboard
• Wanted the class to do it together, also want you to have clear
lecture notes on it
• To understand why these trade-offs exist, we need to understand
the fundamentals of arithmetic circuits
• We have already discussed the selection of number systems and
the design of adders/subtracters
• Similar alternatives exist for multipliers
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Multiplication
• Multiplication is the repeated application addition of ANDed bits
and shifting (multiplying by two)
• Multiplication is the sum of the products of each bit of one
operand with the other operand
• Consequence: A product has double the width of its operands
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Multiplication
Recall that multiplying a number by two shifts it to the left one bit
6 ·3 = 6 · (22 ·0+21 ·1+20 ·1)
= 6 ·22 ·0+6 ·21 ·1+6 ·20 ·1
110 ·011 = 11000 ·0+1100 ·1+110 ·1
= 110+1100
= 10010
= 18
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Multiplication
A2 A1 A0
× B2 B1 B0
A2B0 A1B0 A0B0
A2B1 A1B1 A0B1
+ A2B2 A1B2 A0B2
sum5 sum4 sum3 sum2 sum1 sum0
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Multiplication
Consider multiplying 6 (110) by 3 (011)
1 1 0
× 0 1 1
1 1 0
1 1 0
+ 0 0 0
0 1 0 0 1 0
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Multiplier implementation
• Direct implementation of this scheme possible
• Partial products formed with ANDs
• For four bits, 12 adders and 16 gates to form the partial products
– 88 gates
• Note that the maximum height (number of added bits) is equal to
the operand width
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Combinational multiplier
A 0 B 0 A 1 B 0 A 0 B 1 A 0 B 2 A 1 B 1 A 2 B 0 A 0 B 3 A 1 B 2 A 2 B 1 A 3 B 0 A 1 B 3 A 2 B 2 A 3 B 1 A 2 B 3 A 3 B 2 A 3 B 3
HA
S 0 S 1
HA
F A
F A
S 3
F A
F A
S 4
HA
F A
S 2
F A
F A
S 5
F A
S 6
HA
S 7
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Multiplier building block
F A
X
Y
A B
S CI CO
Cin Sum In
Sum Out Cout
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Combinational multiplier
C
C
C
P0
P1
P2P3P4P5
S
S
SSS
A2 B0 A1 B0 A0 B0
A0 B1A1 B1A2 B1
A1 B2 A0 B2A2 B2
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Sequential multiplier
• Can iteratively one row of adders to carry out multiplications
• Advantage: Area reduced to approximately its square root
• Disadvantage: Takes n clock cycles, where n is the operand bit
width
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2X2 sequential multiplier
co co coco ci ci cicisum sum sumsum
b b bb a a aa
Q QD D
QQQQ
Q Q Q
DDDD
D D D
clkclk
clk
clkclk
clk
clkclkclk
0
0
0
0
Operands already in registersAdder flip-flops cleared
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2X2 sequential multiplier
co co coco ci ci cicisum sum sumsum
b b bb a a aa
Q QD DOperands
QQQQ
Q Q Q
DDDD
D D D
clkclk
clk
clkclk
clk
clkclkclk
0
0
0
0
Operands already in registersAdder flip-flops cleared
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2X2 sequential multiplier
co co coco ci ci cicisum sum sumsum
b b bb a a aa
Q QD DOperands
Could be HA
Could be HA
QQQQ
Q Q Q
DDDD
D D D
clkclk
clk
clkclk
clk
clkclkclk
0
0
0
0
Operands already in registersAdder flip-flops cleared
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Arithmetic/logic units
• Possible to implement functional units that can carry out many
arithmetic and logic operations with little additional area or delay
overhead
• Already saw example: Combined adder/subtracter
• Other operations possible
• Could you generalize the approach used for two’s complement
addition and subtraction to another pair of operations?
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Arithmetic/logic operations
• Increment
• Addition
• Negation
• Subtraction
• Multiplication
– Slow or large
• Division
– Slow or large
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Arithmetic/logic operations
• Shift left
– Fast, multiplication by two
• Shift right
– Fast, division by two
• Bit-wise operations
– AND, OR, NOT, NAND, NOR, XOR, and XNOR
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Word description to state diagram
• Design a vending machine controller that will release (output
signal r) an apple as soon as 30¢ have been inserted
• The machine’s sensors will clock your controller when an event
occurs. The machine accepts only dimes (input signal d) and
quarters (input signal q) and does not give change
• When an apple is removed from the open machine, it indicates
this by clocking the controller with an input of d
• The sensors use only a single bit to communicate with the
controller
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Word description to state diagram
• We can enumerate the inputs on which an apple should be
released
ddd+ddq+dq+qd+qq
d(dd+dq+q)+q(d+q)
d(d(d+q)+q)+q(d+q)
For d, i = 0, for q, i = 1
0(0(0+1)+1)+1(0+1)
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Word description to state diagram
10
0
1
0
1
0
0
1
0(0(0 + 1) + 1) + 1(0 + 1)
1
A/0
B/0
C/0
D/1
E/0
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Word description to state diagram
0
0
1
X
0(0(0 + 1) + 1) + 1(0 + 1)
X
1
X
A/0
B/0
C/0
D/1
E/0
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State diagram to state table
nextcurrent state output (r)state i=0 i=1
A B E 0
B C D 0
C D D 0
D A A 1
E D D 0
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Moore block diagram
combinational logic
sequential elements
combinational logic
feedback
inputs
outputs
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Mealy block diagram
combinational logic
sequential elements
outputs
inputs
feedback
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Moore FSMs
0
0
1
1
1
00 1
D/1
A/0 B/0
C/0
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Mealy FSMs
1/X
1/0
0/00/0
0/1
1/0
1/10/1
CD
BA
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Mealy tabular form
s+/q
s 0 1
A D/0 B/X
B C/1 B/0
C A/0 B/1
D C/1 C/0
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FSM design summary
• Specify requirements in natural form
• Manually derive state diagram
– Automatic way to go from English to FSM, however more
theory required
– Can minimize state count, however, more theory also required
– See me if you want more information on this, or take a
compilers course and a graduate-level switching theory
course, or take my ECE 303
• Assign values to states to minimize logic complexity
• Optimize implementation of state and output functions
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Back to latches
• Latches: Level sensitive
• Flip-flops: Edge-triggered
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Review: Clocking conventions
Active-high transparent Active-low transparent
Positive (rising) edge Negative (falling) edge
DD
D D
Q Q
CLK CLK
CLK CLK
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Latch and flip-flop equations
RS
Q+ = S+ R Q
D
Q+ = D
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Latch and flip-flop equations
JK
Q+ = J Q + K Q
T
Q+ = T ⊕Q
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JK latch
R−S latch
replacements
K
J S
RQ
Q
Use output feedback to ensure that RS6= 11
Q+ = Q K + Q J
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JK latch
J K Q Q+
0 0 0 0
0 0 1 1 hold
0 1 0 0
0 1 1 0 reset
1 0 0 1
1 0 1 1 set
1 1 0 1
1 1 1 0 toggle
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JK race
100 Set Reset Toggle
Race Cond i t ion
J
K
Q
Q
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Falling edge-triggered D flip-flop
• Use two stages of latches
• When clock is high
– First stage samples input w.o. changing second stage
– Second stage holds value
• When clock goes low
– First stage holds value and sets or resets second stage
– Second stage transmits first stage
• Q+ = D
• One of the most commonly used flip-flops
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Falling edge-triggered D flip-flop
DD
lk=
RR
SS
00
00
DD
DDDD
=1
DD
C
Clock high
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Falling edge-triggered D flip-flop
Holds D whenclock goes low
Holds D whenclock goes low
Q
Q
DD
Clk=1
RR
SS
00
00
DD
DDDD
=
DD
Clock switching
Inputs sampled on falling edge, outputs change after falling edge
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Falling edge-triggered D flip-flop
?
Clk=
RR
SS
D
0
DDDD
=
RR
SS
DD
0
D
Clock low
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Another view of an edge-triggered DFF
Q
D
clkR
R
R
Q
Q
Q
Q
Q
Q
S
S
S
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Edge triggered timing
Positive edge− t riggered FF
Negative edge− t riggered FF
100
D
CLK
Qpos
Qpos
Qneg
Qneg
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RS clocked latch
• Storage element in narrow width clocked systems
• Dangerous
• Fundamental building block of many flip-flop types
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JK flip-flop
• Versatile building block
• Building block for D and T flip-flops
• Has two inputs resulting in increased wiring complexity
• Edge-triggered varieties exist
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D flip-flop
• Minimizes input wiring
• Simple to use
• Common choice for basic memory elements in sequential circuits
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Debouncing
• Mechanical switches bounce!
• What happens if multiple pulses?
– Mutliple state transitions
• Need to clean up signal
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Schmitt triggers
A B
A
Low
High
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Schmitt triggers
A B
AVTL
VTH
Low
High
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Schmitt triggers
A B
AVTL
VTH
Low
High
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Schmitt triggers
transition
A B
AVTL
VTH
Low
High
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Schmitt triggers
transitionB
A B
AVTL
VTH
Low
High
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Debouncing
0
1
2
3
4
5
-1.0e-03 -5.0e-04 0.0e+00 5.0e-04 1.0e-03 1.5e-03
V
T (s)
Schmidt trig.RC
0.751.65
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Assigned reading
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Review Sections 6.4 and 6.5
– If FSMs don’t make sense now, please ask questions, or see
me
– FSMs are tricky at first – Almost everybody has this moment
of epiphany at which they suddenly make sense
• Section 6.6
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Computer geek culture references
• Parsers and lexical analyzers
• Writing problem-specific languages
• A. Aho, R. Sethi, and J. Ullman, Compilers principles, techniques,
and tools. Addison-Wesley, Reading, MA, 1986
• Lex and yacc
• Flex and bison
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Today’s topics
• Introduction to instruction processors
• RSE processor
• Architecture
• Assembly
• Compilation
• PIC16C74A
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Change in style
• Micro-controller based design
• In this lecture, I want a lot of help and participation
• You now have the fundamental knowledge to design a processor
• Let’s build a simple one on paper
• You’ll be programming a slightly more complex processor in next
week’s lab assignment
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RSE processor
• Already understand building FSMs
• Can use array of latches to store multiple bits: register
• Consider simple processor, called RSE (Rob’s simplified
example)
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RSE registers
• All registers are 8-bit
• Four general-purpose registers, A,B,C, and D
– Used to do computation
• Program counter PC
• Stack pointer SP(sometimes called TOSfor top of stack), which
may also be used as a general-purpose register
• ALU capable of adding (0) and subtracting (1)
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RSE arithmetic instructions
• add RD, RS1, RS2
• sub RD, RS1, RS2
Do computation on source registers and put result in destination
register
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RSE data motion
• ldm RD, [RS]
– Load from memory location indicated by the source register
into destination register
• stm [RD], RS
– Store to memory location indicated by the destination register
from source register
• ldi RD, I
– Load immediate into destination register
• ldpc RS
– Load from program counter to destination register
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Branch instructions
• blz RT , RC
– Set PC to RT if RC < 0
• bz RT , RC
– Set PC to RT if RC = 0
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Architecture
Inc
Instructionfetch
A MUX
MUX
NPC
<0 0MUX
Instruction decode ®ister fetch
Writeback
SP
PC
Memory
... ALU
DMUX
Execute
I Decoder
MUX
What about memory writes? Immediates?
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Instruction encoding
• How many instructions?
• Worst-case operands?
– 3 registers (each how many bits?)
– 1 register and 1 immediate
– To pack or not to pack?
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Initialization
• Chip has reset line
• Set PC to byte 2
• Start running. . .
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Memory
• Acts like a collection of byte-wide registers
• Address using a decoder
• Can put other devices at some memory locations
– Memory-mapped input-output
• Can also use special-purpose output instructions or registers
• Let’s build some from D flip-flops
• Multiplexing address and data lines?
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Program counter
Every clock tick the processor
• Fetches an instruction from the memory location pointed to by PC
• Decodes the instruction
• Fetches the operands
• Executes the instruction
• Stores the results
• Increments the program counter
• Can jump to another code location by moving a value into the PC
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Example high-level code
Sum up the contents of memory locations 2-6
1. A = 0
2. For B from 2 to 6
3. A = A+[B]
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Example low-level code
Sum up the contents of memory locations 2–6
2. A = 0 ldi A, 0 or sub A, A, A
4. B = 2 ldi B, 2
6. C = [B] (loop start point) ldm C, [B]
8. A = A+C add A, A, C
10. B = B+1 ldi C, 1 — add B, B, C
14. C = 6 (loop start) ldi C, 6
16. If B≤ 6 (B < 7) branch to C ldi D, 7 — sub D, B, D — blz C, D
(Done)
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Example low-level code
Sum up the contents of memory locations 2–6
2. A = 0 ldi A, 0 or sub A, A, A
4. B = 2 ldi B, 2
6. C = [B] (loop start point) ldm C, [B]
8. A = A+C add A, A, C
10. B = B+1 ldi C, 1 — add B, B, C
14. C = 6 (loop start) ldi C, 6
16. If B≤ 6 (B < 7) branch to C ldi D, 7 — sub D, B, D — blz C, D
(Done)
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Example low-level code
Sum up the contents of memory locations 2–6
2. A = 0 ldi A, 0 or sub A, A, A
4. B = 2 ldi B, 2
6. C = [B] (loop start point) ldm C, [B]
8. A = A+C add A, A, C
10. B = B+1 ldi C, 1 — add B, B, C
14. C = 6 (loop start) ldi C, 6
16. If B≤ 6 (B < 7) branch to C ldi D, 7 — sub D, B, D — blz C, D
(Done)
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Example low-level code
Sum up the contents of memory locations 2–6
2. A = 0 ldi A, 0 or sub A, A, A
4. B = 2 ldi B, 2
6. C = [B] (loop start point) ldm C, [B]
8. A = A+C add A, A, C
10. B = B+1 ldi C, 1 — add B, B, C
14. C = 6 (loop start) ldi C, 6
16. If B≤ 6 (B < 7) branch to C ldi D, 7 — sub D, B, D — blz C, D
(Done)
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Example low-level code
Sum up the contents of memory locations 2–6
2. A = 0 ldi A, 0 or sub A, A, A
4. B = 2 ldi B, 2
6. C = [B] (loop start point) ldm C, [B]
8. A = A+C add A, A, C
10. B = B+1 ldi C, 1 — add B, B, C
14. C = 6 (loop start) ldi C, 6
16. If B≤ 6 (B < 7) branch to C ldi D, 7 — sub D, B, D — blz C, D
(Done)
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Example low-level code
Sum up the contents of memory locations 2–6
2. A = 0 ldi A, 0 or sub A, A, A
4. B = 2 ldi B, 2
6. C = [B] (loop start point) ldm C, [B]
8. A = A+C add A, A, C
10. B = B+1 ldi C, 1 — add B, B, C
14. C = 6 (loop start) ldi C, 6
16. If B≤ 6 (B < 7) branch to C ldi D, 7 — sub D, B, D — blz C, D
(Done)
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Example low-level code
Sum up the contents of memory locations 2–6
2. A = 0 ldi A, 0 or sub A, A, A
4. B = 2 ldi B, 2
6. C = [B] (loop start point) ldm C, [B]
8. A = A+C add A, A, C
10. B = B+1 ldi C, 1 — add B, B, C
14. C = 6 (loop start) ldi C, 6
16. If B≤ 6 (B < 7) branch to C ldi D, 7 — sub D, B, D — blz C, D
(Done)
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Example low-level code
Sum up the contents of memory locations 2–6
2. A = 0 ldi A, 0 or sub A, A, A
4. B = 2 ldi B, 2
6. C = [B] (loop start point) ldm C, [B]
8. A = A+C add A, A, C
10. B = B+1 ldi C, 1 — add B, B, C
14. C = 6 (loop start) ldi C, 6
16. If B≤ 6 (B < 7) branch to C ldi D, 7 — sub D, B, D — blz C, D
(Done)
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Error conditions
• What happens on overflow or underflow?
• Special register?
• Special value associated with each register?
• Single-instruction compare and branch?
• Advantages and disadvantages of each?
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Assemble to our encodings
• After assembling, can put program contents into memory, starting
at byte 2
• Compiling from higher-level languages also possible
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Example high-level code
Sum up the contents of memory locations 2-6
1. i = 0
2. For j from 2 to 6
3. i = i +[ j]
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Lesson
• With only a few registers and instructions, powerful actions are
possible
• Less time and power efficient than special-purpose hardware
design
• Instruction processors are flexible
• Allows massive use of a single type of IC
• Assembly is painful
• However, much better than doing hardware design
• Compilation also possible
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Today’s topics
• Architecture
• Assembly
• Compilation
• PIC16C74A
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Assigned reading
• M. M. Mano and C. R. Kime, Logic and Computer Design
Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,
2004
• Sections 7.1-7.9
• Read this and treat it as a reference for Chapter 10
• Note that, although they treat counters as special devices, they
are really just FSMs without (or with few) inputs
• You can understand almost everything in the context of
combinational networks and FSMs
• Chapter 7 is a catalog and cookbook
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Assigned reading
• Section 8.7
• Sections 9.1 and 9.2
• Chapter 10
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Computer geek culture references
• Building multicontroller-based devices for the fun of it
• http://www.bdmicro.com
• http://www.commlinx.com.au/microcontroller.htm
• http://members.home.nl/bzijlstra/
• http://www.robotcafe.com/dir/Companies/Hobby/more3.shtml
• Etc.
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Falling edge-triggered D flip-flop
• Use two stages of latches
• When clock is high
– First stage samples input w.o. changing second stage
– Second stage holds value
• When clock goes low
– First stage holds value and sets or resets second stage
– Second stage transmits first stage
• Q+ = D
• One of the most commonly used flip-flops
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Falling edge-triggered D flip-flop
DD
lk=
RR
SS
00
00
DD
DDDD
=1
DD
C
Clock high
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Falling edge-triggered D flip-flop
Holds D whenclock goes low
Holds D whenclock goes low
Q
Q
DD
Clk=1
RR
SS
00
00
DD
DDDD
=
DD
Clock switching
Inputs sampled on falling edge, outputs change after falling edge
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Falling edge-triggered D flip-flop
?
Clk=
RR
SS
D
0
DDDD
=
RR
SS
DD
0
D
Clock low
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Today’s topics
• Goals
• Future closely related courses
• Resources
• Quick summary of topics
• Review
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Goals
• Did you learn how to design, implement, and debug reasonably
efficient digital hardware and assembly language programs that
do useful things?
• Do you understand how hardware and software relate to each
other?
• Do you feel like you accomplished something worthwhile?
– I hope so – You did!
• Could you teach yourself (using books and experimentation) new
things related to the topics that were introduced in the class?
– I hope so, but there are also other classes that will accelerate
things
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Future closely related courses
ECE 303: Advanced Digital Logic Design
• Robert Dick or Seda Ogrenci Memik
• Hardware design
• Manual and automatic
• Deeper theory
• Labs go beyond ECE 203, but so does the power of the theory
and software tools
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Future closely related courses
• ECE 225: Fundamentals of Electronics
– More on details on circuit implementation, analog circuits
• ECE 361/362: Computer Architecture
– Efficient ways to combine the building blocks you learned
about in ECE 203 into working computers
• ECE 391/392: VLSI Systems Design
– Low-level analysis and design of complex digital systems
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Future closely related courses
• ECE 360: Introduction to Feedback Systems
– Control, e.g., the car lab
• ECE 230/231, CS 211: Programming for Computer Engineers
– High-level languages
• ECE 205: Fundamentals of Computer System Software
– Assembly language
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Future closely related courses
• CS 346: Design and Analysis of Algorithms
– Foundation for programming, automation
• ECE 357: Introduction to VLSI CAD
– Algorithms for physical design automation of digital circuits
• CS 322: Compiler Construction
– Closely related to FSMs, allows automation of FSM
implementation
• CS 343: Operating Systems
– Managing complexity in software systems, even on
µ-controllers
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Books
• Finding the right books can be difficult
• Stop by my office to see if these have what you’re searching for
• A. Aho, R. Sethi, and J. Ullman, Compilers principles, techniques,
and tools. Addison-Wesley, Reading, MA, 1986
• T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to
Algorithms. McGraw-Hill Book Company, NY, 1990
• M. R. Garey and D. S. Johnson, Computers and Intractability: A
Guide to the Theory of NP-Completeness. W. H. Freeman &
Company, NY, 1979
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Books
• J. Hennessy and D. Patterson, Computer Architecture: A
Quantitative Approach. Morgan Kaufmann Publishers, CA, 1995
• P. Horowitz and W. Hill, The Art of Electronics. Cambridge
University Press, 1989
• Z. Kohavi, Switching and Finite Automata Theory. McGraw-Hill
Book Company, NY, 1978
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Books
• D. Lancaster, TTL Cookbook. Howard W. Sams & Co., Inc., 1974
• D. Lancaster, CMOS Cookbook. Howard W. Sams & Co., Inc.,
1977
• B. G. Streetman, Solid State Electronic Devices. Prentice-Hall,
Englewood Cliffs, NJ, 1990
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Quick summary of topics
• Switches
• PMOS and NMOS transistors
• Using TTL
• Logic gates
• Transmission gates
• Two-level minimization
• Multiplexers, demultiplexers, encoders, decoders
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Quick summary of topics
• Computer arithmetic
• Latches and flip-flops
• Mealy and Moore finite state machine synthesis
• Number systems
• Base conversion
• Microcontroller assembly language
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