Intro & ISA.1

1/14

Instruction Set Architecture (ISA)(Ch: 2.1- 2.7, 2.10 4th ed)

Instructions: Language of the Computer

Dr. Khaled El-Ayat

Intro & ISA.2

Instructions = Language of the Machine

• Instruction: words of machine’s language

• Instruction set: instructions – CPU vocabulary

• Chapter overview:– difference in design principles of RISC & CISC

– other instruction set architectures

– MIPS instruction set architecture

• instruction type

• instruction format

• addressing modes

• No. of registers

1/14

Intro & ISA.3

1/14

RISC vs CISC

• RISC -- Reduced Instruction Set Computer -- philosophy– fixed instruction length

– load/store architecture• all operands of ALU instructions must be in registers

– limited addressing modes

– limited operations

• Implies– fewer instructions

– larger register file

– longer program

– good for pipelining

– simpler control

• CISC: Complex Instruction Set Computer

Intro & ISA.4

1/14

Characteristics of some CISC & RISC CPUs

Characteristic IBM370/168

VAX11/780

Intel80486

Motorola88000

MIPSR4000

year develop 1973 1978 1989 1988 1991

# instructions 208 303 235 51 94

inst.size (byt) 2-6 2-57 1-17 4 5

addrss mode 4 16 8 3 4

# GPregisters

16 16 8 32 32

control mem.Size (kbytes)

420 480 246 N/A N/A

Intro & ISA.5

1/14

CISC Ex: 80x86 Registers

031

GPR 0EAX

GPR 3EBX

GPR 1ECX

GPR 2EDX

GPR 6ESI

Code segment pointerCS

Stack segment pointer (top of stack)SS

Data segment pointer 0DS

Data segment pointer 1 ES

Data segment pointer 2FS

Data segment pointer 3GS

GPR 7EDI

GPR 5EBP

GPR 4ESP

EIP Instruction pointer (PC)

EFLAGS Condition codes

Name Use

Intro & ISA.6

1/14

CISC Ex: x86 Instructions have Variable lengths!

Variability is an issue, but is solved by MicroArchitecture e.g. Pentium II, III, IV

JE

JE EIP + displacement

Offset

CALL

MOV EBX, [EDI + 45]

PUSH

PUSH ESI

ADD w

ADD EAX, #6765

Reg

4 4 8

6

8 32

5 3

4 13 32

Immediate

Condition

MOV

1

w

1

d

8 8

TEST EDX, #42

7 1 8 32

TEST Postbyte Immediatew

Reg

f.

e.

d.

c.

b.

a.

CALL

Displacementr-m

postbyte

Displacement

Intro & ISA.7

1/14

Examples of Instruction Format Widths

Variable:

Fixed:

Hybrid:

……

X86, VAX, .

MIPS, Sparc, PowerPC

IBM 360/370, MIPS16, TMS320C54

Intro & ISA.8

1/14

Instruction Formats• If code size is most important,

use variable length instructions

• If performance is most important, use fixed length instructions

• Recent embedded machines (ARM, MIPS) added optional mode to execute subset of 16-bit wide instructions (Thumb, MIPS16); per procedure decide performance or density

• Some architectures actually exploring on-the-fly decompression for more density.

Intro & ISA.9

1/14

Instruction Set Architecture: What Must be Specified?

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction

• Instruction Format or Encoding– how is it decoded?

• Location of operands and result– where other than memory?

– how many explicit operands?

– how are memory operands located?

– which can or cannot be in memory?

• Data type and Size

• Operations– what are supported

• Successor instruction– jumps, conditions, branches

– fetch-decode-execute is implicit!

Intro & ISA.10

1/14

Typical OperationsData Movement Load (from memory)

Store (to memory)memory-to-memory moveregister-to-register moveinput (from I/O device)output (to I/O device)push, pop (to/from stack)

Arithmetic integer (binary + decimal) or FPAdd, Subtract, Multiply, Divide

Logical not, and, or, set, clear

Shift shift left/right, rotate left/right

Control (Jump/Branch) unconditional, conditional

Subroutine Linkage call, return

Interrupt trap, return

Synchronization test & set (atomic r-m-w)

String search, translateGraphics (MMX) parallel subword ops (4 16bit add)

Intro & ISA.11

1/14

Basic ISA Classes

Accumulator (1 register):

1 address add A acc acc + mem[A]

1+x address addx A acc acc + mem[A + x]

Stack:

0 address add tos tos + next

General Purpose Register :

2 address add A B EA[A] EA[A] + EA[B]

3 address add A B C EA[A] [B] + EA[C]

Load/Store:

3 address add Ra Rb Rc Ra Rb + Rc

load Ra Rb Ra mem[Rb]

store Ra Rb mem[Rb] Ra

Most real machines are hybrids of these:

Intro & ISA.12

1/14

General Purpose Registers Dominate° 1975-2000 all machines use general purpose registers

° Advantages of registers

• registers are faster than memory

• registers are easier for a compiler to use

- e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack

• registers can hold variables

- memory traffic is reduced, so program is sped up (since registers are faster than memory)

- code density improves (since register named with fewer bits than memory location)

Intro & ISA.13

1/14

MIPS R3000 Instruction Set Architecture: Registers

• Registers--32 general purpose registers– $zero (0) : 0

• 3 special purpose registers• PC: program counter

• Hi, Lo for multiply and divide

• Word length=32 bits

• In memory: byte addressable

R e g is te r $ 0 - $ 3 1

P C

H i

L o

Intro & ISA.14

1/14

MIPS ISA: Instruction Categories

• Arithmetic & logic (AL) add $s1, $s2, $s3 # $s1 $s2 + $s3 sub $s1, $s2, $s3 # $s1 $s2 - $s3 – each AL inst. has exactly 3 operands all in registers

• Load/store -- data transfer instructionlw $s1, x($s2) # $s1 = memory [$s2+x]sw $s1, x($s2) # memory[$s2+x]=$s1

• Jump & branchbeq $s2, $s3, L1 #branch to (PC)+L1 when ($s2) = ($s3)bne $s2, $s3, L1 #branch to (PC)+L1 when ($s2) ($s3)slt $s2, $s3, $s4 #set on less than, $s2=1 if ($s3) < ($s4)j L1 # goto L1

• floating point, memory management, etc.(will not be covered)

Intro & ISA.15

1/14

MIPS Instruction FormatsInstruction format: layout of the instruction

• 3 types of formats: R-type (regular)

I-type (Immediate)

J-type (Jump)

• R-type: 6 fields– op: operation code (6 bits)– rs: 1st register source operand (5)– rt: 2nd register source operand (5)– rd: register destination (5)– sa: shift amount (5)– function: select the variant of operation in op field (6)

OP rs rt rd sa funct

OP rs rt immediate

OP Target

Intro & ISA.16

1/14

Instruction Format::R-Type

• Example: add $8, $17, $18

OP=00, FUNC=40

• Other R-type instructionssub $1, $2, $3slt $1, $2, $3jr $ra(31) #jump register, for returning to the

calling procedure

OP rs rt rd sa funct

Intro & ISA.17

1/14

Instruction Format/I-type

• 4 fields, 32 bits

• Immediate (address ) field: 16 bits, holds a constant

• Example: load word -- lw $s1, 50($s2)

lw $s1, 48($s2) # $s1 = memory [$s2+48]

• Other I-type inst.add immediate -- addi $8, $9, 100branch on equal -- beq $1, $2, 25: goto (PC+4)+100 if $1=$2

O P rs r t im m e d ia te

Intro & ISA.18

1/14

Instruction Format/J-Type

• 2 fields: 32 bits• op: 6 bits• address field: 26 bits• Example: j 200 # go to location f(4*200)

• Other J type inst.:jal 200 # jump & link, goto location f(4*200)

$31(ra)= PC + 4

OP Target

Intro & ISA.19

1/14

j label #go to label

Jump Instruction Basics

• Instruction Format (J Format):

op 26-bit address

PC4

32

26

32

00

Intro & ISA.20

1/14

MIPS Addressing Modes• Register addressing

– operand is in a registere.g. add $8, $19, $18

• Base or displacement addressing

– operand: at memory location reg. + constant (base)e.g. lw $8, 200($19)

• Immediate addressing

– operand: constant, in inst.e.g. addi $8, $8, 4

• PC-relative addressing

– address = (PC) + constant in inst.e.g., bne $8, $21, Exit

• Pseudodirect addressing: jump address = PC(31-28) (concatenated with) jump constant*4

Intro & ISA.21

1/14

MIPS Addressing Mode Summary

Byte Halfword Word

Registers

Memory

Memory

Word

Memory

Word

Register

Register

1. Immediate addr essing

2. Register addr essing

3. Base addr essing

4. PC-r elative addr essing

5. Pseudodir ect addr essing

op rs rt

op rs rt

op rs rt

op

op

rs rt

Address

Address

Addr ess

rd . . .funct

Immediate

PC

PC

+

+

Intro & ISA.22

1/14

MIPS Organization So FarProcessor

Memory

32 bits

230

words

read/write addr

read data

write data

word address(binary)

0…00000…01000…10000…1100

1…1100Register File

src1 addr

src2 addr

dst addr

write data

32 bits

src1data

src2data

32registers

($zero - $ra)

32

32

3232

32

32

5

5

5

PC

ALU

32 32

3232

32

0 1 2 37654

byte address(big Endian)

FetchPC = PC+4

DecodeExec

Add32

324

Add32

32branch offset

Intro & ISA.23

1/14

bne $s0, $s1, Lbl #go to Lbl if $s0$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1

– Ex: if (i==j) h = i + j;

bne $s0, $s1, Lbl1add $s3, $s0, $s1

Lbl1: ...

MIPS Conditional Branch Instructions

• Instruction Format (I format):

op rs rt 16 bit offset

• Target Address = PC +4 + (offset * 4)

Intro & ISA.24

1/14

• Fr other type of branch conditions Use slt• Set on less than instruction:

slt $t0, $s0, $s1 # if $s0 < $s1 then# $t0 = 1 else # $t0 = 0

• Instruction format (R format):

2

More Branch Instructions

op rs rt rd funct

Intro & ISA.25

1/14

More Branch Instructions, Con’t• Can use slt, beq, bne, and the value 0 in register $zero to create other conditions– less than blt $s1, $s2, Label

– less than or equal to ble $s1, $s2, Label– greater than bgt $s1, $s2, Label– great than or equal to bge $s1, $s2, Label

slt $at, $s1, $s2 #$at set to 1 ifbne $at, $zero, Label # $s1 < $s2

• Such branches are included in the instruction set as pseudo instructions - recognized (and expanded) by the assembler

Intro & ISA.26

1/14

addi $sp, $sp, 4 #$sp = $sp + 4

slti $t0, $s2, 15#$t0 = 1 if $s2<15• Machine format (I format):

MIPS Immediate Instructions

op rs rt 16 bit immediate I format

• Small constants are used often in typical code

• Constant kept inside the instruction– Immediate format limits values to the range +215–1 to -215

Intro & ISA.27

1/14

• To load a 32 bit constant into a register, we use two instructions

• a new "load upper immediate" instruction

lui $t0, 1010101010101010

• Then must get the lower order bits right, use

ori $t0, $t0, 1010101010101010

How About Larger Constants?

16 0 8 1010101010101010

1010101010101010

0000000000000000 1010101010101010

0000000000000000

1010101010101010 1010101010101010

Intro & ISA.28

1/14

MIPS ISA So FarCategory Instr Op Code Example Meaning

Arithmetic

(R & I format)

add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s3

subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3

add immediate 8 addi $s1, $s2, 6 $s1 = $s2 + 6

or immediate 13 ori $s1, $s2, 6 $s1 = $s2 v 6

Data Transfer

(I format)

load word 35 lw $s1, 24($s2) $s1 = Memory($s2+24)

store word 43 sw $s1, 24($s2) Memory($s2+24) = $s1

load byte 32 lb $s1, 25($s2) $s1 = Memory($s2+25)

store byte 40 sb $s1, 25($s2) Memory($s2+25) = $s1

load upper imm 15 lui $s1, 6 $s1 = 6 * 216

Cond. Branch (I & R format)

br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to L

br on not equal 5 bne $s1, $s2, L if ($s1 !=$s2) go to L

set on less than 0 and 42 slt $s1, $s2, $s3 if ($s2<$s3) $s1=1 else $s1=0

set on less than immediate

10 slti $s1, $s2, 6 if ($s2<6) $s1=1 else $s1=0

Uncond. Jump (J & R format)

jump 2 j 2500 go to 10000

jump register 0 and 8 jr $t1 go to $t1

jump and link 3 jal 2500 go to 10000; $ra=PC+4

Intro & ISA.29

1/14

MIPS arithmetic instructionsInstruction Example Meaning Commentsadd add $1,$2,$3 $1 = $2 + $3 3 operands; exception possiblesubtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possibleadd immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possibleadd unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptionssubtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands; no exceptionsadd imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptionsmultiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed productmultiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned productdivide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder

Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient &

remainder Hi = $2 mod $3

Move from Hi mfhi $1 $1 = Hi Used to get copy of HiMove from Lo mflo $1 $1 = Lo Used to get copy of Lo

Intro & ISA.30

1/14

MIPS logical instructionsInstruction Example Meaning Comment

and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND

or or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical OR

xor xor $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical XOR

nor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NOR

and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant

or immediate ori $1,$2,10 $1 = $2 | 10 Logical OR reg, constant

xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant

shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant

shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant

shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend)

shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable

shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable

shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

Intro & ISA.31

1/14

MIPS data transfer instructionsInstruction Comment

SW 500(S4), S3 Store word

SH 502(S2), S3 Store half

SB 41(S3), S2 Store byte

LW S1, 30(S2) Load word

LH S1, 40(S3) Load halfword

LHU S1, 40(S3) Load halfword unsigned (no sign extension)

LB S1, 40(S3) Load byte

LBU S1, 40(S3) Load byte unsigned (no sign extension)

LUI S5, 40 Load Upper Immediate (16 bits shifted left by 16)

Why need LUI?0000 … 0000

LUI S5

S5

Intro & ISA.32

1/14

How shift instructions are implementedTwo kinds: logical-- value shifted in is always "0"

arithmetic-- on right shifts, sign extend

No arithmetic Left Shift – Overflow result

msb lsb"0" "0"

msb lsb

Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!

Intro & ISA.33

1/14

When does MIPS sign extend?• When value is sign extended, copy upper bit to full value:

Examples of sign extending 8 bits to 16 bits:

00001010 00000000 0000101010001100 11111111 10001100

• When is an immediate operand sign extended?– Arithmetic instructions (add, sub, etc.) always sign extend immediates – Logical instructions do not sign extend immediates (They are zero extended)– Load/Store address computations always sign extend immediates

• Multiply/Divide have no immediate operands however:– “unsigned” treat operands as unsigned

• The data loaded by the instructions lb and lh are extended as follows (“unsigned” don’t extend):– lbu, lhu are zero extended– lb, lh are sign extended

Intro & ISA.34

1/14

MIPS Compare and Branch Summary• Compare and Branch

– BEQ rs, rt, offset if R[rs] == R[rt] then PC-relative branch

– BNE rs, rt, offset <>

• Compare to zero and Branch– BLEZ rs, offset if R[rs] <= 0 then PC-relative branch

– BGTZ rs, offset >

– BLT <

– BGEZ >=

– BLTZAL rs, offset if R[rs] < 0 then branch and link (into R 31)

– BGEZAL >=!

• Almost all comparisons are against zero!

Intro & ISA.35

1/14

MIPS jump, branch, compare instructionsInstruction Example Meaning

branch on equal beq $1,$2,25 if ($1 == $2) go to PC+4+100Equal test; PC relative branch. Note: Offset field = 25

branch on not eq. bne $1,$2,25 if ($1!= $2) go to PC+4+100Not equal test; PC relative Note: Offset field = 25

set on less than slt $1,$2,$3 if ($2 < $3) $1=1; else $1=0Compare less than; 2’s comp.

set less than imm. slti $1,$2,100 if ($2 < 100) $1=1; else $1=0Compare < constant; 2’s comp.

set less than uns. sltu $1,$2,$3 if ($2 < $3) $1=1; else $1=0Compare less than; natural numbers

set l. t. imm. uns. sltiu $1,$2,100 if ($2 < 100) $1=1; else $1=0Compare < constant; natural numbers

jump j 2500 go to 10000Jump to target address Note: jump field = 2500

jump register jr $31 go to $31For switch, procedure return

jump and link jal 2500 $31 = PC + 4; go to 10000For procedure call. Note: jump field = 2500

Intro & ISA.36

1/14

Subroutine Calls & StacksStacking of Subroutine Calls & Returns and Environments:

A: CALL B

CALL C

C: RET

RET

B:

A

A B

A B C

A B

A

Some machines provide a memory stack as part of the architecture (e.g., VAX)

Sometimes stacks are implemented via software convention (e.g., MIPS)

Some machines provide stack support in hardware (Embedded processor)

Intro & ISA.37

1/14

0 zero constant 0

1 at reserved for assembler

2 v0 expression evaluation &

3 v1 function results

4 a0 arguments

5 a1

6 a2

7 a3

8 t0 temporary: caller saves

. . . (callee can clobber)

15 t7

MIPS: Software conventions for Registers

16 s0 callee saves

. . . (callee must save)

23 s7

24 t8 temporary (cont’d)

25 t9

26 k0 reserved for OS kernel

27 k1

28 gp Pointer to global area

29 sp Stack pointer

30 fp frame pointer

31 ra Return Address (HW)

Intro & ISA.38

1/14

Summary of MIPS I ISA• 32-bit fixed format inst (3 instruction formats / types)

• 32 32-bit GPR (R0 contains zero) and 32 FP registers (and HI LO)

– partitioned by software convention

• 3-address, reg-reg arithmetic instr.

• Single address mode for load/store: base+displacement• 16-bit immediate plus LUI

• Simple branch conditions

– compare against zero or two registers for =,– no integer condition codes