Interrupt programming

34
INTERRUPT PROGRAMMING

Transcript of Interrupt programming

Page 1: Interrupt programming

INTERRUPT PROGRAMMING

Page 2: Interrupt programming

OVERVIEW

8051 INTERRUPTS INTRODUCTION

INTERRUPT PRIORITY

PROGRAMMING TIMER INTERRUPTS

PROGRAMMING EXTERNAL HARDWARE

INTERRUPT

PROGRAMMING SERIAL

COMMUNICATION INTERRUPT

INTERRUPT PROGRAMMING IN C

Page 3: Interrupt programming

INTRODUCTION

An interrupt is the occurrence of a condition that causes

a temporary suspension of a program while the condition

is serviced by another program.

An interrupt is an external or internal event that disturbs

the microcontroller to inform it that a device needs its

service.

Page 4: Interrupt programming

Introduction

• Interrupts

vs polling

• Interrupt

service

routine

• Steps in

executing an

interrupt

• Six

interrupts in

8051

• Interrupt

vector table

• Enabling and

Disabling an

Interrupt

• Steps in

enabling an

Interrupt

Polling :

The microcontroller continuously monitors the status of a given

device. When the conditions met, it performs the service. After

that, it moves on to monitor the next device until every one is

serviced

Interrupt:

Whenever any device needs it service ,the device notifies the

microcontroller by sending it an interrupt signal. Upon

receiving an interrupt signal, the microcontroller interrupts

whatever it is doing and serves the device

Example: Event Management

Page 5: Interrupt programming

Introduction

• Interrupts vs

polling

• Interrupt

service

routine

• Steps in

executing an

interrupt

• Six

interrupts in

8051

• Interrupt

vector table

• Enabling and

Disabling an

Interrupt

• Steps in

enabling an

Interrupt

Interrupt Service Routine(ISR):

The (sub)program that deals with an interrupt is

called an Interrupt Service Routine or Interrupt

Handler.

or

The (sub)program that is executed when an interrupt

occurs is called an Interrupt Service Routine.

For every interrupt , there must be an interrupt

service routine and there is a fixed location in

memory that holds the address of its ISR

Page 6: Interrupt programming

Introduction

• Interrupts vs

polling

• Interrupt

service

routine

• Steps in

executing

an interrupt

• Six

interrupts in

8051

• Interrupt

vector table

• Enabling and

Disabling an

Interrupt

• Steps in

enabling an

Interrupt

Steps in Executing an Interrupt:

Upon receiving the interrupt signal the Microcontroller ,

finish current instruction and saves the PC on stack.

Jumps to a fixed location in memory depending on type

of interrupt

Starts to execute the interrupt service routine until

RETI (return from interrupt)

Upon executing the RETI the microcontroller returns to

the place where it was interrupted. Get pop PC from

stack

Page 7: Interrupt programming

Introduction

• Interrupts vs

polling

• Interrupt

service

routine

• Steps in

executing an

interrupt

• Six

interrupts

in 8051

• Interrupt

vector table

• Enabling and

Disabling an

Interrupt

• Steps in

enabling an

Interrupt

• Original 8051 has 6 sources of interrupts

– Reset

– Timer 0 overflow

– Timer 1 overflow

– External Interrupt 0

– External Interrupt 1

– Serial Port events (buffer full, buffer empty, etc)

• Enhanced version has 22 sources

– More timers, programmable counter array, ADC, more external interrupts, another serial port (UART)

Page 8: Interrupt programming

Introduction

• Interrupts vs

polling

• Interrupt

service

routine

• Steps in

executing an

interrupt

• Six

interrupts in

8051

• Interrupt

vector table

• Enabling and

Disabling an

Interrupt

• Steps in

enabling an

Interrupt

Each interrupt has a specific place in code memory where

program execution (interrupt service routine) begins.

POINT TO REEMEMBER:

LJMP is always be the first instruction to be executed

Page 9: Interrupt programming

Introduction

• Interrupts vs

polling

• Interrupt

service routine

• Steps in

executing an

interrupt

• Six interrupts

in 8051

• Interrupt

vector table

• Enabling and

Disabling an

Interrupt

• Steps in

enabling an

Interrupt

Upon reset , all interrupts are disabled,

meaning that none will be responded

to the microcontroller

The interrupts must be enabled by software in

order for the microcontroller to them

There is a bit addressable register called Interrupt

Enable(IE) that is responsible for enabling or

disabling the interrupts

Page 10: Interrupt programming

Introduction

• Interrupts vs

polling

• Interrupt

service

routine

• Steps in

executing an

interrupt

• Six

interrupts in

8051

• Interrupt

vector table

• Enabling and

Disabling an

Interrupt

• Steps in

enabling an

Interrupt

1. Bit D7 of the IE register (EA) must be set

to high to allow the rest of register to

take effect

2. The value of EA

If EA = 1, interrupts are enabled and will be

responded to if their corresponding bits in IE are high

If EA = 0, no interrupt will be responded to,

even if the associated bit in the IE register is high

MOV IE,#10010110B ;enable serial, timer 0, EX1

Or

SETB IE.7 ;EA=1, global enable

SETB IE.4 ;enable serial interrupt

SETB IE.1 ;enable Timer 0 interrupt

SETB IE.2 ;enable EX1

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INTERRUPT PRIORITY

• INTERRUPT

PRIORITY

UPON RESET

• INTERRUPT

PRIORITY

WITH IP

REGISTER

• INTERRUPT

INSIDE

INTERRUPT

When the 8051 is powered up, the

priorities are assigned according to the

table given below

Highest to Lowest Priority

External Interrupt 0 INT 0

Timer Interrupt 0 TF 0

External Interrupt 1 INT 1

Timer Interrupt 1 TF 1

Serial Communication RI + TI

Timer 2 (8052 only) TF 2

Page 12: Interrupt programming

INTERRUPT PRIORITY

• INTERRUPT

PRIORITY

UPON RESET

• INTERRUPT

PRIORITY

WITH IP

REGISTER

• INTERRUPT

INSIDE

INTERRUPT

We can alter the sequence of interrupt priority by assigning a

higher priority to any one of the interrupts by programming a

register called IP (interrupt priority)

To give a higher priority to any of the interrupts, we make the

corresponding bit in the IP register high

Interrupt Priority (IP) Register

IP.7: reserved

IP.6: reserved

IP.5: Timer 2 interrupt priority bit (8052 only)

IP.4: Serial port interrupt priority bit

IP.3: Timer 1 interrupt priority bit

IP.2: External interrupt 1 priority bit

IP.1: Timer 0 interrupt priority bit

IP.0: External interrupt 0 priority bit

--- PX0PT0PX1PT1PSPT2---

Page 13: Interrupt programming

INTERRUPT PRIORITY

• INTERRUPT

PRIORITY

UPON RESET

• INTERRUPT

PRIORITY

WITH IP

REGISTER

• INTERRUPT

INSIDE

INTERRUPT

A high-priority interrupt can interrupt a low-priority

interrupt

All interrupt are latched internally

Low-priority interrupt wait until 8051 has finished

servicing the high-priority interrupt

Page 14: Interrupt programming

Discuss what happens if interrupts TF1,

INT1 and INT0 are activated at the same

time. Assume that priority levels were set by

the power up reset

External Interrupt 0 INT 0

Timer Interrupt 0 TF 0

External Interrupt 1 INT 1

Timer Interrupt 1 TF 1

Serial

Communication

RI + TI

INT 0

INT 1

TF 1

Page 15: Interrupt programming

Program the IP register to assign the highest

priority to INT 1 then discuss what happens if

INT0,INT1 and TF0 are activated at the same

time

--- PX0PT0PX1PT1PSPT2---

0 0 0 0 0 1 0 0

MOV IP,#00000100B

SETB IP.2

INT 1

INT 0

TF 0

Page 16: Interrupt programming

Assume that after reset, the interrupt priority

is set by the instruction MOV

IP,#00001110B. Discuss the sequence in

which the interrupts are serviced

0 0 0 0 1 1 1 0--- PX0PT0PX1PT1PSPT2---

TF 0

INT 1

TF 1

.

.

TF 0

INT 1

TF 1

INT 0

RI + TI

INT 0

TF 0

INT 1

TF 1

RI + TI

Page 17: Interrupt programming

TIMER INTERRUPT PROGRAMMING

Page 18: Interrupt programming

The timer flag (TF) is raised when the timer rolls over

In polling TF, we have to wait until the TF is raised

The problem with this method is that the microcontroller is tied down

while waiting for TF to be raised, and can not do anything else is raised

In this way, the microcontroller can do other until it is notified that the

timer has rolled over

Using interrupts solves this problem and, avoids tying down the controller

If the timer interrupt in the IE register is enabled, whenever the timer rolls

over, TF is raised, and the microcontroller is interrupted in whatever it is doing

and jumps to the interrupt vector table to service the ISR

In this way, the microcontroller can do other until it is notified that the timer

has rolled over

JNB TF, Target

Page 19: Interrupt programming

Write a program that displays a value of ‘Y’ at port 0 and

‘N’ at port 2 and also generates a square wave of 10 KHz,

with Timer 0 in Mode 2 at port pi P1.2.XTAL = 22MHz

ORG 0000H

LJMP MAIN

ORG 000BH ;Timer 0 interrupt vector

CPL P1.0 ;Toggle port bit

RETI ;Return from ISR to Main

program

ORG 0030H ;Main Program entry point

MAIN: MOV TMOD,#02H ;

MOV TH0,#0B6H ;50 us delay

MOV IE,#82H ;Enable timer 0 interrupt

SETB TR0 ;Start timer

BACK: MOV P0,#’Y’

MOV P2,#’N’

SJMP BACK

END

TIMER 1 TIMER 0

GATE C/T M1 M0 GATE C/T M1 M0

Page 20: Interrupt programming

Write a program to generate two square waves of 5KHz

and 25KHz frequency at pin P1.3 and P2.3 respectively.

Assume XTAL = 22MHz

ORG 0000H ; avoid the Interrupt Vector

LJMP MAIN

ORG 000BH ; Interrupt vector for Timer 0

CPL P1.3

RETI

ORG 001BH ; Interrupt vector for Timer 1

CPL P2.3

RETI

ORG 0030H

MAIN: MOV TMOD,#22H ; both Timers are initialized for mode 2

MOV IE,#8AH ; enable the Timer 0 and Timer 1 Interrupts

MOV TH0,#048H ; count value for 5KHz square wave

MOV TH1,#0B6H ; count value for 25KHz square wave

SETB TR0 ; start Timer 0

SETB TR1 ; start Timer 1

WAIT: SJMP WAIT ; keep waiting for the roll off of either Timer

END

Page 21: Interrupt programming

Assume that Timer 1 is programmed in mode 2,

TH1=F5H, and the IE bit for Timer 1 is enabled.

Explain how the interrupt for the timer works.

After the Timer 1 is started with instruction SETB TR1, the timer will count

up from F5H to FFH on its own while the 8051 is executing other tasks. Upon

rolling over from FFH to 00H, the TF1 flag is raised, which will interrupt the

8051 in whatever it is doing and force it to jump to memory location 001BH to

execute the ISR belonging to this interrupt

The last two instructions of the ISR for Timer 0 are:

CLR TF0

RETI

There is no need for CLR TF0 since the RETI instruction does it

EXAMPLE: ARRIVAL OF GUEST

Page 22: Interrupt programming

OVERVIEW

8051 INTERRUPTS INTRODUCTION

INTERRUPT PRIORITY

PROGRAMMING TIMER INTERRUPTS

PROGRAMMING EXTERNAL

HARDWARE INTERRUPT

PROGRAMMING SERIAL

COMMUNICATION INTERRUPT

INTERRUPT PROGRAMMING IN C

Page 23: Interrupt programming

INT 0

INT 1

INTERRUPT ENABLE REGISTER

Page 24: Interrupt programming

HOW TO ACTIVATE ?

• LEVEL TRIGGERED INTERRUPT

• EDGE TRIGGERED INTERRUPT

Page 25: Interrupt programming

LEVEL TRIGGERED INTERRUPT

INT 0 and INT 1 pins are normally high and if a low level

signal is applied to them, it triggers the interrupt

The low-level signal at the INT pin must be removed

before the execution of the last instruction of the ISR,

RETI; otherwise, another interrupt will be generated.

Page 26: Interrupt programming

Two switches are connected to pins P3.2 and P3.3. When a switch

is pressed, the corresponding line goes low. Write a program to

1. light all LEDs connected to port 0 if the first switch is pressed

2. light all LEDs connected to port 2 if the second switch is

pressed.ORG 0000H

LJMP MAIN

---------------------------------

ORG 0003H

LED1: MOV P0,#OFFH

MOV R0,#255

DJNZ R0,LED1

RETI

---------------------------------

ORG 0013H

LED2: MOV P2,#0FFH

MOV R0,#255

DJNZ R0,LED2

RETI

---------------------------------

ORG 0030H

MAIN: MOV IE,#85H

HERE: SJM HERE

END

Page 27: Interrupt programming

Pins P3.2 and P3.3 are used for normal I/O unless the INT0 and

INT1 bits in the IE register are enabled.

After the hardware interrupts in the IE register are enabled, the

controller keeps sampling the INTn pin for a low-level signal

once each machine cycle

According to one manufacturer’s data sheet,

The pin must be held in a low state until the start of the

execution of ISR

If the INTn pin is brought back to a logic high before the

start of the execution of ISR there will be no interrupt

If INTn pin is left at a logic low after the RETI instruction

of the ISR, another interrupt will be activated after one

instruction is executed

Page 28: Interrupt programming

To ensure the activation of the hardware interrupt

at the INTn pin, make sure that the duration of the

low-level signal is around 4 machine cycles

Page 29: Interrupt programming

Edge Triggering Interrupt

To make INT0 and INT1 edge triggered interrupts, we must

program the bits of the TCON register

The TCON register holds, among other bits, the IT0 and IT1

flag bits that determine level- or edge-triggered mode of the

hardware interrupt

TF1 IT0IE0IT1IE1TR0TF0TR1

Page 30: Interrupt programming

Generate from all pins of Port 0, a square

wave which is half the frequency of the

signal applied at INT0 pin

ORG 0000H

LJMP MAIN

----------------------------------------

ORG 0003H

CPL P0

RETI

-----------------------------------------

ORG 0030H

MAIN: SETB TCON.0

MOV IE,#81H

HERE: SJMP HERE

END

Page 31: Interrupt programming

PROGRAMMING SERIAL

COMMUNICATION INTERRUPT

In the 8051 there is only one interrupt set aside for

serial communication

This interrupt is used to both send and receive

data

If the interrupt bit in the IE register (IE.4) is enabled,

when RI or TI is raised the 8051 gets interrupted and

jumps to memory location 0023H to execute the ISR

Page 32: Interrupt programming

• In the vast applications, the serial interrupt is

used mainly for receiving data and is never

used for sending data serially.

• The last instruction before RETI is the clearing

RI or TI flags since there is only one interrupt

for both receive and transfer serial data and the

8051 does not know who generated it

Page 33: Interrupt programming

It can also assign a register bank o an ISR. This

avoids code overhead due to thee pushes and

pops of the R0 – R7 registers.

INTERRUPT

PROGRAMMING IN C

The 8051 C compilers have extensive support

for the 8051 interrupts with two major features

as follows

They assign a unique number to each of the 8051

interrupts as shown in the given table

INTERRUPT NAME ASSIGNED NUMBER

EXTERNAL INTERRUPT 0 INT0 0

TIMER INTERRUPT 0 TF0 1

EXTERNAL INTERRUPT 1 INT1 2

TIMER INTERRUPT 1 TF1 3

SERIAL COMMUNICATION RI+TI 4

TIMER 2 TF2 5

Page 34: Interrupt programming

• Write a C program that continuously gets a single bit of data

from P1.7 and sends it to P1.0 while simultaneously creating a

square wave of 200micro seconds period on pin P2.5

#include <reg51.h>

sbit SW = P1^7

sbit IND = P1^0

sbit WAVE = P2^5

void timer0(void) interrupt;

{

WAVE = - WAVE;

}

void main

{

SW = 1;

TMOD = 0x02;

TH0 = 0xA4;

IE = 0x82;

while(1)

{

IND = SW;

}

}