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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN
0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME
150
FPGA IMPLEMENTATION OF VEDIC MULTIPLIER
Kavita1, Umesh Goyal2
1E & Ec Department, PEC University of Technology, Chandigarh, India, 2E & Ec Department, PEC University of Technology, Chandigarh, India,
ABSTRACT
As Multipliers plays an important role in many fields like signal processing,
embedded systems, so the demand to have an efficient and fast multiplier is increasing.
This paper presents an efficient algorithm of Vedic Multiplier. Vedic Multiplier as
compared to other multipliers like array multiplier, Wallace tree multiplier, booth
multiplier, Modified booth multiplier etc. carry out the multiplication of two numbers
very efficiently and Vedic Multiplication process as compared to others is also fast. This
paper briefly describes the methods used for Vedic Multiplication and the flow of
multiplication with the help of flow chart. The hardware implementation of Vedic
Multiplier is carried out using Spartan 3E kit using Xilinx ISE Design Suite 14.2 tool for
simulation and the corresponding results are shown.
Keywords: Multiplier, Vedic, Xilinx, Multiplication
1. INTRODUCTION
Due to the growth of signal processing and demand of high speed processing, the
multipliers have a great role to play. The multipliers are used to multiply two numbers.
The more efficient and fast a multiplier is, the more it will be suitable for fast processing
applications. So an algorithm is developed for fast multiplication of two numbers. This
will be discussed later on in this paper.
INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN
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ISSN 0976 - 6480 (Print) ISSN 0976 - 6499 (Online) Volume 4, Issue 4, May – June 2013, pp. 150-158 © IAEME: www.iaeme.com/ijaret.asp Journal Impact Factor (2013): 5.8376 (Calculated by GISI) www.jifactor.com
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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN
0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME
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2. VEDIC MULTIPLIER
The word “Vedas” which literarily means knowledge has derivational meaning as
principle and limitless store-house of all knowledge. The word Veda also refers to the
sacred ancient Hindu literature which is divided into four volumes. Vedas initially were
passed from previous generation to next generation orally. Later they were transcribed in
Sanskrit [1].
Vedas include information from many subjects such as from religion, astronomy,
architecture, mathematics, medicine etc. Vedic mathematics is not only a mathematical
wonder but also it is logical. That’s why Vedic mathematics has such a degree of
prominence which cannot be disapproved. Due to these characteristics, Vedic
mathematics has already crossed the boundaries of India and has become a leading topic
of research abroad. Vedic mathematics deals with various mathematical operations [2].
The system of Vedic mathematics is based on 16 Sutras – formulas and 13 Up-sutras or
Corollaries [3].
The 16 Sutras are:
1. Ekadhikina Purvena – By one more than the previous one.
2. Nikhilam Navatashcaramam Dashatah – All from 9 and last from 10.
3. Urdhva-tiryakbhyam – Vertically and crosswise.
4. Paraavartya Yojayet – Transpose and adjust.
5. Shunyam Saamyassamuccaye – When the sum is the same that sum is zero.
6. Anurupye Shunyamanyat – If one is in ratio, the other is zero.
7. Sankalana-vyayakalanabhyam – By addition and by subtraction.
8. Puranapuranabyham – By the completion and noncompletion.
9. Chalana-Kalanabyham – Differences and Similarities.
10. Yaavadunam – Whatever the extent of its deficiency.
11. Vyashtisamanstih – Part and Whole.
12. Shesanyankena Charamena – The remainders by the last digit.
13. Sopaantyadvayamantyam – The ultimate and twice the penultimate.
14. Ekanyunena Purvena – By one less than the previous one.
15. Gunitasamuchyah – The product of the sum is equal to the sum of the product.
16. Gunakasamuchyah – The factors of the sum is equal to the sum of the factors [4].
3. GUNAKASAMUCHYAH SUTRA
In this method, if we want to multiply two numbers a and b (each 4 bit). Then their
partial product terms are formed and they are added successively according to the normal
multiplication process using 4 bit adder to obtain the final result. The arrangement to two
4 bit numbers is sown below in fig. 1. This figure shows the 4 bits of both numbers a and
b denoted as (��, ��, ��, ��� � ���, ��, ��, ���. The multiplication of these two numbers
is shown with their 16 partial product terms. Now 4 bit adder is used to add the terms
according to the multiplication process to obtain the final result.
International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN
0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME
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Fig. 1 Multiplication of two 4 bit numbers
Now let us see the flow code to generate these partial product terms using VHDL. The flow
chart is shown as below in fig. 2:
Fig. 2 Flow Chart of Partial Product generator
Start
Initialize a, b (4 bit numbers)
PP1 � a(1) and b
PP2 a(2) and b
PP3 � a(3) and b
Initialize Partial Products PP0
to PP3 to zero (8 bits)
PP0 �a(0) and b
Stop
International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN
0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME
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The scheme for Vedic multiplication is followed as below in fig. 3. In this 4 bit Vedic adders
are used to obtain the result. A partial product generator is used to obtain the partial products
after multiplication of different bits of the numbers.
Fig. 3 Flow Chart of Vedic Multiplier
Start
Initialize Multiplicand X and multiplier Y
(both 4 bit) and output (8 bit)
Partial Product generator
16 partial products generated
Vedic 4 bit adder
Stop
Vedic 4 bit adder
Vedic 4 bit adder
Result Obtained
International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN
0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME
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S0 S1 c0 C1
Sum C2
Carry
3.1.Vedic 4 bit adder
Vedic 4 bit adder is used to add 4 bits and thus generating sum bit and a carry bit. In
this adder two bits are added first to obtain the partial sum and carry bit. Then the remaining
two bits are added to obtain other partial sum and carry bit. Now to obtain the final sum bit
the partial sum bits are added and in this process a carry bit if present is also generated. Now
these three partial carry bits are processed to obtain the final carry bit.
Fig. 4 Flow Chart of 4 bit Vedic Adder
Start
Initialize 4 input bits as a0, a1, a2, a3,
sum bit and carry out bit
Add first two bits a0
and a1
Add other two bits
a2 and a3
Process c0, c1 and
c2
Stop
Add s0 and s1
Result Obtained
International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN
0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME
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4. HARDWARE IMPLEMENTATION
This section presents the hardware design of the system. The schematic diagram of
the circuit being designed is shown in this section. This section also describes the
implementation of software on the system designed.
4.1.Schematic Design of the circuit
Fig. 5 Schematic Design of the system
SW0
SW1
SW2
SW3
L13
L14
H18
N17
SPARTAN 3E
FPGA
XC3S500E
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
1
0
0
1
F12
E12
E11
F11
C11
D11
E9
F9
50 MHz Oscillator
5 VDC, 2A Supply
100-240V AC Input
3.3V
Regulator 2.5V Regulator
1.2V Regulator
International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN
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Fig. 6 Complete Setup of the system
4.2.Implementation Result
Fig. 7 Implementation Result
International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN
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5. CONCLUSION
The Vedic Multiplier designed here is an efficient and fast multiplier as compared to
other multipliers. The number of Look up tables required to implement this multiplier is also
less as compared to other multipliers. The result of this multiplier is shown below:
Fig. 8 Simulation Results of 4 bit Vedic Adder
Fig. 9 Simulation Results of 4x4 bit Vedic Multiplier
International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN
0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 4, May – June (2013), © IAEME
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The simulation results of 4x4 bit Vedic Multiplier in terms of number of occupied slices,
number of 4 inputs LUT and IOBs are shown in Table. 1.
Table 1: Xilinx Results for 4x4 bits Vedic Multiplier
PARAMETER Used Available Utilization
Number of 4 input LUTs 16 63400 1%
Number of occupied Slices 6 15850 1%
Number of bonded IOBs 16 210 7%
Thus the result shows that number of 4 input LUTs required is 16 and percentage utilization
of resources is 1%. Similarly other results are shown based on other parameters like number
of occupied slices and number of bonded IOBs.
REFERENCES
[1] D.Kishore Kumar, A.Rajakumari, Modified Architecture of Vedic Multiplier for High
Speed Applications, International Journal of Engineering Research & Technology, Vol. 1
Issue 6, August – 2012.
[2] Pushpalata Verma, K. K. Mehta, Implementation of efficient multiplier based on Vedic
Mathematics using EDA tool, International Journal of Engineering and Advance
Technology,Volume-1, Issue-5, June 2012.
[3] G.Ganesh Kumar, V.Charishma, Design of high Speed Vedic Multiplier using Vedic
Mathematic Techniques, International Journal of Scientific and Research Publication,
Vol 2, Issue 3, March 2012.
[4] Ramachandran.S*, Kirti.S.Pande, Design, Implementation and Performance Analysis of
an Integrated Vedic Multiplier Architecture, International journal of Computational
Engineering Research.
[5] Sharada Kesarkar and Prof. Prabha Kasliwal, “FPGA Implementation of Scalable Queue
Manager”, International Journal of Electronics and Communication Engineering &
Technology (IJECET), Volume 4, Issue 1, 2013, pp. 79 - 84, ISSN Print: 0976- 6464,
ISSN Online: 0976 –6472.
[6] B.K.V.Prasad, P.Satishkumar, B.Stephencharles and T.Prasad, “Low Power Design of
Wallance Tree Multiplier”, International Journal of Electronics and Communication
Engineering & Technology (IJECET), Volume 3, Issue 3, 2012, pp. 258 - 264,
ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.