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INTERNAL ASSESSMENT TEST – 2 Date : 06 /10/2017 Max Marks : 50 Subject & Code : EMBEDDED COMPUTING SYSTEMS / 10CS72 Section : 7 – A, B &C Name of Faculty : Mrs Jyoti. R. Desai & Ms. K. J Bhuvaneswari Time : 8.30 a.m. to 10 a.m.

Answer any five questions

1. Explain any four I/O devices with neat diagram.

z Timers and Counters

z A/D and D/A Converters

z Keyboards

z LEDs

z Displays

z Touchscreens

Refer Page:169(Book:Wayne)

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2. a)

Explain CPU bus and bus protocols.

CPU BUS:

z CPU communicates with the memory and devices through the bus.

y Shared communication medium.

z A bus is:

y A set of wires.

y A communications protocol by which the CPU, memory, and devices

communicate

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PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -100

Department of Computer Science and Engineering

B.E 7th Semester

b)

BUS PROTOCOLS:

z Bus protocol determines how devices communicate.

z four-cycle handshake is the main part of the bus protocol.

z The handshake uses a pair of wires dedicated to the handshake:

y enq (meaning enquiry) and

y ack (meaning acknowledge).

z Device 1 raises enq.

z Device 2 responds with ack.

z Device 2 lowers ack once it has finished.

z Device 1 lowers enq.

At the end of the handshake, both handshaking signals are low.

With a neat diagram, explain the bus with a DMA controller.

z Direct memory access (DMA) performs data transfers which is not controlled

by the CPU.

z DMA transfer is controlled by DMA controller.

z DMA controller is a separate unit.

z After gaining control, the DMA controller performs read and write operations

directly between devices and memory.

z CPU can’t use bus while DMA operates.

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PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -100

Department of Computer Science and Engineering

B.E 7th Semester

The DMA requires the CPU to provide two additional bus signals:

o The bus request is an input to the CPU through which DMA

controllers ask for ownership of the bus.

o The bus grant signals that the bus has been granted to the DMA

controller.

A device that can initiate its own bus transfer is known as a bus master

DMA controller uses the classic four-cycle handshake

1.bus request is asserted by the DMA controller

2.bus grant is asserted by the CPU when the bus is ready

3.Once the DMA controller is bus master, it can perform reads and writes.

(Memory and devices do not know whether a read or write is performed by

the CPU or by a DMA controller)

4.DMA controller returns the bus to the CPU by deasserting the bus

request, causing the CPU to deassert the bus grant.

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PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -100

Department of Computer Science and Engineering

B.E 7th Semester

DMA OPERATION:

The CPU controls the DMA operation through registers in the DMA

controller.

A typical DMA controller includes the following three registers:

o A starting address register specifies where the transfer is to begin.

o A length register specifies the number of words to be transferred.

o A status register allows the DMA controller to be operated by the

CPU.

What is the CPU doing during a DMA transfer? It cannot use the bus !

If the CPU has enough instructions and data in the cache and registers, it will

continue to do useful work for quite some time and may not notice the DMA transfer.

3. a)

Explain logic analyzer with a neat labeled diagram in debugging techniques.

A logic analyzer is an array of inexpensive oscilloscopes

The analyzer can sample many different signals simultaneously

It can capture millions of samples of data on different channels, providing a

much larger time window into the operation of the machine

The logic analyzer records the values on the signals into an internal memory

and then displays the results on a display once the memory is full or the run is

aborted.

Logic Analyzer acquires data in either of two modes

State Mode

Timing Mode

State and timing mode represent different ways of sampling the values

The system’s data signals are sampled at a latch within the logic analyzer;

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PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -100

Department of Computer Science and Engineering

B.E 7th Semester

b)

the latch is controlled by either the system clock or the internal logic analyzer

sampling clock, depending on whether the analyzer is being used in state or

timing mode.

Each sample is copied into a vector memory (fig 4.27, page 187

Book:Wayne).

The latch, timing circuitry, sample memory, and controller must be designed

to run at high speed if it operates in timing mode

After sampling, the embedded microprocessor takes control of the display of

the data, captured in the sample memory.

Explain ARM AMBA bus with a neat diagram.

Since ARM CPU is manufactured by different vendors, It provides

specification for the ARM Bus.

The AMBA bus supports CPUs, memories, and peripherals integrated in a

system-on-silicon.

Two varieties:

o AMBA high-performance bus (AHB) is for high speed transfers

o AMBA peripherals bus (APB) is lower-speed, lower cost.

AMBA high performance bus (AHB) is optimized for high speed data

transfers and is directly connected to CPU.

AHB supports pipelining, burst transfers, split transactions, multiple bus

masters.

A bridge connects AHB to APB.

APB is simple, easy to implement and relatively consumes little power.

All devices are slaves on APB.

It does not provide pipelining and hence the bus logic is simple

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PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -100

Department of Computer Science and Engineering

B.E 7th Semester

4. a)

Justify PC as a platform for embedded systems

PC is the basis for embedded computing design

Advantages:

o cheap and easy to get;

o rich and familiar software environment.

Disadvantages:

o requires a lot of hardware resources;

o not well-adapted to real-time.

(Refer diagram 4.25 in Book:Wayne)

PCI (Peripheral Component Interconnect) :

o dominant high-performance system bus today.

o uses high-speed data transmission techniques

o standard for high-speed interfacing

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PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -100

Department of Computer Science and Engineering

B.E 7th Semester

b)

o original PCI standard allowed 33 M Hz and achieved 264 MB/s using

64-bit transfers

o revised PCI standard allows 66 MHz giving transfer rate of 524 MB/s

with 64-bit wide transfers.

o The width of the bus both increases the cost of an interface to the bus

and makes the physical connection to the bus more complicated

o Hence PC manufacturers have introduced serial buses for high speed

and low cost

USB (Universal Serial Bus), Firewire (IEEE 1394) are the two major serial

buses.

They provide relatively low-cost serial interface with high speed.

They offer high transfer rates using simple connectors

They also allow devices to be chained together

IBM PC uses BIOS (Basic I/O System) to implement low-level functions:

o boot-up;

o minimal device drivers.

BIOS has become a generic term for the lowest-level system software.

Explain alarm clock interface and alarm clock requirements.

Refer Fig 4.34 in book wayne for clock interface.

z Set time: hold set time, depress hour, minute.

z Set alarm time: hold set alarm, depress hour, minute.

z Turn alarm on/off: depress alarm on/off.

Requirements refer page 197 in book wayne

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PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -100

Department of Computer Science and Engineering

B.E 7th Semester

5. Explain types of Kernel and its services with an appropriate diagram.

Kernel services:

For diagram Refer page 383 in book Shibu

Kernel

o Core of the OS

o Manages system resources

o Communicates between the h/w

o It is a layer of abstraction between system resources and

applications

o Contains system libraries

It has different services….

Process Management

Sets up memory space for processes

Allocates system resources

Schedules and manages execution of process

Sets up Process Control Block (PCB)

Manages inter-process communication

Creates and terminates process

Memory Management

o Has the Memory Management Unit

Swaps pages in and out of RAM

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Department of Computer Science and Engineering

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Allocates and de-allocates memory spaces

Manages memory (paging and segmentation)

Translates logic address to physical memory

address

File System Management

o Creates, modifies and delete files

o Manages the file system

o Creates and manages file tables

o Provides automatic allocation of space for files on

secondary storage

Provides naming convention for files

Device or I/O Management

Maintains a registry of all the i/o devices connected to the system

Routes the information from i/o devices to the memory and cpu

modules

Kernel dynamically updates the list of available devices

Interrupt Handlers

Secondary storage management

Protection systems.

Types of Kernel:

Two ways of designing the kernel

o Monolithic Kernel

o Micro Kernel

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PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -100

Department of Computer Science and Engineering

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Monolithic Kernel:

Here, all kernel services run in the kernel space

Hence all the modules run in the same space under a single kernel thread.

The kernel modules are tightly integrated which utilizes the hardware

effectively.

Drawback is that the whole system crashes in case of any error in any

module

Examples are Linux, Solaris, MS-DOS

Micro Kernel:

Here, all kernel services do not run in the kernel space. Only essential

set of operations are in the kernel.

The remaining modules run as servers in the user space.

This is a highly modular design.

Memory and process management, timer systems, interrupt handlers

are essential services and a part of the microkernel.

6. Explain how threads and processes are used in RTOS.

Process:

Process is an instance of a program in execution.

Multiple instances of the same program can execute simultaneously

Structure of process

Process Life cycle (Refer page no.391 in book Shibu)

Threads:

A Thread is a single sequential flow of control within a process

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PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -100

Department of Computer Science and Engineering

B.E 7th Semester

It is also known as light weight process

A process can have multiple threads

Threads of the same process share the same address space (i.e., same data

memory, code and heap memory areas)

Threads maintain their own thread status (registers values and stack.

Need for threaded programming….

o Very lengthy application program

o Contains various sub-operations like

getting input from i/o devices

Performing internal calculations

Updating some i/o devices etc..

Multi threading:

The process is split up into threads which execute a portion of a process.

Advantages :-

o They share the address space

Better utilization of memory

Reduces inter thread communication

o When one thread enters wait state, CPU is utilized by other

threads, speeding up execution

o CPU is engaged all the time.

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PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -100

Department of Computer Science and Engineering

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7. Explain the following terms in RTOS: a)Multi Processing

b)Multi Tasking

c)Shared Memory

Multi-processing :- Ability of a system to execute multiple processes

simultaneously

Multiprocessing systems have multiple CPUs and can execute

multiple processes simultaneously.

In a uniprocessor system, it is not possible to execute multiple

processes simultaneously.

Multi-tasking :- Ability of the OS to have multiple programs in memory

which are ready for execution and switch the CPU among different processes

is multi-tasking.

Shared memory is memory that may be simultaneously accessed by multiple

programs to provide communication among them or avoid redundant copies.

Shared memory is an efficient means of passing data between programs.

Depending on context, programs may run on a single processor or on

multiple separate processors.

Shared memory implementation is dependent on kernel.

Different mechanisms adopted are:

Pipes

Memory Mapped Objects.

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8. a)

Three processes with process IDs P1, P2, P3 with estimated completion time 10, 5, 7

ms respectively enters the ready queue together in the order P1,P2,P3. Calculate the

waiting time and Turn Around Time for each process and average waiting time and

Turn Around Time (Assuming there is no I/O waiting for the processes) using FCFS

scheduling.

Waiting time:

P1=0ms

P2=10ms

P3=15ms

Average Waiting time=8.33ms

Turn Around Time:

P1=10ms

P2=15ms

P3=22ms

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PESIT Bangalore South Campus Hosur road, 1km before Electronic City, Bengaluru -100

Department of Computer Science and Engineering

B.E 7th Semester

b)

Average Turn Around Time=15.66ms

Three processes with process IDs P1, P2, P3 with estimated completion time 6, 4, 2

ms respectively, enters the ready queue together in the order P1, P2, P3. Calculate the

waiting time and Turn Around Time for each process and the average waiting time

and Turn Around Time(Assuming there is no I/O waiting for the processes) in RR

algorithm with time slice = 2 ms.

Waiting time:

P1=6ms

P2=6ms

P3=4ms

Average Waiting time=5.33ms

Turn Around Time:

P1=12ms

P2=10ms

P3=6ms

Average Turn Around Time=9.33ms.

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