Inter –integrated circuit (i2c)

7/29/2019 Inter integrated circuit (i2c)

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INTER INTEGRATED CIRCUIT (I2C)


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I2C INTRODUCTION

Multi-master serial single-ended bus

developed by Philips , is used to attach low-

speed peripherals to a motherboard,

embedded system, cell phones etc


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I2C PROTOCOL

2 wire Interface communication.

Ie 2 active wires SDA (data line )

-- SCK (clock line).Both are bidirectional bus.


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ADDRESSING

Each device has unique address, no matter

whether it is an MCU, LCD driver, memory, or

ASIC. Each of these chips can act as a

receiver and/or transmitter, depending on thefunctionality

Two mode of addressing 7 bit addresing -127 devices can be connected to

bus

10 bit addressing - 1024 devices


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MODE OF COMMUNICATION

Multi-master mode of communication.

Device act as both slave and master,

No slave select pin , addressing is used to

identify each devices.

4 -Mode of communication: - Master transmitter

Master receiver Slave transmitter

Slave receiver


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BUS CONDITION IN I2C COMMUNIATION

Start condition(S) when SDA is pulled low while SCL stayshigh

Stop(P) data line to allow it to be pulled up while SCL is constantly

high

ACK

Restart


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TIMING DIAGRAM

Start and stop condition


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ACKNOWLEDGE FROM A SLAVE DEVICE

soon as the master pulls SCL low tocomplete the transmission of the byte (1),SDA will be pulled low by the slave (2).

The master now issues a clock pulse on theSCL line (3). the slave will release the SDAline upon completion of this clock pulse (4).


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SLAVE TRANSMITTER MODE


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SLAVE RECIEVER MODE


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REGISTERS ASSOCIATED WITH I2C


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I2C CONTROL REGISTER--I2CONSET

I2EN I2C I t f E bl Wh I2EN i 1


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I2EN I2C Interface Enable. When I2EN is 1,the I2C interface is enabled. When I2EN is 0,the SDA and SCL input signals are ignored.

STA is the START flag. Setting this bit causesthe I2C interface to enter master mode andtransmit a START condition or transmit arepeated START condition if it is already inmaster mode.

STO is the STOP flag. Setting this bit causesthe I2C interface to transmit a STOPconditionin master mode, or recover from an errorcondition in slave mode

SI is the I2C Interrupt Flag. This bit is set whenthe I2C state changes.

AA is the Assert Acknowledge Flag. When set to1, an acknowledge (low level to SDA) will be

returned during the acknowledge clock pulse on


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I2C CONTROL CLEAR REGISTER The I2CONCLR registers control clearing of bits

in the I2CON register that controls operation ofthe I2C interface. Writing a one to a bit of thisregister causes the corresponding bit in the I2C

control register to be cleared


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AAC is the Assert Acknowledge Clear bit.Writing a 1 to this bit clears the AA bit in the I2CONSETregister. Writing 0 has no effect.

SIC is the I2C Interrupt Clear bit. Writing a 1 to

this bit clears the SI bit in the I2CONSET register.Writing 0 has no effect

STAC is the Start flag Clear bit. Writing a 1 to this bitclears the STA bit in the I2CONSET register. Writing 0has no effect.

I2ENC is the I2C Interface Disable bit. Writing a 1 tothis bit clears the I2EN bit in the I2CONSET register.Writing 0 has no effect.


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I2C STATUS REGISTER (I2STAT) Each I2C Status register reflects the condition of

the corresponding I2C interface. The I2C Status

register is Read-Only.

The three least significant bits are always 0. Taken as a byte, thestatus register contentsrepresent a status code. There are 26

possible status codes. When the status code is 0xF8, there is no

relevant information available and the SI bit is not set. All other 25

statuscodes correspond to defined I2C states. When any of these

states entered, the SI bit will be set.


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REF:- PAGE 154 DATASHEET


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I2C DATA REGISTER (I2DAT) This register contains the data to be Transmitted or

the data just received


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I2C SLAVE ADDRESS REGISTER (I2ADR I2C0ADR ) These registers are readable and writable, and is

only used when an I2C interface is set to slave

mode. In master mode, this register has no effect.

The LSB of I2ADR is the general call bit. When thisbit is set, the general call address (0x00) is

recognized


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I2C DUTY CYCLE REGISTER

USED TO SET THE CLOCK FREQUENCY

OF I2C BUS

I2SCLH,I2SCLL


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CONFIG: MASTER TRANSMITTER MODE

Data is transmitted to slave devicesMaster mode is entered by configuring

I2CCON

config the clock rate

Set I2EN ---- Enables the i2c hardware

DATA Transmission is started by setting start bit STA

Start condition is transmitted, next SI bit will be set and Status

register will be updated with 0x08h code.

Reset SI bit and load the I2CDAT register with slave Address+W .After transmitting again SI bit will be set ,read the Status

register(0x18, 0x20, or 0x38) based on the code do appropriate

action

after Repeated start the I2C block is entered in to receiver

mode by loading I2CDAT with SLA+R


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CONFIG: MASTER RECIEVER MODE


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CODE

Inter –integrated circuit (i2c)

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