JESD204B IP

Hardware Checkout Report

with AD9250

Revision 0.5

November 13, 2013

Altera JESD204B IP Hardware Checkout Report

Altera Corporation Page 1 of 14

Table of Contents

Revision History ........................................................................................................................................ 2

References ................................................................................................................................................ 2

1 Introduction .......................................................................................................................................... 3

2 Scope ..................................................................................................................................................... 3

3 Result Key .............................................................................................................................................. 3

4 Hardware Setup .................................................................................................................................... 3

5 Hardware Checkout Methodology ........................................................................................................ 4

5.1 Receiver Data Link Layer ............................................................................................................... 5

5.1.1 Code Group Synchronization ................................................................................................ 5

5.1.2 Initial Frame & Lane Synchronization ................................................................................... 5

5.2 Receiver Transport Layer .............................................................................................................. 7

5.3 Descrambling ................................................................................................................................ 8

5.4 Deterministic Latency for Subclass 1 ............................................................................................ 8

6 Operating Conditions .......................................................................................................................... 10

7 Test Results ......................................................................................................................................... 10

8 Comments on Test Results .................................................................................................................. 12

Appendix ..................................................................................................................................................... 13

Common Symbols for JESD204B ............................................................................................................. 13

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Revision History Rev Release date Description

1.0 Nov 29, 2013 Preliminary hardware checkout with AD9250

References Doc Rev

JEDEC Standard Serial Interface for Data Converters JESD204B.01 January 2012

AD9250 datasheet Rev A, March 2013

ADI AD9250 datasheet: http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9250/products/product.html

Altera JESD204B IP Hardware Checkout Report

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1 Introduction Altera JESD204B IP is hardware tested with a number of selected JESD204B compliant ADC (analog-to-digital converter) and DAC (digital-to-analog converter). The purpose of this document is to explain the Altera JESD204B IP hardware checkout methodology and publish the results with these selected converters.

2 Scope This document publishes the results of hardware checkout on JESD204B logical specification compliance of Altera JESD204B IP. Brief descriptions of the methodologies used are provided. More details regarding the hardware setup and Altera JESD204B IP can be found in application note AN-XXX (www.altera.com need a full link here). The JESD204B parameters shown in the results table are supported by the converters per the datasheet.

3 Result Key The following table contains possible results and their definitions:

Result Definition

PASS The Device Under Test (DUT) was observed to exhibit conformant behavior.

PASS with Comments

The DUT was observed to exhibit conformant behavior however an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed.

FAIL The DUT was observed to exhibit non-conformant behavior.

Warning The DUT was observed to exhibit behavior that is not recommended.

Refer to Comments

From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

Table 1: Result definitions

DUT is defined as Altera JESD204B IP and transport layer within the FPGA.

4 Hardware Setup The hardware needed for checkout is listed below:

Arria V GT FPGA Development Kit

o http://www/products/devkits/altera/kit-arria-v-gt.html

ADI AD9250 EVM (AD9250-FMC-250EBZ)

o http://www.analog.com/en/analog-to-digital-converters/ad-

converters/ad9250/products/EVAL-AD-FMCJESDADC1-EBZ/eb.html

19V power adapter that is included in Arria V GT FPGA Development Kit

Mini-USB cable

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Figure 1: Hardware Setup

The AD9250 EVM derives power from FPGA FMC connector. The EVM supplies clock to FPGA #2 and

AD9250. For subclass 1, FPGA generates SYSREF for the JESD204B IP as well as AD9250. Figure 2

shows a simplified block diagram of one of the test setup where data rate is 4.915Gbps, sampling

clock = 245.76MHz, subclass 1, L=2 and K=32. This test setup is modified from reference design in

AN-XXX.

jesd204b_ed_top.v

ADC

ADC

SPISlave

CLK & SYNC

3-wire

sync_n

ADC#2 clk (245.76MHz)

sysref_out

AD9250ADC#2

CPLD4-wire

Single-ended to differential distributionrx_dev_sync_n

AD9517Clock

generator

sysref

device_clk (122.88MHz)

3-wire or 4-wire

Design Example

jesd204b_ed.v

Sysref generator

JESD204B IP (duplex)L=2,M=2,F=2

L0

L1

Arria V FPGA #2 AD9250-FMC-250EBZ

ADC

ADC

SPISlave

CLK & SYNC

AD9250ADC#1

FMC

rx_serial_data[0] (4.915Gbps)

rx_serial_data[1] (4.915Gbps)

sclk, ss_n[0], miso, mosi

Oscillator100MHz

mgmt_clk

link_clk (122.88MHz)

ISSP

Qsys System

JTAG to Avalon Master Bridge

Avalon-MMInterface

signals

Avalon MM Slave

Translator

global_resetrx_seriallpbken

LEDx7

Signaltap II

Figure 2: Simplified block diagram of LMF=222 test setup

5 Hardware Checkout Methodology

device clock

transceiver lanes

sysref

sync_n

power

AD9250 EVM Arria V GT FPGA Development Kit

FPGA

#2

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5.1 Receiver Data Link Layer

5.1.1 Code Group Synchronization

On link start-up, the receiver issues a synchronization request and the transmitter emits comma

characters /K/= /K28.5/. Signaltap II is used to monitor the operation of receiver data link layer.

Test Case

Objective Description Passing Criteria

CGS.1 Check sync request is de-asserted after correct reception of four successive /K/ characters

The following signals in <ip_variant_name>_inst_phy.v are tapped:

i. jesd204_rx_pcs_data[(L*32)-1:0] ii. jesd204_rx_pcs_data_valid[L-1:0]

iii. jesd204_rx_pcs_kchar_data[(L*4)-1:0]

The following signals in <ip_variant_name>.v are tapped:

iv. rx_dev_sync_n v. jesd204_rx_int

L is the number of lanes. Signaltap sampling clock= rxframe_clk Each lane is represented by 32-bit data bus in jesd204_rx_pcs_data. The 32-bit data bus for is broken down to 4 octets.

/K/ character or K28.5 (0xBC) is observed at each octet of jesd204_rx_pcs_data bus. jesd204_rx_pcs_data_valid must be asserted to indicate data from PCS is valid. jesd204_rx_pcs_kchar_data is asserted whenever control characters like /K/, /R/, /Q/ or /A/ characters are observed. Rx_dev_sync_n is de-asserted after correct reception of at least four successive /K/ characters. Jesd204_rx_int is de-asserted if there is no error.

CGS.2 Check full code group synchronization at receiver after correct reception of another four 8B/10B characters

The following signals in <ip_variant_name>_inst_phy.v are tapped:

i. jesd204_rx_pcs_errdetect[(L*4)-1:0] ii. jesd204_rx_pcs_disperr[(L*4)-1:0]

The following signals in <ip_variant_name>.v are tapped:

iii. jesd204_rx_int L is the number of lanes. Signaltap sampling clock= rxframe_clk

jesd204_rx_pcs_errdetect, jesd204_rx_pcs_disperr and jesd204_rx_int should not be asserted during CGS phase.

Table 2: Test cases of Code Group Synchronization

5.1.2 Initial Frame & Lane Synchronization

Signaltap II and system console are used to monitor the operation of receiver data link layer.

Test Objective Description Passing Criteria

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Case

ILA.1

Check initial frame synchronization state machine enters FS_DATA state upon receiving non /K/ characters

The following signals in <ip_variant_name>_inst_phy.v are tapped:

i. jesd204_rx_pcs_data[(L*32)-1:0] ii. jesd204_rx_pcs_data_valid[L-1:0]

iii. jesd204_rx_pcs_kchar_data[(L*4)-1:0]

The following signals in <ip_variant_name>.v are tapped:

iv. rx_dev_sync_n v. jesd204_rx_int

L is the number of lanes. Signaltap sampling clock= rxframe_clk Each lane is represented by 32-bit data bus in jesd204_rx_pcs_data. The 32-bit data bus for is broken down to 4 octets.

Upon /R/ character or K28.0 (0x1C ) is observed at one octet of jesd204_rx_pcs_data bus. jesd204_rx_pcs_data_valid should be asserted. Jesd204_rx_int and rx_dev_sync_n should be de-asserted. Each multiframe in ILAS phase is ended with /A/ character or K28.3 (0x7C). jesd204_rx_pcs_kchar_data is asserted whenever control characters like /K/, /R/, /Q/ or /A/ characters are observed.

ILA.2

Check JESD204B configuration parameters from ADC in second multiframe

The following signals in <ip_variant_name>_inst_phy.v are tapped:

i. jesd204_rx_pcs_data[(L*32)-1:0] ii. jesd204_rx_pcs_data_valid[L-1:0]

The following signals in <ip_variant_name>.v are tapped:

iii. jesd204_rx_int L is the number of lanes. Signaltap sampling clock= rxframe_clk System console is used to access registers ilas_octet0, 1, 2 & 3.

/R/ character is followed by /Q/ character or K28.4 (0x9C) at the beginning of second multiframe. Jesd204_rx_int is de-asserted if there is no error. Octets 0-13 read from these registers tally with JESD204B parameters in each test setup.

ILA.3

Check lane alignment

The following signals in <ip_variant_name>_inst_phy.v are tapped:

i. jesd204_rx_pcs_data[(L*32)-1:0] ii. jesd204_rx_pcs_data_valid[L-1:0]

The following signals in <ip_variant_name>.v are tapped:

iii. rx_somf[3:0] iv. dev_lane_aligned v. jesd204_rx_int

L is the number of lanes. Signaltap sampling clock= rxframe_clk

dev_lane_aligned is asserted after the end of fourth multiframe in ILAS phase but before the first rx_somf is asserted. Rx_somf marks the start of multiframe in user data phase. Jesd204_rx_int is de-asserted if there is no error.

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Table 3: Test cases of Initial Frame & Lane Synchronization

5.2 Receiver Transport Layer To check the data integrity of payload data stream through RX JESD204B IP and transport layer, the

ADC is configured to output PRBS test data pattern and operates with the same JESD204B

configuration set in JESD204B IP. PRBS checker in FPGA fabric checks data integrity for 1 minute.

Figure 3 shows the conceptual test setup for data integrity checking.

RXJESD204B IP

PHY + Link Layer

RXTransport

Layer

PRBS Checker

TXJESD204B IP

PHY + Link Layer

FPGA

TXTransport

Layer

PRBS Generator

AD9250

Figure 3: Data integrity checking using PRBS checker

Signaltap II is used to monitor the operation of receiver transport layer.

Test Case

Objective Description Passing Criteria

TL.1 Check transport layer mapping

The following signals in altera_jesd204_transport_rx_top.v are tapped:

i. jesd204_rx_data_valid ii. jesd204_rx_link_data_valid

iii. jesd204_rx_link_error The following signals in jesd204b_ed.v are tapped:

iv. data_error[M-1:0] v. jesd204_rx_int

M is the number of converter. Signaltap sampling clock= rxframe_clk Data_error is the PRBS checker pass/fail indicator.

Jesd204_rx_data_valid and jesd204_rx_link_data_valid should be asserted. Data_error, jesd204_rx_link_error and jesd204_rx_int should be de-asserted.

Table 4: Test case for transport layer

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5.3 Descrambling Data integrity of descrambler can be checked using PRBS checker at RX transport layer. Signaltap II is

used to monitor the operation of descrambler.

Test Case

Objective Description Passing Criteria

SCR.1 Check descrambler functionality

Enable scrambler at ADC and descrambler at RX JESD204B IP. The signals tapped in this test case are same as in test case TL.1

Same as test case TL.1

Table 5: Test case for descrambler

5.4 Deterministic Latency for Subclass 1

This section describes how the deterministic latency was measured with AD9250. Figure 4 shows the

block diagram of deterministic latency test setup. A SYSREF generator is used to provide a periodic

SYSREF pulse for both AD9250 and JESD204B IP. This SYSREF generator is running in link clock domain

and the period of SYSREF pulse is configured to the desired multiframe size. The purpose of this SYSREF

pulse is to restart the LMF counter and re-align it to the LMFC boundary. Signaltap II uses link clock as

the sampling clock. For F=2, frame clock frequency is 2 times of link clock and they are synchronous to

each other. The clocking relationship is explained in AN-xxx.

jesd204b_ed_top.v

ADC

ADC

SPISlave

CLK & SYNC

3-wire

sync_n

ADC#2 clk (245.76MHz)

sysref_out

AD9250ADC#2

CPLD4-wire

Single-ended to differential distributionrx_dev_sync_n

AD9517Clock

generator

sysref

device_clk (122.88MHz)

3-wire or 4-wire

Design Example

jesd204b_ed.v

Sysref generator

JESD204B IP (duplex)L=2,M=2,F=2

L0

L1

Arria V FPGA #2 AD9250-FMC-250EBZ

ADC

ADC

SPISlave

CLK & SYNC

AD9250ADC#1

FMC

rx_serial_data[0] (4.915Gbps)

rx_serial_data[1] (4.915Gbps)

sclk, ss_n[0], miso, mosi

Oscillator100MHz

mgmt_clk

link_clk (122.88MHz)Signaltap II

Deterministic Latency

Measurement

global_rst_n

S11 USER2_PB0

user2_dipsw[0]

SW3

Figure 4: Deterministic latency test setup

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Deterministic latency check block is used to check deterministic measurement. The latency was checked

by measuring the number of link clock counts between start of de-assertion of SYNC~ to first user data

output as shown in Figure 5.

Figure 5: Deterministic Latency Measurement

With the setup above, four test cases were defined to prove deterministic latency. Please refer to Table

6 for deterministic latency’s test cases. Further, please take note the “LMFC offset” register was

configured to 0x8 and “SYSREF buffer” register was enabled on AD9250 for this deterministic

measurement.

The JESD204B configurations tested for deterministic latency measurement is defined in Table 8.

Test Case

Objectives Description Passing Criteria

DL.1 Check LMFC Alignment

Check FPGA and ADC aligned to desired LMF periods. Enabled always SYSREF detection. Observed via Signal Tap II on sysref_lmfc_err.

sysref_lmfc_err should not be triggered.

DL.2 Check SYSREF Capture

Check FPGA and ADC capture SYSREF correctly and restart the LMF counter. Repetitive reset both ADC and FPGA. Observed via SignalTap II on the csr_rbd_count’s value.

If the SYSREF is captured correctly and restart the LMF counter, the observed csr_rbd_count values should be the same for every reset.

DL.3 Check latency from start de-assertion of SYNC~ to first user data output

Check the latency is fixed for every FPGA reset. Repetitive reset the FPGA upon assertion of RX valid and recorded the number of link clocks count from start de-assertion of SYNC~ to first user data output. Repetitively compared the current test (n) recorded on the number of

Excellent repeatability of start de-assertion of SYNC~ to first user data output latency.

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link clocks from de-assertion of SYNC~ to first user data output with the previous test (n-1) recorded one.

DL.4 Check the data latency during user data phase

Check the data latency is fixed during user data phase

Observed via SignalTap II on the ramp pattern. The ramp pattern should be in perfect shape with no distortion.

Table 6: Test case for deterministic latency

6 Operating Conditions The JESD204B parameters L, M and F used in this hardware checkout are natively supported by AD9250 device quick configuration register at address 0x5E. The transceiver data rate, sampling clock frequency and other JESD204B parameters complied with AD9250 operating conditions.

JESD204B parameters: S = 1, CS = CF = 0, N’ = 16, N = 14; HD=0 for LMF=112, 124, 222 test cases; HD=1 for LMF=211 test case

K character replacement is enabled by default in converters

Data pattern = PRBS-9

FPGA clock: o device clock = 122.88MHz, management clock = 100MHz o frame clock = sampling clock, link clock = 122.88MHz

FPGA frame clock and link clock is derived device clock using internal PLL. The device clock is used to clock the transceiver.

7 Test Results Table 7 shows the results of test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1 an SCR.1 with various L, M, F, K, subclass, data rate, sampling clock, link clock and sysref frequencies. Test

Setup L M F

Sub-Class SCR K Data rate

(Mbps) Sampling Clock

(MHz) Link Clock

(MHz) Sysref (Mhz)

Result

1 1 1 2 0

0

16 4915 245.76 122.88 N/A PASS

2 32 PASS

3 1 16 PASS

4 32 PASS

5 1

0 16 15.36 PASS

6 32 7.68 PASS

7 1 16 15.36 PASS

8 32 7.68 PASS

9 1 2 4 0 0 16 122.88 N/A PASS

10 32 PASS

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11 1 16 PASS

12 32 PASS

13 1 0 16 7.68 PASS

14 32 3.84 PASS

15 1 16 7.68 PASS

16 32 3.84 PASS

17 2 1 1 0 0 20 2457 245.76 61.44 N/A PASS

18 32 PASS

19 1 20 PASS

20 32 PASS

21 1 0 20 12.288 PASS

22 32 7.68 PASS

23 1 20 12.288 PASS

24 32 7.68 PASS

25 2 2 2 0 0 16 4915 122.88 N/A PASS

26 32 PASS

27 1 16 PASS

28 32 PASS

29 1 0 16 15.36 PASS

30 32 7.68 PASS

31 1 16 15.36 PASS

32 32 7.68 PASS

Table 7: AD9250 hardware checkout results of receiver data link layer, transport layer and descrambler

Note: N/A means not applicable.

Table 8 shows the deterministic latency measurement.

Test Case

L M F

Sub-Class K Data rate (Mbps)

Sampling Clock (MHz)

Link Clock (MHz)

Sysref (Mhz)

Result

DL.3 2 2 2 1 32 4915 245.76 122.88 7.68 131-132 link clocks

Table 8: Deterministic latency measurement

Figure 6 shows the Signaltap II waveform of the clock count from the de-assertion of SYNC~ the first

output of ramp test pattern. The clock count is used to measure the first user data output latency. No

distorted ramp pattern is observed.

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Figure 6 : Ramp pattern observed on deterministic latency measurement

8 Comments on Test Results In each test case, the RX JESD204B IP initializes successfully from code group synchronization (CGS)

phase, initial lane alignment (ILA) phase until user data phase. No data integrity issue is being observed

from PRSB checker. For LMF=211 test case, the data rate is reduced to 2457Mbps to constraint frame

clock within frequency range acceptable for timing closure. Table 3 explains the timing closure

challenges of in both scenarios with different data rates:

Item Scenario 1 Scenario 2 Remark

Data Rate 4915 Mbps 2457 Mbps Data rate within AD9250 operating condition

Link Clock = data rate/40 122.88 MHz 61.44 MHz Link clock frequency is determined by data rate

Frame Clock = 4 x link clock and must be ≤ ADC maximum sampling rate

491.52MHz 245.76MHz Frame clock frequency in scenario 1 is too challenging for timing closure and is beyond the operating condition of AD9250

Table 3: Timing closure challenge with LMF=211 test case

The 1 link clock variation in deterministic latency measurement is caused by word alignment where

control characters fall into the next cycle of data sometimes after realigned. This makes the ILAS phase’s

duration is longer by 1 link clock sometimes after reset.

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Appendix

Common Symbols for JESD204B SYMBOLS DESCRIPTION

L Number of lanes per converter device

M Number of converters per converter device

F Number of octets per frame

S Number of transmitted samples per converter per frame

N Number of conversion bits per converter

N’ Number of transmitted bits per sample (JESD204 Word Size)

CS Number of control bits per conversion sample

CF Number of control words per frame clock period per link

HD High Density user data format

K Number of frames per multi-frame

LMFC Local Multi-frame Clock

FC Frame clock rate