Intel and SAP History of Co-Innovation Timeline

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Intel and SAP Co-Innovation Timeline 1997 Intel and SAP jointly establish an e-commerce company Pandesic LLC 2002 Intel and Microsoft collaborate early on with SAP to find solutions. 2009 Intel and SAP co-invent a new, ultra-fast, in-memory table scan using on-chip vector processing units. 2010 SAP HANA is officially launched with Intel as the reference architecture. 2013 SAP HANA Enterprise Cloud launches running on Intel ® Xeon ® processor E7 based servers. 2015 Co-Founder of SAP SE Hasso Plattner explains the impact of Intel Haswell’s processor on SAP HANA 2017 World’s first public demo on Intel® Optanepersistent memory with SAP HANA. 2019 Intel launches 2 nd Generation Intel Xeon Scalable processors and Intel® OptanePMem for data-centric innovation. Today and beyond Collaboration on next gen technology – in memory computing, IOT, AI/ML and cloud Over 30,000 Customers have benefited from these joint blueprints and reference architectures

Transcript of Intel and SAP History of Co-Innovation Timeline

Page 1: Intel and SAP History of Co-Innovation Timeline

Intel and SAP Co-Innovation Timeline

1997Intel and SAP jointly establish an e-commerce company Pandesic LLC

2002Intel and Microsoft collaborate early on with SAP to find solutions.

2009Intel and SAP co-invent a new, ultra-fast, in-memory table scanusing on-chip vector processing units.

2010SAP HANA is officially launched with Intel as the reference architecture.

2013SAP HANA Enterprise Cloudlaunches running on Intel® Xeon®processor E7 based servers.

2015Co-Founder of SAP SE HassoPlattner explains the impact of Intel Haswell’s processor on SAP HANA

2017World’s first public demo on Intel® Optane™ persistent memory with SAP HANA.

2019Intel launches 2nd Generation Intel Xeon Scalable processors and Intel® Optane™ PMem for data-centric innovation.

Today and beyondCollaboration on next gen technology – in memory computing, IOT, AI/ML and cloud

Over 30,000 Customers have benefited from these joint blueprints and reference architectures