Document Number: 332691-002EN

Intel 100 Series and Intel C230 Series Chipset Family Platform Controller Hub (PCH)Datasheet - Volume 2 of 2

Supporting S and H Platform Register Information

July 2017

2 Datasheet, Volume 2 of 2

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Datasheet, Volume 2 of 2 3

Contents

1 LPC Interface (D31:F0)............................................................................................631.1 LPC Configuration Registers Summary..................................................................63

1.1.1 Identifiers (ID)Offset 0h .......................................................................631.1.2 Device Command (CMD)Offset 4h ..........................................................641.1.3 Status (STS)Offset 6h ..........................................................................651.1.4 Revision ID (RID)Offset 8h....................................................................661.1.5 Class Code (CC)Offset 9h......................................................................661.1.6 Header Type (HTYPE)Offset Eh ..............................................................671.1.7 Sub System Identifiers (SS)Offset 2Ch ...................................................671.1.8 Capability List Pointer (CAPP)Offset 34h..................................................681.1.9 Serial IRQ Control (SCNT)Offset 64h ......................................................681.1.10 I/O Decode Ranges (IOD)Offset 80h.......................................................691.1.11 I/O Enables (IOE)Offset 82h .................................................................701.1.12 LPC Generic I/O Range #1 (LGIR1)Offset 84h..........................................711.1.13 LPC Generic I/O Range #2 (LGIR2)Offset 88h..........................................721.1.14 LPC Generic I/O Range #3 (LGIR3)Offset 8Ch .........................................721.1.15 LPC Generic I/O Range #4 (LGIR4)Offset 90h..........................................721.1.16 USB Legacy Keyboard/Mouse Control (ULKMC)Offset 94h..........................721.1.17 LPC Generic Memory Range (LGMR)Offset 98h.........................................741.1.18 FWH ID Select #1 (FS1)Offset D0h ........................................................741.1.19 FWH ID Select #2 (FS2)Offset D4h ........................................................751.1.20 BIOS Decode Enable (BDE)Offset D8h ....................................................761.1.21 BIOS Control (BC)Offset DCh ................................................................781.1.22 PCI Clock Control (PCCTL)Offset E0h ......................................................79

1.2 LPC PCR Registers Summary...............................................................................811.2.1 General Control & Function Disable (GCFD)Offset 3418h ...........................81

2 Enhanced SPI Interface (D31:F0) ............................................................................832.1 Enhanced SPI (eSPI) PCI Configuration Registers Summary ....................................83

2.1.1 Identifiers (ESPI_DID_VID)Offset 0h ......................................................832.1.2 Device Status and Command (ESPI_STS_CMD)Offset 4h...........................842.1.3 Class Code and Revision ID (ESPI_CC_RID)Offset 8h................................862.1.4 BIST, Header Type, Primary Latency Timer, Cache Line Size

(ESPI_BIST_HTYPE_PLT_CLS)Offset Ch ..................................................862.1.5 Sub System Identifiers (ESPI_SS)Offset 2Ch ...........................................872.1.6 Capability List Pointer (ESPI_CAPP)Offset 34h .........................................872.1.7 I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE)Offset 80h ................882.1.8 eSPI Generic I/O Range #1 (ESPI_LGIR1)Offset 84h ................................902.1.9 eSPI Generic I/O Range #2 (ESPI_LGIR2)Offset 88h ................................912.1.10 eSPI Generic I/O Range #3 (ESPI_LGIR3)Offset 8Ch ................................922.1.11 eSPI Generic I/O Range #4 (ESPI_LGIR4)Offset 90h ................................932.1.12 USB Legacy Keyboard/Mouse Control (ESPI_ULKMC)Offset 94h .................942.1.13 eSPI Generic Memory Range (ESPI_LGMR)Offset 98h ...............................962.1.14 FWH ID Select #1 (ESPI_FS1)Offset D0h ................................................962.1.15 FWH ID Select #2 (ESPI_FS2)Offset D4h ................................................972.1.16 BIOS Decode Enable (ESPI_BDE)Offset D8h ............................................982.1.17 BIOS Control (ESPI_BC)Offset DCh ...................................................... 100

2.2 eSPI PCR Registers Summary ........................................................................... 1022.2.1 eSPI Slave Configuration and Link Control

(SLV_CFG_REG_CTL)Offset 4000h ....................................................... 102

4 Datasheet, Volume 2 of 2

2.2.2 eSPI Slave Configuration Register Data (SLV_CFG_REG_DATA)Offset 4004h .....................................................104

2.2.3 Peripheral Channel Error for Slave 0 (PCERR_SLV0)Offset 4020h..............1052.2.4 Virtual Wire Channel Error for Channel 0 (VWERR_SLV0)Offset 4030h.......1082.2.5 Flash Access Channel Error for Slave 0 (FCERR_SLV0)Offset 4040h ..........1112.2.6 Link Error for Slave 0 (LNKERR_SL0)Offset 4050h ..................................113

3 P2SB Bridge (D31:F1) ............................................................................................1163.1 P2SB Configuration Registers Summary ..............................................................116

3.1.1 PCI Identifier (PCIID)Offset 0h.............................................................1173.1.2 PCI Command (PCICMD)Offset 4h ........................................................1173.1.3 Revision ID (PCIRID)Offset 8h .............................................................1183.1.4 Class Code (PCICC)Offset 9h ...............................................................1193.1.5 PCI Header Type (PCIHTYPE)Offset Eh ..................................................1193.1.6 Sideband Register Access BAR (SBREG_BAR)Offset 10h ..........................1203.1.7 Sideband Register BAR High DWORD (SBREG_BARH)Offset 14h ...............1203.1.8 PCI Subsystem Identifiers (PCIHSS)Offset 2Ch.......................................1213.1.9 VLW Bus:Device:Function (VBDF)Offset 50h ..........................................1213.1.10 ERROR Bus:Device:Function (EBDF)Offset 52h.......................................1223.1.11 Routing Configuration (RCFG)Offset 54h................................................1223.1.12 High Performance Event Timer Configuration (HPTC)Offset 60h ................1233.1.13 IOxAPIC Configuration (IOAC)Offset 64h ...............................................1243.1.14 IOxAPIC Bus:Device:Function (IBDF)Offset 6Ch .....................................1243.1.15 HPET Bus:Device:Function (HBDF)Offset 70h .........................................1253.1.16 Sideband Register posted 0 (SBREGPOSTED0)Offset 80h.........................1263.1.17 Sideband Register posted 1 (SBREGPOSTED1)Offset 84h.........................1263.1.18 Sideband Register posted 2 (SBREGPOSTED2)Offset 88h.........................1273.1.19 Sideband Register posted 3 (SBREGPOSTED3)Offset 8Ch ........................1273.1.20 Sideband Register posted 4 (SBREGPOSTED4)Offset 90h.........................1283.1.21 Sideband Register posted 5 (SBREGPOSTED5)Offset 94h.........................1283.1.22 Sideband Register posted 6 (SBREGPOSTED6)Offset 98h.........................1293.1.23 Sideband Register posted 7 (SBREGPOSTED7)Offset 9Ch ........................1293.1.24 Display Bus:Device:Function (DISPBDF)Offset A0h .................................