Integration/Reliability Issues for Cu/low-k BEOL Interconnects

© 2007 IBM Corporation

IEEE Workshop on Microelectronics and Electron Devices, April 3, 2009, Boise

Integration/Reliability Issues for Cu/low-k BEOL Interconnects

Daniel C. EdelsteinIBM Fellow and Manager, BEOL Technology StrategyIBM T. J. Watson Research Center, Yorktown Hts., New [email protected]

2 D. Edelstein, April 3, 2009 © 2007 IBM Corporation

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Outline

From an integration perspective, discuss scaling impacts on reliability of:

Metals

Insulators

Chip-Package Interaction (CPI)

Summarize for each– key issues, proposed solutions, key metrics, analytical techniques


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Via/line interface

Liner-seed and Cu fill

Cu electromigration

Cap reliability

Dielectric-Cap adhesion

Dielectric reliability

Outline

Vacuum (“Air-”) Gaps

90 nm45 nm

Technology Map

Underfill

Chip-Package

Crackstop


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SummaryMetals

– Issues: Cu gapfill, Cu grain growth, electromigration scaling, new materials in liner/seed– Proposed solutions: Noble-like metal in liner, selective metal cap, Cu-alloy seed– Critical Metrics: Via yields, Cu resistivity, defectivity, electromigration, stressmigration– Analytical: Cu/barrier interfacial diffusivity and Ea, Cu grainsize, metal interdiffusions, galvanic

potentials, TEM/EELS, tomography, other microprobes

Insulators– Issues: Low-k mechanical and dielectric strengths, process damage, damascene pattern integrity– Proposed solutions: Incremental k reduction, re-optimization of film properties, modify skeleton– Critical metrics: Patterning, wire C, I-V, Vbr, TDDB, tensile stress, modulus, chip-package reliability– Analytical: Electrical, mech. modeling, modulus/hardness, adhesion, fracture toughness, pore size,

porosity, plasma-induced damage

Chip-Package– Issues: TCE mismatches, tensile low-k, weak low-k and pkg. polymers, larger chips, Pb-free C4’s– Proposed solutions: Tough crackstop, maximized low-k strength and adhesion, “ideal” underfills,

chip-join thermal budgets, reduced-TCE laminates (cores), compliant leads, Si Carrier– Critical metrics: Deep thermal cycle reliability, T/H/B, etc., underfill toughness and fatigue– Analytical: Sonoscan, failure analyses techniques, polymer Kc and fatigue


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Acknowledgements

This work was done by countless colleagues from IBM and our R&D Alliance partners, at:– T. J. Watson Research Center, Yorktown Hts., NY

– Nanotechnology Center, Albany, NY

– Semiconductor and Packaging R&D Centers, E. Fishkill, NY


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Data Section


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Impact of Electron Scattering in Nanoscale Cu WiresExtracted Cu Resistivity vs. Wire Cross-Sectional Area

L. Gignac, AMC 2007

• Cu resistivity increases as Cu wire area decreases.• Cu grain size does not influence ρ greatly when grain size > electron mean free path.• In the above case, surface scattering is the major factor.• TCR method in literature overestimates ρ.

ITRS65 nm nodeρ~2.5 µΩcm

1.5x103 104 105

2.0x10-6

2.2x10-6

2.4x10-6

2.6x10-6

2.8x10-6

3.0x10-6

3.2x10-6

3.4x10-6

3.6x10-6

3-4 TEMs per datapoint

Data fit to:ρ= ρo (1+Cλ/A)

ρo = 2.01 ± 0.02 E-6 Ω-cm

C = 580 ± 45 Ωcm. nmλ = 3 nm

M1

Cu

ρ( Ω

-cm

)

Line Area ( nm2 )

LRACu=ρ

Able to predict ρ for future technology nodes



a)

b)

c)


IEEE WMEDExtendibility Problem: Electromigration Lifetime Reduction Scaling in Cu Damascene Lines

– Top Cu/cap interface dominates E-M diffusion for bamboo lines– Scaling trend is predictable by geometry, with no adjustable parameters– Lifetime drops as dimension shrinks – now dropping at 50%/generation– At the same time, chip current density requirements scale up– Cu lines at 45 nm node and beyond have reduced bamboo grains – further impact

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.01

0.1

1

Theory

t 50/t 50

(1.3

x0.9

)

∆Lcrxh (µm2)

e

Blocking material

liner Void Cu h

C-K. Hu, IRPS 2004 and IITC 200716 17 18 19

10 1

10 2

10 3 W f B w (µm ) Q E M(eV ) 1 .9 0 .93 0 .7 0 .96 0 .14 0 .95 0 .09 0 .84

t 50 (h

)1 /T (10 -4K -1)

Interfacial diffusion

Interfacial diffusion Ta

gb diffusion

SiCNH

surfa

ce

Void

Marker Velocity

Grain-boundary diffusion degrades Cu electromigration reliability in nanowires

Cu linewidth, grain size


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Bamboo (Cu grainsize solved) Non-Bamboo (Cu grains not solved)

Approaches to Recover Cu Electromigration Reliability vs. Scaling

Selective Metal Cap(Shut down top-surface Cu diffusivity)

e.g. electroless CoWPimpacts: leakage, TDDB,

manufacturability

Flash noble liner layer on TaN/Ta(Increase Cu grain growth?)

e.g. PVD (Ta)Ru, CVD-Ru or –Coimpacts: reduced Cu volume %, galvanic

corrosion potential, CMP difficulties

Doped Cu seed(Stuff small Cu grain boundaries)

e.g. Cu(Al)impacts: Cu resistivity, linewidth-dependence,

dilute alloy control in mfg.


IEEE WMEDOne Solution to Cu Electromigration Scaling Problem: Selective Metal Caps

For “bamboo” lines:• Selective top metal cap can eliminate EM issue completely• Activation energy can reach to bulk Cu values• Current densities are then limited to much higher values by rms joule heating

For small-grained lines:• Grain boundary diffusion may still dominate electromigration lifetimes

Challenges:• Remedy insufficient Cu recrystallization or Cu grain boundary diffusion (e.g. by alloy)• Achieve manufacturable selective metal capping process with a uniform ~few nm cap, and no impact to shorts yield, line-line leakage, or dielectric breakdown reliability

C-K. Hu, IRPS 2004

example: electroless CoWP


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Selective CVD-Ru Metal Cap

Sele

ctiv

ity

Blanket Deposition Rates

Microanalysis

Test Chips

Performance

Opens and Shorts Yields

TDDB Reliability

Electromigration Reliability

C-C. Yang, et al. submitted to IITC 2009


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Another Approach - Cu-Alloy Seedlayer for E-M Enhancement

Pileup of Al dopant at Cu/cap interface reduces fast-path Cu E-M

S. Yokogawa, et al., IEEE IRPS 2007

Electromigration

Cu Resistivity

• Adding certain dopants to the Cu seedlayer can enhance E-M reliability…but at the expense of Cu resistivity…and linewidth-dependence…and other potential mfg. control issues

• Need to determine best dopant and its % in Cu for optimal R vs. E-M.Numerous candidates studied over the years, most rejectedAluminum has emerged as a good candidate

• Several companies have adopted Cu(≤ 1 at.% Al) in production since 65/45 nm


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Cu Metallization Gapfill Extendibility Problem

Via yield and reliability are based on liner/seed/plating process window…

…that is determined by Cu seed process window, comprised of:

• Reactive Ion Etch (RIE) patterning

• Liner pinch-off above, and continuity below

• Seed pinch-off above, and continuity below

• Plating (seed etching and superfill rates)


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Extendibility of Cu Damascene Metallization: Add Noble Metal to Ta-Based Barrier

Retain ECD-Cu gapfill process window and Cu reliability with minimal integration disruptionRetain high-integrity PVD-Cu/barrier interface for electromigration (e.g. Ta/Cu, not Ta2O5/Cu)Increase thin Cu seed wettability and continuity in small, high a.r. featuresProvide good plating nucleation inside Cu-seed discontinuitiesMinimal impacts to plating (terminal effect), CMP, Cu fill volume (Cu line resistance)New concerns for galvanic corrosion, Cu/barrier adhesion and electromigration

PVD-TaNPVD-TaPVD Ta(Ru) or CVD-Ru

PVD-CuECD-Cu

TaN/Ta TaN/Ta0.3Ru0.7 TaN/Ta0.1Ru0.9

TaN/Ta TaN/Ta0.1Ru0.9 TaN/Ta/Ru

PVD

PVD/CVDPVDPVD

PVDPVD

BEOL: Yang et al., IITC 2006Cu contacts: Seo et al., AMC 2008

BEOL: Nogami et al., AMC 2008


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12

5

10

20

3040506070

80

90

95

9899

Cum

ulat

ive

Failu

re P

roba

bilit

y(%

)

Lifetime (au)

T = 300oC, I = 0.10 mA

V1 to M2

TaN/TaTaN/TaRu90%

TaN/Ta

TaN/TaRu90%

Cu Electromigration Performance with TaN/TaRu Barrier

More than 3X longer lifetimesRecovered normal reliability by fixing defective Cu gapfill


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Testing New Barrier Properties

TaRu90%

TaRuN90%

TaRuN70%

TaRu70%

Ta TaN

PVD TaRu(N) films do not fully block Cu+ or O2 diffusion.PVD TaN and/or Ta is required underneath TaRu.

Ta, TaN >> TaRu70% > TaRuN70% > TaRu90% > TaRuN90%

Cu+ Barrier Test(Triangular Voltage Sweep, 300C, 1 MV/cm

TaRuN90%/TaRu90%

No Cu oxidation

Cu is oxidized Cu is oxidized

TaRuN70%/TaRu70%

TaN/TaTaN/TaRu90%

No Cu oxidation

Oxidation Barrier Test(310C/8 days in air)

TaN/Ta = TaN/TaRu90% >> TaRuN/TaRu


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Extendibility of the Most Reliable Via/Line Contacts

max stress

low stress

stress gradient

max stress

low stress

stress gradient

max stress

low stress

stress gradient

max stress

low stress

stress gradient

max stress

low stress

stress gradient

A. Fischer, et al., IEEE IRPS (2007).

1 10 100 1000

Stress Failure Time (hrs.)

99.9

99959075502510

51

0.10.01

perc

entil

e

V2 -> M2; T50 = 215.3 hrs. σ = 0.1463

Cu is 500 X better than Al(Cu) at 300C

D. Edelstein, et al., IEEE IRPS (2004).

90 nm CMOS 45 nm CMOS65 nm CMOS ULK with new process

ULK with old process

C-C. Yang, et al., AMC (2008).


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Advanced Dielectrics Roadmap: current IBM status

Leading development and implementation of industry’s most advanced low-k and ultralow-k PECVD dielectrics

Technology nodes

AvailabilityImplementation

90nm 45nm65nm 32nm 22nmSiCOH k=3.0

pSiCOH k=2.4

15nm

SiCOH k=2.7

pSiCOH k=2.2

pSiCOH k=2.0

PECVD Films

A. Grill, AMC 2007 and MRS 2009


IEEE WMEDLow-k and Ultralow-k Time-Dependent Dielectric Breakdown (TDDB)

• Low-k obeys root-E kinetics at least, and may be more robust• Cu reduces lifetimes and plays an important role• Moisture is bad• Line-edge roughness affects lifetimes J. Lloyd, AMC 2008


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channel crackingcohesive vs. adhesive failure

delamination

chip packaging interactionBEOL film fabrication

G: energy release rate G: fracture strengthstructure and geometryfilm stressthermal expansion and modulus

chemical bondinginteraction with environment

Methodology of Fracture Mechanicsexcerpts from X-H. Liu, MRS 2009 invited talk

ΓG <

X.H. Liu et al, IITC (2004) AMC (2004)Issue: Low-k C-doped SiOx glass films, the industry de facto standard, are unfortunately always tensile-stressed and have relatively low moduli and fracture toughnesses


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Strengthening Low-k and Ultralow-k SiCOH Interfacial RegionHistorically, chronically low SiCOH adhesion results

Typical pretreatments did not improve

Discovered weak nucleation layer at interface

Solution became clear – graded nucleation

Dramatic adhesion improvement, approaching

~bulk cohesive strength

Extendible to ultralow-k porous SiCOH (not trivial)

Identifiable by TOF-SIMS profiles of thin samples

Adhesion StrengthControl - no optimization

G = 2.1 J/m2

With optimization

G = 5.0 J/m2

A. Grill et al., MRS Spring 2007.D. Restaino et al., AMC 2007.S. Molis et al., SIMS Workshop 2007.

Si

Bulk SiCOH

SiCHN “adhesion layer”

Low-k Insulators

3.53.52.7-3.42.0k=2.4

4.54.1n/a2.0k=2.7

6.05.03.0-4.02.0k=3.0

Cohesive Strength (J/m2)

Optimized Transition (J/m2)

Substrate Treatment (J/m2)

Bulk-only SiCOH (J/m2)

SiCOH Version


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Effect of Multilevel MetallizationX-H. Liu, MRS 2009 invited talk

0 5 10 15 200.0

0.5

1.0

1.5

2.0

Ene

rgy

Rel

ease

Rat

e N

orm

aliz

ed

Gap Width Normalized

thin wires

channel crack propagation

crack arrest on cap

fat wires

substrate

Single metal level

Multiple metal levels

Large enhancements in G possible with patterned metal under layers

J.M. Ambrico, E.E. Jones, and M.R. Begley, (2002) Int. J. Solids and Struct, 39, pp.1443


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•Cap layer acts like a springholding the metal pads together.•Strength of spring is proportional to the cap thickness X Cap Modulus

Effects of CapsX-H. Liu, MRS 2009 invited talk

Cap stiffness is important to prevent cracking.

0 2 4 6 8 1025

30

35

40

45

50

Gm

ax/G

0

varying modulus varying thickness

Modulus x Thickness (kNm)


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Spontaneous Cracking X-H. Liu, MRS 2009 invited talk

Spontaneous cracking observed in structures with a narrow gap. Tunneling cracks may form in the SiCN cap dielectric. Si SiO2

4 levels in SiCOH

4 Levels in pSiCOH


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Finite Element Modeling of ULK Films in BEOL StructuresTo optimize ULK mechanical properties and wiring groundrule limits, and compute maximum strain energy release rate before channel cracking

Energy release rate (crack driving force) increases with # levels in stackMost sensitive to (tensile) stress, somewhat sensitive to modulus

‚ Reduce ULK film stress and increase modulus to avoid cracking

X.Liu et al., ASME 200612

34

56

10

20

3040

5060

0

1

2

3

4

5

6

7

8

9

10

11

Film Stress Normalized

Ener

gy R

elea

se R

ate

Nor

mal

ized

Modulus Normalized

EB

B2

M31X

2X

4X

G=A σ2 h/E

Safe

Channel Cracking

Cohesive StrengthOf Dielectric

TE∆∆

−+= α

υσσ

1int


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Fundamental SiCOH Toughness

Goal: Exceed universal curve for tougher PECVD ULK pSiCOHReduce sensitivity to plasma-induced damage

Approach: Improve molecular skeleton with Si-C-Si bonding……but don’t go too far!

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0Nominal Dielectric Constant, k

0.0

4.0

8.0

12.0

Coh

esiv

e St

reng

th, Γ

(J/m

2 )Universal curve determined by Si-O bond density

Current(O)SG Universal Trend


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DEMS

BCHD

SkeletonPrecursor 2

PECVD

300 mmProduction tool

UV cure

300 mmProduction tool

Ultralow-k Porous SiCOH Extendibility:Increase Cohesive Strength and Reduce Resistance to Plasma Damage

Skeleton 1: DEMS (diethoxymethylsiloxane), strong Si-O x-linking, efficient porogen incorp.Porogen: BCHD (bicycloheptadiene) incorporates very efficiently, widely tunable k.Skeleton 2: (proprietary), adds Si-CH2-Si bonding for smaller pores, reduced plasma damage, increased toughness.

k 2.4 pore size distributions from EP

0

2

4

6

8

10

12

1 1.5 2 2.5 3 3.5 4 4.5 5Pore diameter (nm)

dV/d

(ln R

)

V1.0 Film 2

Property V1 V2 V1 V2

Modulus [Gpa] 4.5 3.8 2.7 2.3

Stress [Mpa] 47 51 38 40

Interface strength [J/m2] 4.0 4.0 3.5 4.0

Porosity (%) 30 29 37 33

k 2.4 k 2.2

S. Gates, et al., AMC (2008).


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Effects of adding Si-C-Si bonding to Si-O-Si matrixLess pore connectivity, more Si-C bonds to break for damage less plasma-induced damage

Average line width reducedTrench bottoms improvedLeakage current reducedNet reduction in line capacitance for same k of film

K 2.2, V1

K 2.2, V2

K 2.2, V2Advanced Porous SiCOH, K=2.2, at 32 nm Node 1x Dimensions

S. Gates, et al., AMC (2008).


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Advanced Bilayer Low-k Cap Film

Passes O2 Barrier test

Cu

Adv. SiCNy

SiCNx

0 0.5 1 1.5 2 2.5 3 3.5 4 4.50

10

20

30

40

50

60

70

80

90

100

Sputter Time (min)

Rel

ativ

e C

once

ntra

tion

(%)

N1.ls1C1.ls1

Si2.ls1

O1.ls1

Cu1.ls1Air barrier properties confirmed

G. Bonilla, et al., AMC (2008).

10 100 100012

5

10

20304050607080

90

95

98 302oC

Cum

ulat

ive

Failu

re P

roba

bilit

y (%

)

τ (h)

256oC331oC 218oC

SiCNxLow-k Adv barrier

350oC

Passes E-M, S-M, and TDDB tests

-5%

Achieves required keff reduction


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Multilevel Airgap Wiring Demonstration on Advanced 65 nm Production Microprocessor

Airgap process schemes applied to all Cu wiring levels above M1.Lithographic slots on larger (2x and above) levelsSelf-assembly sublithographic patterning for minimum (1x) levels

No changes to standard Cu wiring process flow, fab tooling, or materials.Yield, performance, reliability, and modeling predictions demonstrated.

8x

4x

2x

8x

4x

2x1x

1x

Airgap Technology


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Capacitance modeling– C reduction can be optimized to -40%

CPU tuned performance estimates – ~10% Fmax, ~15% active pwr



Mechanical modeling – Gap calculations find low cracking risk




Thermal modeling sets current limits – very small gap impact is calculated





Electromigration– good preliminary results






Time-dependent dielectric breakdown– good preliminary results

1.00E-3 1.000.01 0.10 1.00 10.00 100.00 1000.00 10000.00 100000.001000000.001.00

5.00

10.00

50.00

90.00

99.00

Time [hrs]C

DF

(%)

Ungapped (Green)

Gapped (Red)






Time-dependent dielectric breakdown– good preliminary results

Chip-package reliability stressing– no issues in preliminary tests

We have seen some good preliminary indicators for manufacturabilityNeed more extensive data, models, process windows for qualification

Comprehensive Airgap Performance/Reliability Assessment

Sonoscan after 1000 deep thermal cycles shows no fails


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1. Corner Underfill Delam./Crack 2. C4/BEOL Delam.

3. BEOL Edge Delam. 4. Chip Fracture


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1. Corner Underfill Delam/Crack 2. C4/BEOL Delam.

3. Edge BEOL Delamination Chip Fracture

– Worst for ultra-large chips on organic laminates– Increases with chip-size– Cracks circumvent chip crackstop– Fatal, independent of BEOL materials– Limitations on available underfills, laminates– Mitigation strategies required

– Chip-size, dicing, and BEOL low-k, ULK dependent– Solved by tough crackstop and optimized dicing– Crackstop toughness >> ULK, Si, SiO2, etc.– Low-k and ULK optimized for adhesion/cohesion

– Flat vs. chip size above ~0.5 cm– Worse for Pb-free C4– Can fail at weakest BEOL interface– Mitigation strategies required

– Primarily when chips are thinned– Dicing and handling defects + stress– Increases with chip size– Fatal, independent of BEOL materials– Mitigation strategies required


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Crackstop Problem OverviewX-H. Liu, MRS 2009 invited talk

Si

G, Γ

Interfacial adhesion (limited by ILD cohesive strength)

Crackstop toughness

position

Energy of dicing cracks during dicing process

Maximum energy of delamination during DTC

Si toughness

(After Robert Cook 1994)


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molding compound

Silicon substrate

oxide

ILD

Method to Improve Crackstop ToughnessX-H. Liu, MRS 2009 invited talk

fibre toughening


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Measurement of Crackstop Effective Toughness

Produce chip with large areas of crackstop structure

Mask designs includes multiple isolated crackstop designs

4 point bend test gives toughness of individual designs

Load for failure of crack stop used to determine optimum design

0 1000 2000 30000

2

4

6

Load

(lbs

)

Time (Secs)

8-10 J/m2

4 J/m2

Delamination traveling

In the unreinforced area

Delamination hits

Crack stops

Delamination pinned

at loading points

Delamination

initiates

Load Displacement for Multilevel ULK Build

T. Shaw et al., IITC 2007

Notch position

Crackstops

Isolated widths of crackstop structure

4-pt. bend load cell

Fracture Energy Calculation:

32

222

16)1(21hEb

LPG cν−=


IEEE WMEDSolving Cu/Low-k and Ultralow-k Chip-Package Interaction (CPI) Reliabilityexample: 45 nm CMOS with low-k and ultralow-k wiring levels

Fundamental mechanical solutions enable ULK (k=2.4) to pass comprehensive CPI:Extensive finite-element modelingOptimized dicingImproved crackstop toughness Improved ULK adhesion S. Sankaran et.al., IEEE IEDM (2006).

C4

Si

BEOL

Delaminationsobserved

No Delaminationsobserved after dicing optimization

Delaminationsobserved

No Delaminationsobserved after dicing optimization

0 CPI fails after 1000 cycles of -55/+125C

EPBGAWirebond

0 fails after 1800 cycles of -40/+125C stress.

FCPBGA


MLC-LGAFlip chip

Deep thermal cycle stress

PackagingTest chip

0 CPI fails after 1000 cycles of -55/+125C

EPBGAWirebond


FCPBGA


MLC-LGAFlip chip

Deep thermal cycle stress

PackagingTest chip

SiMold

MoldOxide

SiSiCOH

BPSG

X25 Crackstop Toughness

Interface CS1 CS20

1

2

3

4

5

6

7

8

9

10

Rel

ativ

e To

ughn

ess


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Crack dives into BEOL structuredamage found on multiple layers

Examples of Chip-Corner/Underfill Fail Mode

Modeling is well understood for corner stresses, but not underfill fatigue

Integration/Reliability Issues for Cu/low-k BEOL Interconnects

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