Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel...

68
Lecture 5 CMOS Fabrication Process Prof. José Luís Güntzel [email protected] Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering

Transcript of Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel...

Page 1: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

Lecture 5 CMOS Fabrication Process

Prof. José Luís Güntzel [email protected]

Integrated Circuits & Systems INE 5442

Federal University of Santa Catarina Center for Technology

Computer Science & Electronics Engineering

Page 2: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.2

The Silicon Atom

• Grande estabilidade física e química em temperatura • 4 elétrons na órbita externa: valência 4 • permite uma obtenção “natural” do SiO2 - óxido de silício

Source: R. Reis 1999

Page 3: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.3

Silicon Crystal Monocristal: Silício Monocristalino •  estrutura regular e homogênea •  ligações covalentes • material quimicamente estável Em estado puro (intrínsico): • mau condutor a temperatura ambiente •  isolante a baixas temperaturas Aumento da temperatura: •  provoca quebra das ligações •  um elétron livre provoca a formação de uma

lacuna •  ocorre a geração de pares elétrons-lacunas

Source: R. Reis 1999

Page 4: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.4

p.n = ni2

pi = ni = 1,45.1010/cm3 @ 27o C

Electrons and Holes

Source: Gilson Wirth. EMicro2004

Page 5: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.5

N-Type Silicon

Source: Gilson Wirth. EMicro2004

Page 6: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.6

P-Type Silicon

Source: Gilson Wirth. EMicro2004

Page 7: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.7

Electrons and Holes

Source: Gilson Wirth. EMicro2004

Page 8: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.8

Mobilidade dos elétrons Mobilidade das lacunas µn µp

OBS: Cerca de 3 vezes para o silício e 30 vezes para o AsGa

Resistividade: capacidade de um material veicular corrente - concentração de portadores (temperatura, dopagem) - mobilidade dos portadores no material

Dopantes: átomos com excesso de elétrons ou de buracos

Mobility of Carriers

Source: R. Reis 1999

Page 9: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.9

NMOS Transistor as ideal switch

G = 0

D

S

G = 1

D

S

S

D

Switch is off (no current)

D≠S

S

D

Switch is on Current until

D=S

Channel current is made of electrons (referred to as major carriers)

Page 10: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.10

G = 0

D

S

G = 1

D

S

S

D

Switch on Current until

D=S

S

D

Switch is off (no current)

D≠S

PMOS Transistor as ideal switch Channel current is made of holes (referred to as major carriers)

Page 11: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.11

N

N

N

P

Poly

Polysilicon

Silicon Oxide (SiO2)

N implant (or N “diffusion”) P bulk (substrate)

Sideview

The MOS Transistor

Source: R. Reis 1999

Page 12: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.12

N

N implant

P bulk (substrate)

Top

view

Contact

Source Drain Gate Si

devi

ew

channel

G (gate)

D S (drain) (source)

Source: R. Reis 1999

Page 13: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.13

Source Drain Gate = 0V

Source Drain Gate = Vdd

channel is on

channel is off

G

D S

Page 14: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.14

Truth table

Logic schematics Electric schematics

A Z

A Z

0 1 1 0

A Z

Vdd

Page 15: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.15

NMOS transistor PMOS transistor

Polysilicon (poly)

N well

Layout for CMOS Inverter

P implant (drain & source)

N implant (drain & source)

Active area & P implant (well contact)

Active area & P implant

(substrate contact)

Active areas

Page 16: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.16

NMOS transistor PMOS transistor

Polysilicon

Metal 1

Contact holes

Layout for CMOS Inverter

Metal 2

Via 1

Gnd Vdd

Gnd Vdd

Page 17: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.17

NMOS transistor PMOS transistor

Layout for CMOS Inverter To study the CMOS process steps, we will disregard substrate and well contacts

Poly

N well P implant

(drain & source)

N implant (drain & source)

Gnd Vdd

Page 18: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.18

NMOS transistor PMOS transistor Layout vs. AA’ Cross on Fabricated Structure

N well Field oxide

Transistor gate (poly)

P substrate

N implant

Transistor gate (poly)

Field oxide Field oxide

Gate (thin) oxide

Gate (thin) oxide P implant

Metal 1 Metal 2

A A’

Isolation oxide

N.B.: oxide = SiO2

Page 19: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.19

NMOS transistor PMOS transistor

Layout vs. AA’ Cross on Fabricated Structure

  Designers define only the top view geometries   The vertical geometries (thickness of the various materials)

are consequence of the fabrication process

Page 20: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.20

NMOS transistor PMOS transistor

Page 21: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.21

NMOS transistor PMOS transistor

Lp

Process Features: Gate Length

Ln, Lp: NMOS, PMOS transistor channel length Lmin: minimum channel length allowed by a given fabrication

process. Examples: 350nm, 180nm, 130nm, 90nm, 65nm, 45nm, 32nm, 22nm …

Ln

Page 22: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.22

Wn, Wp: NMOS, PMOS channel width

Wmin: minimum channel width allowed by a given fabrication process (generally, is the same value for both NMOS and PMOS)

NMOS transistor PMOS transistor

Wp Wn

Process Features: Gate Width

Page 23: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.23

A Single Well CMOS Process (Oldies)

N well Field oxide

Transistor gate (poly)

P substrate

N implant

Transistor gate (poly)

Field oxide Field oxide

Gate (thin) oxide

Gate (thin) oxide P implant

Metal 1 Metal 2

Isolation oxide

Obs: oxide = SiO2

Page 24: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.24

Dual-Well Trench-Isolated CMOS Process (Current)

Source: Rabaey; Chandrakasan; Nikolic, 2003

Epitaxial layer: Single-crystal film grown on silicon surface with controlled impurities, that can have fewer defects than native wafer surface.

Page 25: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.25

Chip (“die”)

Process testing chips

A wafer with several exemplars of a given die (chip)

Source: R. Reis 1999

Final Product

Page 26: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.26

The Czochralski Process

Pure silicon + high temperature melting dopant

up spin

motor Seed of single-crystalline silicon

Single-crystalline silicon ingot

Inductive heating

Source: Gilson Wirth, EMicro2004

Obtaining the Single-Crystalline Silicon Ingot

Page 27: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.27

Obtaining the Single-Crystalline Silicon Ingot

Source: R. Reis 1999

Page 28: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.28

Polishing the Single-Crystalline Cylinder Obtaining the Silicon Wafer

Source: R. Reis 1999

Page 29: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.29

1. Reference cut (to provide mask alignment)

2. Slicing the silicon ingot

Source: R. Reis 1999

Obtaining the Silicon Wafer

Page 30: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.30

Cada wafer passa individualmente por um processo de polimento, tanto das bordas como de suas superfícies. Source: R. Reis 1999

Page 31: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.31

Rinsing the Wafer Obtaining the Silicon Wafer

Source: R. Reis 1999

Page 32: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.32

Wafer Doping

Source: R. Reis 1999

Page 33: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.33

Photolithography

Source: Rabaey; Chandrakasan; Nikolic, 2003

Page 34: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.34

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

oxidation Optical mask

T

photoresist coating Photoresist removal (ashing)

spin, rinse, dry (SRD)

acid etch

Photoresist development

stepper exposure

Source: Fullman

Typical Operations in a Single Photolithography Cycle

process step

Page 35: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.35

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

oxidation Optical mask

T

photoresist coating Photoresist removal (ashing)

spin, rinse, dry (SRD)

acid etch

Photoresist development

stepper exposure

Modified from: Fullman

Typical Operations in a Single Photolithography Cycle

process step

Page 36: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.36

oxigênio

água

Forno de quartzo wafers

Si + O2 → SiO2 Si + 2H2O → SiO2 + 2H2 (gás)

1000oC a 1200oC

Oxidation (of Silicon Wafer)

Source: Gilson Wirth. EMicro2004

Page 37: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.37

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

oxidation Optical mask

T

photoresist coating Photoresist removal (ashing)

spin, rinse, dry (SRD)

acid etch

Photoresist development

stepper exposure

Modified from: Fullman

Typical Operations in a Single Photolithography Cycle

process step

Page 38: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.38

Photoresist Coating

A light sensitive polymer is evenly applied by spinning the wafer (thickness ~1µm)

Negative photoresist:

• Originally, is soluble in an organic solvent • When exposed to light, it becomes insoluble

Page 39: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.39

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

oxidation Optical mask

T

photoresist coating Photoresist removal (ashing)

spin, rinse, dry (SRD)

acid etch

Photoresist development

stepper exposure

Modified from: Fullman

Typical Operations in a Single Photolithography Cycle

process step

Page 40: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.40

Si substrate

SiO2

Photoresist (negative type)

UV light

Si substrate

SiO2

Development:

Modified from: Gilson Wirth. EMicro2004

Stepper Exposure & Photoresist Development

(glass) mask

•  Washed with either acid or base solution

•  Wafer is “soft-baked” to harden remaining photoresist

Page 41: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.41 Slide 41

Stepper

ASM Lithography Stepper

Page 42: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.42

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

oxidation Optical mask

T

photoresist coating Photoresist removal (ashing)

spin, rinse, dry (SRD)

acid etch

Photoresist development

stepper exposure

Modified from: Fullman

Typical Operations in a Single Photolithography Cycle

process step

Page 43: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.43

silicon

Coating (protection)

Material is selectively removed from areas of the wafer that are not covered by photoresist

Reactive solutions used (very dangerous). • E.g.: Hydrofluoric acid (isotropic etch), inappropriate for < 2.5µm

Source: Gilson Wirth. EMicro2004

Acid (Wet) Etching

Page 44: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.44

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

oxidation Optical mask

T

photoresist coating Photoresist removal (ashing)

spin, rinse, dry (SRD)

acid etch

Photoresist development

stepper exposure

Modified from: Fullman

Typical Operations in a Single Photolithography Cycle

process step

Page 45: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.45

The wafer is cleaned with deionized water and dried with nitrogen.

  Cleaning reduces the chances of contamination.   All processing is carried out in ultra-clean rooms

(dust particles per cubic foot of air are maintained at 1 to 10).

Source: Gilson Wirth. EMicro2004

Spin, Rinse and Dry (SRD)

Page 46: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.46

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

oxidation Optical mask

T

photoresist coating Photoresist removal (ashing)

spin, rinse, dry (SRD)

acid etch

Photoresist development

stepper exposure

Modified from: Fullman

Typical Operations in a Single Photolithography Cycle

process step

Page 47: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.47

Process Steps   Doping: Ion implantation (or Diffusion, in old tech.)

  Well Implants   Channel Implants (for threshold voltage adjustment)   Source/Drain Implants

  Deposition   Chemical Vapor Deposition (CVD): Dielectric   CVD: Tungsten   Physical Vapor Deposition (PVD)

  Etching   Conductor Etch: Metal Etch, Poly Etch and Silicon Trench Etch   Dielectric Etch

  Planarization

Page 48: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.48

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

oxidation Optical mask

T

photoresist coating Photoresist removal (ashing)

spin, rinse, dry (SRD)

acid etch

Photoresist development

stepper exposure

Modified from: Fullman

Typical Operations in a Single Photolithography Cycle

process step

Page 49: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.49

Photoresist Removal (Ashing)

A high-temperature plasma is used to remove the remaining photoresist without damaging device layers

Page 50: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.50

Patterning of SiO2

The image

The image

The image

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and deposition of negative photoresist

(c) Stepper exposure

Photoresist SiO 2

UV-light Patterned optical mask

Exposed resist

SiO 2

Si-substrate

Si-substrate

Si-substrate

SiO 2

SiO 2

(d) After development and etching of resist, chemical or plasma etch of SiO 2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasma etch

Source: Rabaey; Chandrakasan; Nikolic, 2003

Page 51: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.51

Process Steps

Page 52: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.52

Process Steps   Doping: Ion implantation (or Diffusion, in old tech.)

  Well Implants   Channel Implants (for threshold voltage adjustment)   Source/Drain Implants

  Deposition   Chemical Vapor Deposition (CVD): Dielectric   CVD: Tungsten   Physical Vapor Deposition (PVD)

  Etching   Conductor Etch: Metal Etch, Poly Etch and Silicon Trench Etch   Dielectric Etch

  Planarization

Page 53: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.53

•  = Adição de átomos de um material (“impurezas”) em um volume de outro material

•  Na fabricação de CIs, dopa-se certas regiões (volumes) do silício com portadores tipo P ou tipo N

•  As impurezas devem substituir átomos de silício dentro da rede cristalina

•  A dosagem depende da finalidade. Valor típico: um átomo de dopante para cada 107 átomos de silício

•  Profundidade típica da região dopada: 1µm

Doping (Dopagem )

Page 54: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.54

gás transportador (inerte)

líquido dopante

Forno de quartzo

Lâminas (dezenas a centenas)

aquecedor Temperatura

uniforme (1000oC)

Coeficiente de difusão depende da temperatura Fonte: Gilson Wirth, EMicro2004

Dopagem por Difusão

Page 55: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.55

Substrato

Ions Dopantes

•  Método simples, rápido e de grande escala •  Inconvenientes:

–  Imprecisão na área efetivamente dopada –  Maior concentração de dopante junto à superfície (perfil de dopagem segue Gaussiana)

Fonte: Gilson Wirth, EMicro2004

Dopagem por Difusão

proteção

Page 56: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.56

fonte de íons

acelerador primário

analisador magnético

eletrodos defletores

acelerador secundário

Íons de boro ou fósforo são formados em uma câmara de vácuo e selecionados por um analisador magnético que descarta íons de outros materiais

analisador magnético

Fonte: Gilson Wirth, EMicro2004

Dopagem por Implantação Iônica

Page 57: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.57

Substrato

Feixe de Ions

Profundidade dos íons depende de sua energia cinética, função de: • Massa do íon • Tensão de aceleração • Ângulo, com relação ao plano de cristalização Fonte: Gilson Wirth: EMicro2004

Dopagem por Implantação Iônica

Page 58: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.58

• Vantagens: – Precisão na geometria da área dopada – Permite controle independente da profundidade da região

dopada e da dosagem (⇒ Excelente controle do perfil de distribuição dos portadores)

• Desvantagens: – Processo mais complexo que difusão – As lâminas são processadas uma por vez (demanda muito

tempo e muitos recursos) – Bombardeamento iônico causa desalinhamentos e defeitos

diversos na estrutura cristalina (que perde suas características semicondutoras) ⇒ Recozimento

Dopagem por Implantação Iônica

Page 59: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.59

Um gás inerte (como o CF4) sob baixa pressão, quando ionizado por um campo elétrico intenso

Plasma

Page 60: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.60

forno ~ 1000ºC Deposição Química Auxiliada por Plasma - PECVD

Fonte: Gilson Wirth, EMicro2004

Plasma

íons

Fonte AC alta frequência

lâmina

SiH4 + NH3 → Si3N4 + H2 gás gás filme gás

Nitreto de silício é usado como “capa” durante a formação do óxido de gate

Page 61: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.61

forno ~ 1000ºC

SiH4

SiH4 → Si + H2 gás filme gás

lâminas SiH4 + H2

Deposição Química em Fase de Vapor - CVD

Adaptado de Gilson Wirth, EMicro2004

Deposição de Polissilício (gates dos transistores e conexões curtas)

Gás sileno

Page 62: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.62

material vaporizado subprodutos

2WF6 + 3Si → 2W + 3SiF4 (gás) W = tungstênio

Fonte: Gilson Wirth, EMicro2004

Deposição Química em Fase de Vapor - CVD Deposição de Tungstênio (para formar os contatos)

Page 63: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.63

suporte orbital

lâminas

fornalha

alumínio vaporizado

Fonte: Gilson Wirth, EMicro2004

Deposição por Evaporação Deposição de Alumínio (para formar as conexões)

Page 64: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.64

Deposição por Borrifamento (Sputtering) Deposição de Alumínio (para formar as conexões)

íons Material arrancado

lâmina

Alta tensão (contínua)

Fonte: Gilson Wirth, EMicro2004

Page 65: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.65

Etching (corrosão)

Após a deposição de algum material (sobre toda a wafer), o material é retirado seletivamente, sendo conservado apenas nas regiões de interesse. Dois tipos de etching: • Acid or Wet etching (já visto) • Dry or plasma etching, mais recentemente usado.

Page 66: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.66

Plasma

íons

Fonte AC alta frequência

lâmina

eletron + CF4 → CF3 + F 4F + Si → SiF4 (gás)

Plasma Etching

Fonte: Gilson Wirth, EMicro2004

Page 67: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.67

Plasma Etching

Substrato

Coating Poly

Ions

Fonte: Gilson Wirth, EMicro2004

Page 68: Integrated Circuits & SystemsLecture 5 CMOS Fabrication Process Prof. José Luís Güntzel guntzel@inf.ufsc.br Integrated Circuits & Systems INE 5442 Federal University of Santa Catarina

CMOS Fabrication Process

Lecture 5 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 5.68

References

1.  RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. 2nd Edition. Prentice Hall, 2003. ISBN: 0-13-090996-3.

2.  JAEGER, Richard C. “Introduction to Microelectronic Fabrication” 2nd Edition. (Modular Series on Solid State Devices, Vol V), Prentice Hall, 2002.

3.  REIS, Ricardo.(Organizador.) Concepção de Circuitos Integrados. Porto Alegre: Sagra-Luzzatto/UFRGS, 2002. 2a edição. Cap. 3. ISBN 85-241-0625-5