Instruction Set Reference [by Bradley]

8/8/2019 Instruction Set Reference [by Bradley]

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InstructionSet Reference

PLC-5ProgrammableControllers

Allen-Bradley


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PLC-5 Instruction Set Alphabetical Listing


For this

Instruction:See Page:

For this


For this


For this


ABL 17-51 CMP 3-3 JSR 13-12 RES 2-25

ACB 17-71 COP 9-20 LBL 13-5 RET 13-12

ACI 17-91 COS 4-211 LEQ 3-9 RTO 2-13

ACN 17-101 CPT 4-5 LES 3-10 SBR 13-12

ACS 4-131 CTD 2-20 LFL 11-51 SDS 18-2

ADD 4-14 CTU 2-18 LFU 11-51 SFR 13-231

AEX 17-111 DDT 10-2 LIM 3-11 SIN 4-271

AFI 13-19 DEG 6-51 LN 4-231 SQI 12-2

AHL 17-121 DFA 18-3 LOG 4-241 SQL 12-2

AIC 17-141 DIV 4-22 MCR 13-3 SQO 12-2

AND 5-2 DTR 10-8 MEQ 3-13 SQR 4-28

ARD 17-151 EOT 13-24 MOV 7-4 SRT 4-291

ARL 17-181 EQU 3-6 MSG 16-2 STD 4-311

ASC 17-211 FAL 9-2 MUL 4-25 SUB 4-34

ASN 4-151 FBC 10-2 MVM 7-5 TAN 4-351

ASR 17-221 FFL 11-5 NEG 4-26 TND 13-19

ATN 4-161 FFU 11-5 NEQ 3-15 TOD 6-3

AVE 4-171 FLL 9-21 NOT 5-4 TOF 2-9

AWA 17-231 FOR 13-8 NXT 13-8 TON 2-5

AWT 17-261 FRD 6-4 ONS 13-20 UID 13-251

BRK 13-8 FSC 9-15 OR 5-6 UIE 13-261

BSL 11-2 GEQ 3-7 OSF 13-221 XIC 1-3

BSR 11-2 GRT 3-8 OSR 13-211 XIO 1-4

BTD 7-2 IDI 1-102 OTE 1-5 XOR 5-8

BTR 15-4 IDO 1-112 OTL 1-6 XPY 4-361

BTW 15-4 IIN 1-8 OTU 1-7 1 Enhanced PLC -5 processorsonly.

2 6200 programming software

with ControlNet PLC-5

processors only

CIO 15-252 IOT 1-9 PID NO TAG

CLR 4-20 JMP 13-5 RAD 6-61


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Table AChoosing an Instruction Category

Table BExample Operations

If You Want to Performthis Operation:

Use this Instruction Category:

examine, check or control 2- state device or condition bit levelmultiple 2-state devices or conditions multi-bit

move, copy, change,compute, compare

analog values, codes element levelmultiple sets of values file instructions

convert conversion instructions

time or delay timer

count counter

shift or track bit shift

sequence sequencer

PID PID

message sending/receiving message

transfer data to/from modules block transfer or ControlNet transfer

diagnostics, fault handl ing diagnostics

control the flow of your program program control

If Your Application Calls for Operations such as: Use:

detecting when a limit switch closes bit level

changing the temperature preset element level

transfer analog data block transfer

turn on a motor 10 seconds after a pump is activated timing

move 1 of 3 recipes into a work area multi-element

keep track of parts as they move from station to station shifting

keep track of total parts in a bin counting


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Summary of Changes

Summary of Changes

New Information Added to

this Manual

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For this Update Information: See Chapter:

Converting non-decimal numbers with the FRD instruction 6

How non-existing, indirect addresses affect the COP andFLL instructions

9

How the .POS value operates in sequencer instructions 12

Using a RET instruction 13

Using the PID bias term 14

Using the no zero crossing (.NOZC) and no back calculation(.NOBC) features in the PD control block

14

Clarification to error code 89 for MSG instruction 16

Ethernet PLC-5 processors now support SLC Typed Read andSLC Typed Write MSG instructions

16

Configuring a multihop MSG instruction over Ethernet orover ControlNet

16

Monitoring the status of the .EN bit in a continuousMSGinstruction

16


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Preface

Preface

Conventions 7KLVPDQXDOXVHVWKHIROORZLQJFRQYHQWLRQV

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>Enter]; [F1] Online Programming/Documentation

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filename

0HVVDJHVDQGSURPSWVWKDWWKHWHUPLQDOGLVSOD\VDUHVKRZQDV

Press a function key

References to: Include these Allen- Bradley Processors:

Classic PLC-5 processors PLC-5/10, -5/12, -5/15, -5/25, and -5/VME processors.

Enhanced PLC-5 processors PLC-5/11, -5/20, -5/30, -5/40, -5/40L, -5/60 ,-5/60L, and -5/80 processors.

Note: Unless otherwise specified, Enhanced PLC-5 processors includeEthernet PLC-5, ControlNet PLC-5, Protected PLC-5 and VME PLC-5processors.

Ethernet PLC-5 processors PLC-5/20E, - 5/40E, and -5/80E processors.

ControlNet PLC-5 processors PLC-5/20C , -5/40C, -5/46C, and -5/80C processors.

Protected PLC-5 processors 1 PLC-5/26, -5/46, and -5/86 processors.

VME PLC-5 processors PLC-5/V30, -5/V40, -5/V40L, and -5/V80 processors. See thePLC-5/VME VMEbus Programmable Controllers User Manual for moreinformation.

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Preface

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Table of Contents

1785-6.1 November 1998

Relay-Type InstructionsXIC, XIO, OTE, OTL, OTU, IIN, IOT,

IDI, IDO

Chapter 1Using Relay-Type Instructions . . . . . . . . . . . . . . . . . . . . . . . . 1-1I/O Image Files in Data Storage . . . . . . . . . . . . . . . . . . . . . 1-2

Rung Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Examine On (XIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Examine Off (XIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Energize (OTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4Latch (OTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4Unlatch (OTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5Immediate Input (IIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6Immediate Output (IOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Immediate Data Input (IDI). . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Immediate Data Output (IDO). . . . . . . . . . . . . . . . . . . . . . . . . 1-8Using IDI and IDO Instructions . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Timer Instructions TON, TOF,

RTO Counter Instructions CTU,

CTD Reset RES

Chapter 2Using Timers and Counters . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Using Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2Timer Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3Timer On Delay (TON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Timer Off Delay (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Retentive Timer On (RTO) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Using Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

Count Up (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Count Down (CTD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

Timer and Counter Reset (RES). . . . . . . . . . . . . . . . . . . . . . 2-20


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toc4 Table of Contents

File Instructions

FAL, FSC, COP, FLL

Chapter 9Using File Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1File Arithmetic and Logic (FAL) . . . . . . . . . . . . . . . . . . . . . . . 9-2

Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

FAL Copy Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

FAL Arithmetic Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7Upper and Lower Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

FAL Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12FAL Convert Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14File Search and Compare (FSC). . . . . . . . . . . . . . . . . . . . . . 9-14

Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15

FSC Search and Compare Operations . . . . . . . . . . . . . . . . . 9-17Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17

File Search Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17

File Copy (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19

File Fill (FLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20

Diagnostic Instructions

FBC, DDT, DTR

Chapter 10Using Diagnostic Instructions . . . . . . . . . . . . . . . . . . . . . . . 10-1File Bit Comparison (FBC) and Diagnostic Detect (DDT) . . . . 10-2

Selecting the Search Mode . . . . . . . . . . . . . . . . . . . . . . . 10-2

One Mismatch at a Time . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

All Per Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5Data Transitional (DTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8


Shift Register Instructions

BSL, BSR, FFL, FFU, LFL, LFU

Chapter 11Applying Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1Using Bit Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 11-2



Using FIFO and LIFO Instructions. . . . . . . . . . . . . . . . . . . . . 11-5Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5


Sequencer Instructions

SQO, SQI, SQL

Chapter 12Applying Sequencers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1Using Sequencer Instructions . . . . . . . . . . . . . . . . . . . . . . . 12-2



Resetting the Position of SQO . . . . . . . . . . . . . . . . . . . . . 12-6

Using SQI Without SQO . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7


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Program Control Instructions MCR,

JMP, LBL, FOR, NXT, BRK, JSR,

SBR, RET, TND, AFI, ONS, OSR, OSF,

SFR, EOT, UIE, UID

Chapter 13Selecting Program Flow Instructions . . . . . . . . . . . . . . . . . . 13-1Master Control Reset (MCR) . . . . . . . . . . . . . . . . . . . . . . . . 13-2Jump (JMP) and Label (LBL) . . . . . . . . . . . . . . . . . . . . . . . . 13-3

Using JMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

Using LBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4For Next Loop (FOR, NXT), Break (BRK) . . . . . . . . . . . . . . . . 13-5


Using FOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

Using BRK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7

Using NXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7

Jump to Subroutine (JSR), Subroutine (SBR),and Return (RET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8

Passing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10

Nesting Subroutine Files . . . . . . . . . . . . . . . . . . . . . . . . 13-10Using JSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11

Using SBR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11

Using RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12

Temporary End (TND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13Always False (AFI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13One Shot (ONS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14One Shot Rising (OSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15


One Shot Falling (OSF). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16

Sequential Function Chart Reset (SFR). . . . . . . . . . . . . . . . 13-17Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17

End of Transition (EOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18User Interrupt Disable (UID) . . . . . . . . . . . . . . . . . . . . . . . . 13-19User Interrupt Enable (UIE). . . . . . . . . . . . . . . . . . . . . . . . . 13-20

Process Control Instruction PID Chapter 14Using PID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

PID Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

Using PID Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2Conversion of Gain Constants . . . . . . . . . . . . . . . . . . . . . 14-3

Integral Term Implementation . . . . . . . . . . . . . . . . . . . . . 14-3

Derivative Term . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

Setting Input/Output Ranges . . . . . . . . . . . . . . . . . . . . . . . . 14-5Implementing Scaling to Engineering Units . . . . . . . . . . . . . 14-5Setting the Dead Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

Using Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

Using No Zero Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

Selecting the Derivative Term (Acts on PV or Error) . . . . . . . 14-7


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Setting Output Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7Using Output Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

Anti-Reset Windup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8

Using a Manual Mode Operation (Bumpless Transfer) . . . 14-8

Set Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8

Feedforward or Output Biasing . . . . . . . . . . . . . . . . . . . . . . 14-9Resume Last State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9PID Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10

Using No Back Calculation. . . . . . . . . . . . . . . . . . . . . . . 14-11

Operational Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . 14-11

Integer Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11

PD Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12


Using an Integer Data File Type for the Control Block. . . . . 14-14Using Control Block Values . . . . . . . . . . . . . . . . . . . . . . 14-16

Using a PD File Type for the Control Block. . . . . . . . . . . . . 14-18Using Control Block Values . . . . . . . . . . . . . . . . . . . . . . 14-23

Programming Considerations . . . . . . . . . . . . . . . . . . . . . . 14-25Run Time Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25

Transferring Data to the PID Instruction . . . . . . . . . . . . . 14-25

Loop Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26Number of PID Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26

Loop Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26

Descaling Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27PID Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29Integer Block (N) Examples . . . . . . . . . . . . . . . . . . . . . . . . 14-29

Main Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29STI Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30

RTS Program File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32

PD Block Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33Main Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33

STI Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34

RTS Program File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36

Ladder Logic Simulation of a Manual Control Station . . . 14-37

Cascading Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38

Ratio Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38

Process Variable Tracking . . . . . . . . . . . . . . . . . . . . . . . 14-39PID Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40


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Message Instruction MSG Chapter 16Using the Message Instruction. . . . . . . . . . . . . . . . . . . . . . . 16-1Message (MSG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

Control Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

MSG Data Entry Screen . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3Using the Message Instruction for EthernetCommunications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5


Using the Message Instruction for PLC-5 Ethernet InterfaceModule Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7


Configuring an Ethernet Multihop MSGInstruction. . . . . . . . 16-9Using the Message Instruction for ControlNetCommunications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10

Control Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10

Configuring a ControlNet Multihop MSGInstruction . . . . . . 16-11Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12Using the Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13

Error Code (.ERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13

Requested Length (.RLEN). . . . . . . . . . . . . . . . . . . . . . . 16-13

Transmitted Length (.DLEN). . . . . . . . . . . . . . . . . . . . . . 16-13

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14Communication Command . . . . . . . . . . . . . . . . . . . . . . 16-14

External Data Table Addresses. . . . . . . . . . . . . . . . . . . . 16-15

PLC-2 to PLC-5 Compatibility Files . . . . . . . . . . . . . . . . 16-15

Sending SLC Typed Logical Read and Typed LogicalWrite Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16

Monitoring a Message Instruction . . . . . . . . . . . . . . . . . . . 16-17Selecting Continuous Operation. . . . . . . . . . . . . . . . . . . . . 16-18Selecting Non-Continuous Operation . . . . . . . . . . . . . . . . . 16-19MSG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22


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Table of Contents toc9

ASCII Instructions

ABL, ACB, ACI, ACN, AEX, AIC, AHL,

ARD, ARL, ASC, ASR, AWA, AWT

Chapter 17Using ASCII InstructionsEnhanced PLC-5 Processors Only . . . . . . . . . . . . . . . . . . . . 17-1


Using the Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

Length (.LEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3Position (.POS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

Using Strings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

Test Buffer for Line (ABL) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

Number of Characters in Buffer (ACB) . . . . . . . . . . . . . . . . . 17-5Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5

ASCII String to Integer (ACI). . . . . . . . . . . . . . . . . . . . . . . . . 17-6ASCII String Concatenate (ACN). . . . . . . . . . . . . . . . . . . . . . 17-7ASCII String Extract (AEX) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7

Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7ASCII Set or Reset Handshake Lines (AHL). . . . . . . . . . . . . . 17-8Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8

ASCII Integer to String (AIC). . . . . . . . . . . . . . . . . . . . . . . . . 17-9ASCII Read Characters (ARD). . . . . . . . . . . . . . . . . . . . . . . 17-10


ASCII Read Line (ARL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12

ASCII String Search (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . 17-14Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14

ASCII String Compare (ASR). . . . . . . . . . . . . . . . . . . . . . . . 17-15

ASCII Write with Append (AWA) . . . . . . . . . . . . . . . . . . . . . 17-15Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15

ASCII Write (AWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17

Custom Application Routine

Instructions SDS, DFA

Chapter 18Chapter Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1Smart Directed Sequencer (SDS) Overview . . . . . . . . . . . . . 18-2

Programming the SDS Instruction . . . . . . . . . . . . . . . . . . 18-2

Diagnostic Fault Annunciator (DFA) Overview . . . . . . . . . . . 18-3Programming the DFA Instruction . . . . . . . . . . . . . . . . . . 18-3


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Instruction Timing and

Memory Requirements

Appendix A-1Instruction Timing and Memory Requirements. . . . . . . . . . . . A-1Timing for Enhanced PLC-5 Processors. . . . . . . . . . . . . . . . . A-2

Bit and Word Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . A-2

File Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

Timing for Classic PLC-5 Processors. . . . . . . . . . . . . . . . . . A-10Bit and Word Instructions. . . . . . . . . . . . . . . . . . . . . . . . . A-10

File Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13

Program Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17Direct and Indirect Elements: Enhanced PLC-5 Processors . A-17Direct and Indirect Elements: Classic PLC-5 Processors . . . A-18Indirect Bit or Elements Addresses: ClassicPLC-5 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-19Additional Timing Considerations: ClassicPLC-5 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20

SFC Reference Appendix B-1Appendix Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1SFC Status Information in the Processor Status File. . . . . . . . B-1Memory Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3Dynamic Constraints Classic PLC-5 Processors Only . . . . . B-5Scanning Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

Step and Transition Scanning . . . . . . . . . . . . . . . . . . . . . . B-7

Selected Branch Scanning. . . . . . . . . . . . . . . . . . . . . . . . . B-8

Simultaneous Branch Scanning. . . . . . . . . . . . . . . . . . . . . B-9

SFC Example and Scan Sequence . . . . . . . . . . . . . . . . . . B-11

Run Times Classic PLC-5 Processors . . . . . . . . . . . . . . . . B-12Using Sequence Diagrams to Determine Run Time . . . . . B-13

Using Equations to Determine Run Time . . . . . . . . . . . . . B-14

Valid Data Types for

Instruction Operands

Appendix C-1Appendix Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1Instruction Operands and Valid Data Types . . . . . . . . . . . . . . C-1


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1-2 Relay-Type Instructions XIC, XIO, OTE, OTL, OTU, IIN, IOT, IDI, IDO

I/O Image Files in Data Storage

7KHLQSXWLPDJHILOHLQWKHSURFHVVRUVWRUHVWKHVWDWXVRILQSXWVHQVRUV

FRQQHFWHGWRLQSXWPRGXOHWHUPLQDOV


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Energize (OTE)

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Latch (OTL)

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01

Example:

Turn ON bit O:013/01 of the output image table ifthe rung is true. Turn it OFF if the rung is false.

This bit corresponds to output terminal 01 of amodule in /O group 3 of I/O rack 1.

If the Rung Is: Then the Processor Turns the Bit: Bit Logic State:

true on 1

false off 0

L

O:013

01

Example:

L

Turn ON bit O:013/01 of the output image tableif the rung is true.

This bit corresponds to output terminal 1 of amodule in I/O group 3 of I/O rack 1.


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Relay-Type Instructions XIC, XIO, OTE, OTL, OTU, IIN, IOT, IDI, IDO 1-5

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true on

false no change

U

U

O:013

01

Example:

Turn OFF bit O:013/01 of the output image tableif the rung is true.

This bit corresponds to output terminal 1 of amodule in I/O group 3 in I/O rack 1.

If the Rung is: Then the Processor Turns the Bit:

true off

false no change


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Immediate Input (IIN)

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IIN

IIN

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Example:

Where:

RR = I/O rack number00-03 PLC-5/10, -5/11, -5/12, -5/15, -5/2000-07 PLC-5/25, -5/30000-177 PLC-5/40, -5/40L000-277 PLC-5/60, -5/60L, -5/80

G = I/O group number (0 - 7)

IIN

001

When the input conditions are true, update theinput image word corresponding to I/O rack 0,group 1.

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Immediate Output (IOT)

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IOT

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Example:

Where:

RR = I/O rack number00-03 PLC-5/10, -5/11, -5/12, -5/15, -5/2000-07 PLC-5/25, -5/30000-177 PLC-5/40, -5/40L000-277 PLC-5/60, -5/60L, -5/80

G = I/O group number (0 - 7)

IOT

001

When the input conditions are true, update theoutput image word corresponding to I/O rack 0,group 1.

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Immediate Data Input (IDI)

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/HQJWKVSHFLILHVWKHQXPEHURIZRUGVWREHWUDQVIHUUHGDQLPPHGLDWHYDOXHRUDORJLFDODGGUHVVWKDWVSHFLILHVWKHQXPEHURIZRUGVWREHWUDQVIHUUHG

'HVWLQDWLRQVSHFLILHVDGDWDWDEOHDGGUHVVWREHXVHGDVWKH

GHVWLQDWLRQRIWKHZRUGVWREHWUDQVIHUUHG

,PSRUWDQW7KH'HVWLQDWLRQVKRXOGEHWKHPDWFKLQJGDWDWDEOH

DGGUHVVLQWKH'DWD,QSXW)LOH',)H[FHSWZKHQ\RX

XVHWKHLQVWUXFWLRQWRHQVXUHGDWDEORFNLQWHJULW\LQWKH

FDVHRI6HOHFWDEOH7LPHG,QWHUUXSWV67,V)RUPRUH

LQIRUPDWLRQVHHSDJH

Immediate Data Output (IDO)

Description: :KHQWKHUXQJJRHVWUXHWKH,'2LQVWUXFWLRQSHUIRUPVDQLPPHGLDWHXSGDWHRIWKH&RQWURO1HWPHPRU\EXIIHUVIURPWKHVRXUFHILOHEHIRUH

WKHQH[WRXWSXWLPDJHXSGDWHVHQGLQJWKHXSGDWHGGDWDRXWSXWILOHLQIRUPDWLRQDFURVVWKH&RQWURO1HWQHWZRUNWRWKHDSSURSULDWH

&RQWURO1HWGHYLFH

7RSURJUDPDQ,'2LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRUZLWK

WKHIROORZLQJLQIRUPDWLRQWKDWLWVWRUHVLQLWVFRQWUROEORFN

'DWDILOHRIIVHWVSHFLILHVWKHRIIVHWLQWRWKH'DWD2XWSXW)LOH'2)ZKHUHZRUGVDUHZULWWHQFDQEHDQLPPHGLDWHYDOXHRUDORJLFDODGGUHVVWKDWVSHFLILHVWKHGDWDLPDJHILOHRIIVHW

/HQJWKVSHFLILHVWKHQXPEHURIZRUGVWREHWUDQVIHUUHGDQLPPHGLDWHYDOXHRUDORJLFDODGGUHVVWKDWVSHFLILHVWKHQXPEHURIZRUGVWREHWUDQVIHUUHG

6RXUFHVSHFLILHVDGDWDWDEOHDGGUHVVWREHXVHGDVWKHVRXUFHRIWKHZRUGVWREHWUDQVIHUUHG

,PSRUWDQW7KH6RXUFHVKRXOGEHWKHPDWFKLQJGDWDWDEOHDGGUHVVLQ

WKH'DWD2XWSXW)LOH'2)H[FHSWZKHQ\RXXVHWKH

LQVWUXFWLRQWRHQVXUHGDWDEORFNLQWHJULW\LQWKHFDVHRI

6HOHFWDEOH7LPHG,QWHUUXSWV67,V)RUPRUH

LQIRUPDWLRQVHHSDJH

IDI

IMMEDIATE DATA INPUT

Data file offset

Length

Destination

10

N10:232

232

IDO

IMMEDIATE DATA OUTPUT

Data file offset

Length

Source

10

N7:232

232


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Using IDI and IDO Instructions


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1RWHV


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Chapter 2

Timer Instructions TON, TOF, RTO

Counter Instructions CTU, CTDReset RES

Using Timers and Counters 7LPHUVDQGFRXQWHUVOHW\RXFRQWURORSHUDWLRQVEDVHGRQWLPHRUQXPEHURIHYHQWV7DEOH$OLVWVWKHDYDLODEOHWLPHUDQGFRXQWHU

LQVWUXFWLRQV

Table 2.AAvailable Timer and Counter Instructions

)RUPRUHLQIRUPDWLRQRQWKHRSHUDQGVDQGYDOLGGDWDW\SHVYDOXHVRI

HDFKRSHUDQGXVHGE\WKHLQVWUXFWLRQVGLVFXVVHGLQWKLVFKDSWHUVHH$SSHQGL[&

Using Timers

%HIRUH\RXSURJUDPWLPHULQVWUXFWLRQV\RXQHHGWRXQGHUVWDQGWKH

SDUDPHWHUVWKDW\RXHQWHUIRUWLPHULQVWUXFWLRQVDQGKRZWLPHU

DFFXUDF\ZRUNV

If You Want to: Use this Instruction: Found on Page:

Delay turning on an output TON 2-4

Delay turning off an output TOF 2-7

Time an event retentively RTO 2-10

Count up CTU 2-15

Count down CTD 2-17

Reset a counter, timer, or counterinstruction

RE 2-20


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2-2 Timer Instructions TON, TOF, RTO Counter Instructions CTU, CTD Reset RES

Entering Parameters 7RSURJUDPDWLPHULQVWUXFWLRQSURYLGHWKHSURFHVVRUZLWKWKHIROORZLQJLQIRUPDWLRQ

7LPHULVWKHWLPHUFRQWURODGGUHVVLQWKHWLPHU7DUHDRIGDWDVWRUDJH8VHWKHIROORZLQJDGGUHVVIRUPDW

,PSRUWDQW


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Timer Instructions TON, TOF, RTO Counter Instructions CTU, CTD Reset RES 2-3

7LPH%DVHGHWHUPLQHVKRZWKHWLPHURSHUDWHV7DEOH%OLVWVWKHSRVVLEOHWLPHEDVHV

Table 1.BAvailable Time Base Values

3UHVHWVSHFLILHVWKHYDOXHZKLFKWKHWLPHUPXVWUHDFKEHIRUHWKHSURFHVVRUVHWVWKHGRQHELW'1


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Figure 2.2Example TON Timing Diagram

ON

OFF

180

120

0

16649

Rung Condition

Timer Enable Bit

Timer Timing Bit

Timer Done Bit

Output Device(Controlled by Done Bit)

Timer Accumulated Value

(Accumulator)

Timer Preset = 180

2 minutes

3 minutes ONDelay

ON

OFF

ON

OFF

ON

OFF

ON

OFF


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,I\RXVHWWKHGRQHELW'1XVLQJDQ27(LQVWUXFWLRQIRUH[DPSOH

\RXFDQSDXVHWKHWLPHU7KH(1DQG77ELWVUHPDLQVHWEXWWKH

DFFXPXODWHGYDOXHGRHVQRWLQFUHPHQW7LPLQJUHVXPHVZKHQ\RX

FOHDUWKH'1ELW,IWKHUXQJJRHVIDOVHZKLOHWKHWLPHULVSDXVHGWKH

WLPHUUHVHWVDVQRUPDO

,I\RXFKDQJHWR3URJUDPPRGHRUWKHSURFHVVRUORVHVSRZHURUWKHSURFHVVRUIDXOWLQWHUUXSWVWKH72)LQVWUXFWLRQEHIRUHLW

UHDFKHVWKHSUHVHWYDOXHWKHIROORZLQJRFFXUV

WLPHUHQDEOH(1ELWUHPDLQVUHVHW

WLPHUWLPLQJ77ELWUHPDLQVVHW

WLPHUGRQH'1ELWUHPDLQVVHW

DFFXPXODWHG$&&YDOXHUHPDLQVWKHVDPH

7KHQLI\RXVZLWFKWR5XQPRGHRU7HVWPRGHWKHIROORZLQJ

KDSSHQV

'XULQJSUHVFDQWKHIROORZLQJKDSSHQV

WLPHUWLPLQJ77ELWLVFOHDUHG

DFFXPXODWHG$&&YDOXHLVHTXDOWRWKHSUHVHWYDOXH

Condition: Result:

If the rung is true: .EN bit is set.TT bit is reset.DN bit remains set.ACC value is cleared

If the rung is false: .EN bit is reset.TT bit is reset.DN bit is reset.ACC value equals PRE value(the timer does not start timing)

$77(17,21 %HFDXVHWKH5(6LQVWUXFWLRQUHVHWVWKHDFFXPXODWHGYDOXHGRQHELWDQGWLPLQJELWVRIDWLPLQJ

LQVWUXFWLRQGRQRWXVHWKH5(6LQVWUXFWLRQWRUHVHWD72)

WLPHU


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Figure 2.3Example TOF Ladder Diagram

Figure 2.4Example TOF Timing Diagram

EN

TOF

TIMER OFF DELAY

TimerTime base

Preset

Accum

T4:01.0

180

0

DN

T4:0

TT

O:013Sets the output while the timer is timing

I:012

T4:0

DN

O:013Resets the output when the timer is done timing

10

01

02

When the input goes false, the processor startsincrementing the accumulated value in T4:0 in1-second increments until the input goes true.

When bit I:012/10 is reset, the processor starts timer T4:0. The accumulated value increments by 1-second intervals as long as therung remains false. T4:0.TT is set and output bit O:013/01 is set (the associated output device is energized) while the timer is timing.When the timer is finished (.ACC = .PRE), T4:0.TT is reset (so O:013/01 is reset and the associated output device is de-energized)and T4:0.DN is reset (so O:013/02 is reset and the associated output device is de-energized). When the accumulated value reaches180 or when the rung conditions go true, the timer stops.

ON

OFF

180

120

0

16650

Rung Condition

Timer Enable Bit

Timer Timing Bit

Timer Done Bit


Timer Accumulated Value(Accumulator)

Timer Preset = 180

2 minutes 3 minutesOFF Delay

ON

OFF

ON

OFF

ON

OFF

ON

OFF

Time


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,I\RXVHWWKHGRQHELW'1XVLQJDQ27(LQVWUXFWLRQIRUH[DPSOH

\RXFDQSDXVHWKHWLPHU7KH(1DQG77ELWVUHPDLQVHWEXWWKH

DFFXPXODWHGYDOXHGRHVQRWLQFUHPHQW7LPLQJUHVXPHVZKHQ\RX

FOHDUWKH'1ELW,IWKHUXQJJRHVIDOVHZKLOHWKHWLPHULVSDXVHGWKH

WLPHUUHVHWVDVQRUPDO

,I\RXFKDQJHWR3URJUDPPRGHRUWKHSURFHVVRUORVHVSRZHURUDSURFHVVRUIDXOWLQWHUUXSWVWKH572LQVWUXFWLRQWKHIROORZLQJ

RFFXUV

WLPHUHQDEOH(1ELWUHPDLQVVHW

WLPHUWLPLQJ77ELWUHPDLQVVHW

DFFXPXODWHG$&&YDOXHUHPDLQVWKHVDPH

:KHQ\RXVZLWFKEDFNWR5XQPRGHRU7HVWPRGHWKHIROORZLQJ

KDSSHQV

Figure 2.5Example RTO Ladder Diagram

Condition: Result:

If the rung is t rue: .EN bit remains set.TT bit remains set.ACC value continues timing

If the rung is false: .EN bit is reset.TT bit is reset.DN bit remains the same.ACC value remains the same

EN

RTO

RETENTIVE TIMER ONTimer

Time base

Preset

Accum

T4:10

1.0

180

0

DN

I:012

10When the input is true, the processor starts incrementingthe accumulated value of T4:10 in 1- second increments.The timer values remain when the input goes false.

RES

I:017

12

T4:10Resets the timer


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Figure 2.6Retentive Timer Timing Diagram

ON

OFF

180

120

016651

Rung Condition

Timer Enable Bit

Timer Timing Bit

Timer Done Bit


Timer Accumulated Value(Accumulator)

Timer Preset = 180

ON

OFF

ON

OFF

ON

OFF

ON

OFF

Reset Pulse

40

100

ON

OFF


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Using Counters %HIRUHXVLQJFRXQWHULQVWUXFWLRQV\RXQHHGWRXQGHUVWDQGWKHSDUDPHWHUVWKDW\RXHQWHU

Entering Parameters

7RSURJUDPDFRXQWHULQVWUXFWLRQSURYLGHWKHSURFHVVRUZLWKWKHIROORZLQJLQIRUPDWLRQ

&RXQWHULVWKHFRXQWHUFRQWURODGGUHVVLQWKHFRXQWHU&DUHDRIGDWDVWRUDJH8VHWKHIROORZLQJDGGUHVVIRUPDW

,PSRUWDQW


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3UHVHWVSHFLILHVWKHYDOXHZKLFKWKHFRXQWHUPXVWUHDFKEHIRUHLWVHWVWKHGRQHELW'1(QWHUDSUHVHWYDOXHIURPXSWR7KHSUHVHWYDOXHLVVWRUHGDVDELWLQWHJHUYDOXH

1HJDWLYHYDOXHVDUHVWRUHGLQWZRVFRPSOHPHQWIRUP

$FFXPXODWHG9DOXH LVWKHFXUUHQWFRXQWEDVHGRQWKHQXPEHURI

WLPHVWKHUXQJJRHVIURPIDOVHWRWUXH7KHDFFXPXODWHGYDOXHLVVWRUHGDVDELWLQWHJHUYDOXH1HJDWLYHYDOXHVDUHVWRUHGLQWZRVFRPSOHPHQWIRUP7KHUDQJHRIWKHDFFXPXODWHGYDOXHLVWR7\SLFDOO\\RXHQWHUD]HURYDOXHZKHQSURJUDPPLQJFRXQWHULQVWUXFWLRQV,I\RXHQWHUDQRQ]HURYDOXHWKHLQVWUXFWLRQVWDUWVFRXQWLQJIURPWKDWYDOXH,IWKHFRXQWHULVUHVHWWKHDFFXPXODWHGYDOXHLVVHWWR]HUR


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Count Up (CTU)

Description: 7KH&78LQVWUXFWLRQFRXQWVXSZDUGRYHUDUDQJHRIWR(DFKWLPHWKHUXQJJRHVIURPIDOVHWRWUXHWKH&78

LQVWUXFWLRQLQFUHPHQWVWKHDFFXPXODWHGYDOXHE\RQHFRXQW:KHQ

WKHDFFXPXODWHGYDOXHHTXDOVRUH[FHHGVWKHSUHVHWYDOXHWKH&78LQVWUXFWLRQVHWVDGRQHELW'1ZKLFK\RXUODGGHUSURJUDPFDQ

XVHWRLQLWLDWHVRPHDFWLRQVXFKDVFRQWUROOLQJDVWRUDJHELWRUDQ

RXWSXWGHYLFH

7KHDFFXPXODWHGYDOXHRIDFRXQWHULVUHWHQWLYH7KHFRXQWLVUHWDLQHG

XQWLOUHVHWE\DUHVHWLQVWUXFWLRQ5(6WKDWKDVWKHVDPHDGGUHVVDV

WKHFRXQWHU

Using Status Bits

([DPLQHVWDWXVELWVLQWKHODGGHUSURJUDPWRWULJJHUVRPHHYHQW7KH

SURFHVVRUFKDQJHVWKHVWDWHVRIVWDWXVELWVZKHQWKHSURFHVVRUUXQVWKH&78LQVWUXFWLRQ


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Figure 2.7Example CTU Ladder Diagram

Figure 2.8Example CTU Timing Diagram

CU

CTU

COUNT UP

Counter

Preset

Accum

C5:0

4

0

DN

C5:0

DN

O:020Tells when the count is reached (ACC > or = PRE)

I:012

10

C5:0

OV

O:021Tells when the counter overflows +32,767

RES

I:017

12

C5:0

01

02

Reset the counter

Each time the input goes false to true,the processor increments the counterby 1.

12

34

0

Counter preset = 4 counts

0 16636

Rung condition thatcontrols counter

Rung condition thatcontrols reset instruction

Done Bit

Output instruction on rungcontrolled by counter

Counter Accumulated Value

ON

OFF

ON

OFF

ON

OFF

ON

OFF

Count-up enable bit

ON

OFF


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Count Down (CTD)

Description: 7KH&7'LQVWUXFWLRQFRXQWVGRZQZDUGRYHUDUDQJHRIWR(DFKWLPHWKHUXQJJRHVIURPIDOVHWRWUXHWKH&7'

LQVWUXFWLRQGHFUHPHQWVWKHDFFXPXODWHGYDOXHE\RQHFRXQW7KH

GRQHELW'1LVVHWDVORQJDVWKHDFFXPXODWHGYDOXHLVJUHDWHUWKDQRUHTXDOWRWKHSUHVHWYDOXH:KHQWKHDFFXPXODWHGYDOXHLVOHVVWKDQWKH

SUHVHWYDOXHWKHGRQHELW'1LVUHVHWZKLFK\RXUODGGHUSURJUDPFDQ

XVHWRLQLWLDWHVRPHDFWLRQVXFKDVFRQWUROOLQJDVWRUDJHELWRUDQ

RXWSXWGHYLFH

7KHDFFXPXODWHGYDOXHRIDFRXQWHULVUHWHQWLYH7KHFRXQWLVUHWDLQHG

XQWLOUHVHWE\DUHVHWLQVWUXFWLRQ5(6WKDWKDVWKHVDPHDGGUHVVDV

WKH&7'LQVWUXFWLRQ

Using Status Bits

([DPLQHVWDWXVELWVLQWKHODGGHUSURJUDPWRWULJJHUVRPHHYHQW7KHSURFHVVRUFKDQJHVWKHVWDWHVRIVWDWXVELWVZKHQWKHSURFHVVRUUXQV

WKLVLQVWUXFWLRQ


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Figure 2.9Example CTD Ladder Diagram

Figure 2.10Example CTD Timing Diagram

CD

CTD

COUNT DOWN

CounterPreset

Accum

C5:04

8

DN

C5:0

DN


I:012

10

C5:0

UN

O:021Tells when the counter underflows -32,768

RES

I:017

12

C5:0Resets the counter

01

02

Each time the input goes from false to true,the processor decrements the counter by 1.

87

65

43

016637

Counter preset = 4 countsCounter accumulated = 8

Rung condition thatcontrols counter

Rung condition that

controls reset instruction

Done Bit

Output instruction on rungcontrolled by counter

Counter Accumulated Value

ON

OFF

Count-up enable bit


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Figure 2.11Example CTU and CTD Logic Diagram

Figure 2.12Example CTU and CTD Timing Diagram

CD

CTD

COUNT DOWN

CounterPreset

Accum

C5:04

0DN

C5:0

DN


I:012

11

C5:0

UN

Tells when the counter underflows -32,768

RES

I:017

12


CU

CTU

COUNT UP

Counter

PresetAccum

C5:0

40

DN

I:012

10

C5:0

OV

Tells when the counter overflows +32,767 O:013

O:013

01

02

03

Count up pushbutton

Count down pushbutton

01 2

34

3

2 10

1 2

34

5

Count Up Pushbutton

Count Down Pushbutton

Reset Pulse

Done Bit

Counter Accumulated ValueCount Up Preset = 4Count Down Preset = 4

16652

ON

OFF

ON

OFF

ON

OFF

ON

OFF


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Timer and Counter Reset (RES)

Description: 7KH5(6LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWUHVHWVDWLPHURUFRXQWHU7KH5(6LQVWUXFWLRQH[HFXWHVZKHQLWVUXQJLVWUXH

,IWKHFRXQWHUUXQJLVHQDEOHGWKH&8RU&'ELWZLOOEHUHVHWDVORQJ

DVWKH5(6LQVWUXFWLRQLVHQDEOHG,PSRUWDQW or = PRE)

I:012

10

RES

I:017

12


01

Each time the input goes from false to true, theprocessor decrements the counter by 1.


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Chapter 3

Compare Instructions CMP, EQU, GEQ,

GRT, LEQ, LES, LIM, MEQ, NEQUsing Compare Instructions 7KHFRPSDULVRQLQVWUXFWLRQVOHW\RXFRPSDUHYDOXHVXVLQJDQ

H[SUHVVLRQRUDVSHFLILFFRPSDULVRQLQVWUXFWLRQ7DEOH$OLVWVWKH

DYDLODEOHFRPSDUHLQVWUXFWLRQV

Table 3.AAvailable Compare Instructions

,PSRUWDQW


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3-2 Compare Instructions CMP, EQU, GEQ, GRT, LEQ, LES, LIM, MEQ, NEQ

Using Arithmetic Status Flags 7KHDULWKPHWLFVWDWXVIODJVDUHLQZRUGELWVLQWKHSURFHVVRUVWDWXVILOH60RQLWRUWKHVHELWVLI\RXSHUIRUPDQDULWKPHWLF

IXQFWLRQZLWKLQWKH&03LQVWUXFWLRQ7DEOH%OLVWVWKHVWDWXVELWV

Table 3.BArithmetic Status Bits

Compare (CMP) 7KH&03LQVWUXFWLRQFRPSDUHVYDOXHVDQGSHUIRUPVORJLFDOFRPSDULVRQV

Description: 7KH&03LQVWUXFWLRQLVDQLQSXWLQVWUXFWLRQWKDWSHUIRUPVDFRPSDULVRQRQDULWKPHWLFRSHUDWLRQV\RXVSHFLI\LQWKHH[SUHVVLRQ

:KHQWKHSURFHVVRUILQGVWKHH[SUHVVLRQLVWUXHWKHUXQJJRHVWUXH

2WKHUZLVHWKHUXQJLVIDOVH:LWK(QKDQFHG3/&SURFHVVRUV\RX

FDQHQWHUPXOWLSOHRSHUDQGVFRPSOH[H[SUHVVLRQ

7KHH[HFXWLRQWLPHRID&03LQVWUXFWLRQLVORQJHUWKDQWKHH[HFXWLRQ

WLPHRIRQHRIWKHRWKHUFRPSDULVRQLQVWUXFWLRQVHJ*57/(4

HWF$&03LQVWUXFWLRQDOVRXVHVPRUHZRUGVLQ\RXUSURJUDPILOH

WKDQWKHFRUUHVSRQGLQJFRPSDULVRQLQVWUXFWLRQ

Entering the CMP Expression

7KHH[SUHVVLRQGHILQHVWKHRSHUDWLRQV\RXZDQWWRSHUIRUP'HILQH

WKHH[SUHVVLRQZLWKRSHUDWRUVDQGDGGUHVVHVRUSURJUDPFRQVWDQWV

:LWK(QKDQFHG3/&SURFHVVRUV\RXFDQHQWHUFRPSOH[

H[SUHVVLRQV7DEOH&OLVWVYDOLGRSHUDWLRQVIRUDQH[SUHVVLRQWKH

IROORZLQJOLVWSURYLGHVJXLGHOLQHVIRUZULWLQJH[SUHVVLRQV

2SHUDWRUVV\PEROVGHILQHWKHRSHUDWLRQV

$GGUHVVHVFDQEHGLUHFWLQGLUHFWRULQGH[HGDGGUHVVHVPXVWEHZRUGOHYHO

:LWK(QKDQFHG3/&SURFHVVRUVSURJUDPFRQVWDQWVFDQEH

LQWHJHURUIORDWLQJSRLQWQXPEHUVLI\RXHQWHURFWDOYDOXHVXVHDOHDGLQJ2LI\RXHQWHUKH[DGHFLPDOYDOXHVXVHDOHDGLQJ+LI\RXHQWHUELQDU\YDOXHVXVHDOHDGLQJ%

This Bit: Description:

S:0/0 Carry (C)

S:0/1 Overflow (V)

S:0/2 Zero (Z)

S:0/3 Sign (S)

CMP

COMPARE

Expression


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Compare Instructions CMP, EQU, GEQ, GRT, LEQ, LES, LIM, MEQ, NEQ 3-3

Table 3.CValid Operations for Use in a CMP Expression

Determining the Length of an Expression

(QKDQFHG3/&SURFHVVRUVVXSSRUWFRPSOH[LQVWUXFWLRQVXSWRD

WRWDORIFKDUDFWHUVLQFOXGLQJVSDFHVDQGSDUHQWKHVHV'HSHQGLQJ

RQWKHRSHUDWRUWKHSURFHVVRULQVHUWVFKDUDFWHUVEHIRUHDIWHUWKH

RSHUDWRULQ\RXUH[SUHVVLRQWRIRUPDWWKHH[SUHVVLRQIRUHDVLHU

LQWHUSUHWDWLRQ8VH7DEOH'WRGHWHUPLQHWKHQXPEHURIFKDUDFWHUV

HDFKRSHUDWRUXVHVLQDQH[SUHVVLRQ

,PSRUWDQW= greater than or equal to if A >= B, then ...

Arithmetic + add 2 + 3 Enhanced PLC-5 processor:2 + 3 + 7

subtract 12 5

* multiply 5 * 2 PLC-5/30, -5/40, -5/60,-5/80: 6 * (5 * 2)

| (vertical bar) divide 24 | 6

negate N7:0

SQR square root SQR N7:0

** exponential(x to the power of y)

10**3(Enhanced PLC-5 processors only)

Conversion FRD convert from BCDto binary

FRD N7:0

TOD convert from binaryto BCD

TOD N7:0


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:LWKWKH&03LQVWUXFWLRQDPD[LPXPRIFKDUDFWHUVRIWKH

H[SUHVVLRQFDQEHGLVSOD\HG,IWKHH[SUHVVLRQ\RXHQWHULVQHDUWKLV

FKDUDFWHUPD[LPXPZKHQ\RXDFFHSWWKHUXQJFRQWDLQLQJWKH

LQVWUXFWLRQWKHSURFHVVRUPD\H[SDQGLWEH\RQGFKDUDFWHUV:KHQ

\RXWU\WRHGLWWKHH[SUHVVLRQRQO\WKHILUVWFKDUDFWHUVDUH

GLVSOD\HGDQGWKHUXQJLVGLVSOD\HGDVDQHUURUUXQJ7KHSURFHVVRUGRHVFRQWDLQWKHFRPSOHWHH[SUHVVLRQKRZHYHUDQGWKHLQVWUXFWLRQ

UXQVSURSHUO\

7RDYRLGWKLVGLVSOD\SUREOHPH[SRUWWKHSURFHVVRUPHPRU\ILOHDQG

PDNH\RXUHGLWVLQWKH3&WH[WILOH7KHQLPSRUWWKLVWH[WILOH)RU

PRUHLQIRUPDWLRQRQLPSRUWLQJH[SRUWLQJSURFHVVRUPHPRU\ILOHVVHH

\RXUSURJUDPPLQJPDQXDO

Table 3.DCharacter Lengths for Operators

Example:

)RUPRUHLQIRUPDWLRQRQHQWHULQJFRPSOH[H[SUHVVLRQVVHHFKDSWHU

This Operation: Using this Operator:Uses this Number

of Characters:

math binary +, , *, | 3

OR, ** 4

AND, XOR 5

math unary (negate) 2

LN 3

FRD, TOD, DEG, RAD, SQR, NOT, LOG, SIN,COS, TAN, ASN, ACS, ATN

4

comparative =, 3

, = 4

CMP

COMPARE

Expression

(N7:0 + N7:1) > (N7:2 + N7:3)

O:013

01

The CMP instruction tells an Enhanced PLC-5 processor: if the sum of the values in N7:0 and N7:1 is greater than the sum of thevalues in N7:2 and N7:3, set output bit O:013/01. (The total number of characters used in this expressions is 3.)


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Equal to (EQU)

Description: 8VHWKH(48LQVWUXFWLRQWRWHVWZKHWKHUWZRYDOXHVDUHHTXDO6RXUFH $DQG6RXUFH%FDQHLWKHUEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQ

YDOXHV

Example:

)ORDWLQJSRLQWYDOXHVDUHUDUHO\DEVROXWHO\HTXDO,I\RXQHHGWR

GHWHUPLQHWKHHTXDOLW\RIIORDWLQJSRLQWYDOXHVXVHWKH/,0

LQVWUXFWLRQLQVWHDGRIWKH(48)RULQIRUPDWLRQRQWKH/,0

LQVWUXFWLRQVHHSDJH

Greater than or Equal to (GEQ)

Description: 8VHWKH*(4LQVWUXFWLRQWRWHVWZKHWKHURQHYDOXH6RXUFH$LVJUHDWHUWKDQRUHTXDOWRDQRWKHUYDOXH6RXUFH%6RXUFH$DQG

6RXUFH%FDQEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQYDOXHV

Example:

EQU

EQUALSource A

Source B

EQU

EQUALSource ASource B

O:013

01N7:5N7:10

If the value in N7:5 is equal to the value in N7:10, set output bit O:013/01.

GEQ

GREATER THAN OR EQUAL

Source A

Source B

GEQ


Source A

Source B

O:013

01N7:5

N7:10

If the value in N7:5 is greater than or equal to the value in N7:10, set output bit O:013/01.


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Greater than (GRT)

Description: 8VHWKH*57LQVWUXFWLRQWRWHVWZKHWKHURQHYDOXH6RXUFH$LVJUHDWHUWKDQDQRWKHUYDOXH6RXUFH%6RXUFH$DQG6RXUFH%FDQ

HLWKHUEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQYDOXHV

Example:

Less than or Equal to (LEQ)

Description: 8VHWKH/(4LQVWUXFWLRQWRWHVWZKHWKHURQHYDOXH6RXUFH$LVOHVVWKDQRUHTXDOWRDQRWKHUYDOXH6RXUFH%6RXUFH$DQG6RXUFH%FDQ

HLWKHUEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQYDOXHV

Example:

GRT


Source A

Source B

GRT

GREATER THAN

Source A

Source B

O:013

01N7:5

N7:10

If the value in N7:5 is greater than the value in N7:10, set output bit O:013/01.

LEQ

LESS THAN OR EQUAL

Source A

Source B

LEQ

LESS THAN OR EQUAL

Source A

Source B

O:013

01N7:5

N7:10

If the value in N7:5 is less than or equal to the value in N7:10, set output bit O:013/01.


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Less than (LES)

Description: 8VHWKH/(6LQVWUXFWLRQWRWHVWZKHWKHURQHYDOXH6RXUFH$LVOHVVWKDQDQRWKHUYDOXH6RXUFH%6RXUFH$DQG6RXUFH%FDQEHYDOXHV

RUDGGUHVVHVWKDWFRQWDLQYDOXHV

Example:

Limit Test (LIM)

Description: 7KH/,0LQVWUXFWLRQLVDQLQSXWLQVWUXFWLRQWKDWWHVWVIRUYDOXHVLQVLGHRIRURXWVLGHRIDVSHFLILHGUDQJH7KHLQVWUXFWLRQLVIDOVHXQWLOLW

GHWHFWVWKDWWKHWHVWYDOXHLVZLWKLQFHUWDLQOLPLWV7KHQWKHLQVWUXFWLRQ

JRHVWUXH:KHQWKHLQVWUXFWLRQGHWHFWVWKDWWKHWHVWYDOXHJRHVRXWVLGH

FHUWDLQOLPLWVLWJRHVIDOVH


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LIM Example Using Integer: ,IYDOXH/RZ/LPLWYDOXH+LJK/LPLW:KHQWKHSURFHVVRUGHWHFWVWKDWWKHYDOXHRI%7HVWLVHTXDOWRRUEHWZHHQOLPLWVWKHLQVWUXFWLRQLVWUXHLIYDOXH7HVWLVRXWVLGHWKHOLPLWVWKHLQVWUXFWLRQLVIDOVH

,IYDOXH/RZ/LPLWYDOXH+LJK/LPLW:KHQWKHSURFHVVRUGHWHFWVWKDWWKHYDOXHRI7HVWLVHTXDOWRRURXWVLGHWKHOLPLWVWKHLQVWUXFWLRQLVWUXHLIYDOXH7HVWLVEHWZHHQEXWQRWHTXDOWRHLWKHUOLPLWWKHLQVWUXFWLRQLVIDOVH

Example (when the Low Limit is lessthan the High Limit):

false < - - - - - - - t rue- - - - - - > false

A C. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .< value B >

from -32,768 to +32,767

true < - -- -- - false- -- -- - > true. . . . . . . . . . . . C A . . . . . . . . . . . .from -32,768 to +32,767

value B < < value B

LIM

LIMIT TEST (CIRC)

Low lim

Test

O:013

01N7:10

N7:15

High lim N7:20

If the value in N7:15 is greater than or equal to the value in N7:10 and less than or equal to the value inN7:20, set output bit O:013/01.


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Mask Compare Equal to (MEQ)

Description: 7KH0(4LQVWUXFWLRQLVDQLQSXWLQVWUXFWLRQWKDWFRPSDUHVDYDOXHIURPDVRXUFHDGGUHVVZLWKGDWDDWDFRPSDUHDGGUHVVDQGDOORZV

SRUWLRQVRIWKHGDWDWREHPDVNHG,IWKHGDWDDWWKHVRXUFHDGGUHVV

PDWFKHVWKHGDWDDWWKHFRPSDUHDGGUHVVELWE\ELWOHVVPDVNHGELWVWKHLQVWUXFWLRQLVWUXH7KHLQVWUXFWLRQJRHVIDOVHDVVRRQDVLWGHWHFWVD

PLVPDWFK


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Not Equal to (NEQ)

Description: 8VHWKH1(4LQVWUXFWLRQWRWHVWZKHWKHUWZRYDOXHVDUHQRWHTXDO6RXUFH$DQG6RXUFH%FDQEHYDOXHVRUDGGUHVVHV

Example:

NEQ

NOT EQUAL

Source A

Source B

NEQ

NOT EQUAL

Source A

Source B

O:013

01N7:5

N7:10

If the value in N7:5 is not equal to the value in N7:10, set output bit O:013/01.


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Chapter 4

Compute Instructions CPT, ACS, ADD,

ASN, ATN, AVE, CLR, COS, DIV, LN, LOG,MUL, NEG, SIN, SRT, SQR, STD, SUB,

TAN, XPY

Using Compute Instructions 7KHFRPSXWHLQVWUXFWLRQVHYDOXDWHDULWKPHWLFRSHUDWLRQVXVLQJDQH[SUHVVLRQRUDVSHFLILFDULWKPHWLFLQVWUXFWLRQ7DEOH$OLVWVWKH

DYDLODEOHFRPSXWHLQVWUXFWLRQV

Table 4.AAvailable Compute Instructions

If You Want to:Use this

Instruction:

Found on

Page:

Evaluate an expression CPT 4-5

Take the arc cosine of a number ACS* 4-11

Add two values ADD 4-12

Take the arc sine of a number ASN* 4-13

Take the arc tangent of a number ATN* 4-14

Calculate the average for a set of values AVE* 4-15

Clear an address word (set al l bits to zero) CLR 4-17

Take the cosine of a number COS* 4-18

Divide two values DIV 4-19

Take the natural log of a number LN* 4-20

Take the log of a number LOG* 4-21

* Only Enhanced PLC-5 processors support this instruct ion.

(Continued)


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4-2 Compute Instructions CPT, ACS, ADD, ASN, ATN, AVE, CLR, COS, DIV, LN, LOG, MUL, NEG, SIN, SRT, SQR, STD, SUB, TAN, XPY

)RUPRUHLQIRUPDWLRQRQWKHRSHUDQGVDQGYDOLGGDWDW\SHVYDOXHVRI

HDFKRSHUDQGXVHGE\WKHLQVWUXFWLRQVGLVFXVVHGLQWKLVFKDSWHUVHH

$SSHQGL[&

Using Arithmetic Status Flags 7KHDULWKPHWLFVWDWXVIODJVDUHLQZRUGELWVLQWKHSURFHVVRUVWDWXVILOH67DEOH%OLVWVWKHVWDWXVELWV

Table 4.BArithmetic Status Bits

Multiply two values MUL 4-22

Take the opposite sign of a value NEG 4-23

Take the sine of a number SIN* 4-24

Take the square root of a value SQR 4-25

Sort a set of values into ascending order SRT* 4-26

Calculate the standard deviation for a set of values STD* 4-28

Subtract two values SUB 4-31

Take the tangent of a number TAN* 4-32

Raise a number to a power XPY* 4-33

* Only Enhanced PLC-5 processors support this instruct ion.

If You Want to:Use this

Instruction:

Found on

Page:

This Bit: Description:

S:0/0 Carry (C)

S:0/1 Overflow (V)

S:0/2 Zero (Z)

S:0/3 Sign (S)


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Compute Instructions CPT, ACS, ADD, ASN, ATN, AVE, CLR, COS, DIV, LN, LOG, MUL, NEG, SIN, SRT, SQR, STD, SUB, TAN, XPY 4-3

Data Types and the

Compute Instruction


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)RUH[DPSOHLI YDOXH1DQG1

YDOXH1DQG1

UHVXOW1DQG1

DQG\RXZDQWWRDGGYDOXHWRYDOXH\RXUODGGHUSURJUDPZRXOGEH

Using Floating Point Data Types )RUDQ(QKDQFHG3/&SURFHVVRULI\RXXVHIORDWLQJSRLQWGDWD

W\SHVDQGWKHUHVXOWLVWRRODUJHRULILWLVXQGHILQHGLHQDWXUDOORJRIWKHSURFHVVRUVHWVWKHRYHUIORZELW

,IWKHUHVXOWLWWRRODUJHD!+INF!LVGLVSOD\HGLIWKHUHVXOWWRWRR

VPDOOD!-INF!LVGLVSOD\HG,IWKHYDOXHLVQRWDQXPEHU!NAN!

LV GLVSOD\HG

,PSRUWDQW ,I\RXDUHXVLQJIORDWLQJSRLQWDQGWKHQXPEHULVJUHDWHU

WKDQRUOHVVWKDQ\RXPXVWXVHD

GHFLPDOSRLQW,I\RXGRQRWXVHDGHFLPDOSRLQWWKH

HUURUINVALID OPERAND DSSHDUV

:KHQ\RXXVHFRPSOH[H[SUHVVLRQVLIDQ\RSHUDQGLVIORDWLQJ

SRLQWWKHHQWLUHH[SUHVVLRQLVHYDOXDWHGDVIORDWLQJSRLQW6HHWKH

H[DPSOHLQWKH([SUHVVLRQ([DPSOHVVHFWLRQRQSDJHIRU

PRUHLQIRUPDWLRQ

]

ADD

ADD

Source ASource B

N7:1

ADD

ADD

Source A

I:012

10 N7:1N7:3

Dest N7:5

]

ADD

ADD

Source A

Source B N7:4

N7:4

ADD

N7:0

ADD

ADD

Source A

Source B N7:4Dest N7:4

ADD

N7:2

ADD

BITWISE AND

Source A

1Dest N7:4

AND

Source A

Source B

S:0

Add the lower words of value1 and value2.

Capture the carry bit.

Add the high word of value1 to the carry bit.

Add the high word of value2 to this sum.

]

I:012

10

]

]

I:012

10

]

]

I:012

10

]

Dest


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Compute (CPT) 7KH&37LQVWUXFWLRQSHUIRUPVFRS\DULWKPHWLFORJLFDODQGFRQYHUVLRQRSHUDWLRQV

Description: 7KH&37LQVWUXFWLRQLVDQRXWSXWLQVWUXFWLRQWKDWSHUIRUPVWKHRSHUDWLRQV\RXGHILQHLQWKHH[SUHVVLRQDQGZULWHVWKHUHVXOWLQWRWKH

GHVWLQDWLRQDGGUHVV7KH&37LQVWUXFWLRQFDQDOVRFRS\GDWDIURPRQHDGGUHVVWRDQRWKHUDQGDXWRPDWLFDOO\FRQYHUWVWKHGDWDW\SHDWWKH

VRXUFHDGGUHVVWRWKHGDWDW\SH\RXVSHFLI\LQWKHGHVWLQDWLRQDGGUHVV

7KHH[HFXWLRQWLPHRID&37LQVWUXFWLRQLVORQJHUWKDQWKHH[HFXWLRQ

WLPHRIDQDULWKPHWLFORJLFRUPRYHLQVWUXFWLRQLH$''$1'

029HWF7KH&37LQVWUXFWLRQDOVRXVHVPRUHZRUGVLQ\RXU

SURJUDPILOH

$IWHUHDFK&37LQVWUXFWLRQLVSHUIRUPHGWKHDULWKPHWLFVWDWXVELWVLQ

WKHVWDWXVILOHRIWKHGDWDWDEOHDUHXSGDWHGWKHVDPHDVWKH

FRUUHVSRQGLQJDULWKPHWLFORJLFRUPRYHLQVWUXFWLRQ)RUH[DPSOH

UHIHUWRWKHGHVFULSWLRQRIWKH$''LQVWUXFWLRQWRVHHKRZWKHVWDWXV

ELWVDUHXSGDWHGDIWHUD&37DGGLQVWUXFWLRQLVH[HFXWHG

Entering the CPT Expression

7KHH[SUHVVLRQGHILQHVWKHRSHUDWLRQV\RXZDQWWRSHUIRUP


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Table 4.CValid Operations for Use in a CPT Expression

Type Operator Description Example Operation

Copy none copy from A to B enter source address in the expression enter

destination address in destination

Clear none set a value to zero 0 (enter 0 for the expression)

Arithmetic + add 2 + 3

2 + 3 + 7 (Enhanced PLC-5 processors)

subtract 12 5

(12 5) 7 (Enhanced PLC-5 processors)

* multiply 5 * 2

6 * (5 * 2) (Enhanced PLC-5 processors)

| (vertical bar) divide 24 | 6

(24 | 6) *2 (Enhanced PLC-5 processors)

negate N7:0

SQR square root SQR N7:0

** exponential *(x to the power of y)

10**3

LN natural log * LN F8:20

LOG log to the base 10* LOG F8:3

Trigonometric ACS arc cosine* ACS F8:18

ASN arc sine* ASN F8:20

ATN arc tangent * ATN F8:22

COS cosine* COS F8:14

SIN sine* SIN F8:12

TAN tangent* TAN F8:16

Bitwise AND bitwise AND D9:3 AND D10:4

OR bitwise OR D10:4 OR D10:5

XOR bitwise exclusive OR D9:5 XOR D10:4

NOT bitwise complement NOT D9:3

Conversion FRD convert from BCDto binary

FRD N7:0

TOD convert from binaryto BCD

TOD N7:0

DEG convert radiansto degrees*

DEG F8:8

RAD convert degreesto radians*

RAD F8:10

* Available in Enhanced PLC-5 processors only.


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Determining the Length of an Expression

:LWK(QKDQFHG3/&SURFHVVRUV\RXFDQHQWHUFRPSOH[LQVWUXFWLRQV

XSWRDWRWDORIFKDUDFWHUVLQFOXGLQJVSDFHVDQGSDUHQWKHVHV

'HSHQGLQJRQWKHRSHUDWRUWKHSURFHVVRULQVHUWVFKDUDFWHUV

EHIRUHDIWHUWKHRSHUDWRULQ\RXUH[SUHVVLRQWRIRUPDWWKHH[SUHVVLRQ

IRUHDVLHULQWHUSUHWDWLRQ8VH7DEOH'EHORZWRGHWHUPLQHWKH

QXPEHURIFKDUDFWHUVHDFKRSHUDWRUXVHVLQDQH[SUHVVLRQ

:LWKWKH&37LQVWUXFWLRQDPD[LPXPRIFKDUDFWHUVRIWKH

H[SUHVVLRQDUHGLVSOD\DEOH,IWKHH[SUHVVLRQ\RXHQWHULVQHDUWKLV

FKDUDFWHUPD[LPXPZKHQ\RXDFFHSWWKHUXQJFRQWDLQLQJWKH

LQVWUXFWLRQWKHSURFHVVRUPD\H[SDQGLWEH\RQGFKDUDFWHUV:KHQ

\RXWU\WRHGLWWKHH[SUHVVLRQRQO\WKHILUVWFKDUDFWHUVDUH

GLVSOD\HGDQGWKHUXQJLVGLVSOD\HGDVDQHUURUUXQJ7KHSURFHVVRU

GRHVFRQWDLQWKHFRPSOHWHH[SUHVVLRQKRZHYHUDQGWKHLQVWUXFWLRQ

UXQVSURSHUO\

7RZRUNDURXQGWKLVGLVSOD\SUREOHPH[SRUWWKHSURFHVVRUPHPRU\ILOHDQGPDNH\RXUHGLWVLQWKH3&WH[WILOH7KHQLPSRUWWKLV

WH[W ILOH

,PSRUWDQW


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Determining the Order of Operation

7KHRSHUDWLRQV\RXZULWHLQWRWKHH[SUHVVLRQDUHSHUIRUPHGE\WKH

SURFHVVRULQDSUHVFULEHGRUGHUQRWQHFHVVDULO\WKHRUGHU\RXZULWH

WKHP


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Example:

:KHQ\RXXVHFRPSOH[H[SUHVVLRQVLIDQ\RSHUDQGLVIORDWLQJSRLQW

WKHHQWLUHH[SUHVVLRQLVHYDOXDWHGDVIORDWLQJSRLQW

Example:

Entering the Destination(QWHUDGLUHFWRULQGLUHFWORJLFDODGGUHVVIRUWKHGHVWLQDWLRQ7KH

LQVWUXFWLRQVWRUHVWKHUHVXOWRIWKHRSHUDWLRQLQWKHGHVWLQDWLRQDGGUHVV

,PSRUWDQW7KHSURFHVVRUDXWRPDWLFDOO\FRQYHUWVWKHGDWDW\SH

VSHFLILHGE\WKHVRXUFHDGGUHVVWRWKDWVSHFLILHGE\WKH

GHVWLQDWLRQDGGUHVV7KHSURFHVVRUXVHV%&'IRUGLVSOD\

RUFRPSDWLELOLW\ZLWK3/&IDPLO\SURFHVVRUV


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7KHLQVWUXFWLRQSHUIRUPVWKHIXQFWLRQV\RXVSHFLI\EDVHGRQD

PQHPRQLF:KHQ\RXHQWHUWKHH[SUHVVLRQHQWHUWKHPQHPRQLFDV

WKHSUHIL[WRWKHDGGUHVVRIWKHYDOXHRQZKLFK\RXZDQWWRRSHUDWHRU

DVDSUHIL[WRWKHYDOXHLWVHOIZKHQHQWHUHGDVDSURJUDPFRQVWDQW

,PSRUWDQW)ORDWLQJSRLQWQXPEHUVDUHELWYDOXHV,QWHJHUVDUH

ELWYDOXHV7KHLQVWUXFWLRQDXWRPDWLFDOO\FRQYHUWVWKHGDWDW\SHVIRXQGLQWKHH[SUHVVLRQWRWKHGDWDW\SH

VSHFLILHGE\WKHGHVWLQDWLRQDGGUHVV

7DEOH)OLVWVWKH&37IXQFWLRQV\RXFDQXVH

Table 4.FCPT Functions for Number Conversion


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Arc Cosine (ACS)

(Enhanced PLC-5 Processors Only)

Description: 8VHWKH$&6LQVWUXFWLRQWRWDNHWKHDUFFRVLQHRIWKHVRXUFHLQUDGLDQVDQGVWRUHWKHUHVXOWLQUDGLDQVLQWKH'HVWLQDWLRQ6HH7DEOH

*IRUVWDWXVIODJVIRUWKH$&6LQVWUXFWLRQ

7KH6RXUFHPXVWEHJUHDWHUWKDQRUHTXDOWRDQGOHVVWKDQRU

HTXDOWR,ILWLVQRWLQWKLVUDQJHWKHSURFHVVRUUHWXUQVD!NAN!

UHVXOWLQWKH'HVWLQDWLRQ7KHUHVXOWLQJYDOXHLQWKH'HVWLQDWLRQLV

DOZD\VJUHDWHUWKDQRUHTXDOWRDQGOHVVWKDQRUHTXDOWRZKHUH

Table 4.GUpdating Arithmetic Status Flags for an ACS Instruction

Example:

ACS

ARCCOSINE

Source

Destination

With this Bit: The Processor:

Carry (C) always resets

Overflow (V) sets if overflow generated; otherwise resets

Zero (Z) sets i f result is zero; otherwise resets

Sign (S) always resets

]

ACSARCCOSINE

Source

I:012

10F8:19

Destination F8:20

]

0.7853982

0.6674572

If input word 12, bit 10 is set, take the arc cosine of the value in F8:19 and store the result in F8:20.


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Addition (ADD)

Description: 8VHWKH$''LQVWUXFWLRQWRDGGRQHYDOXH6RXUFH$WRDQRWKHUYDOXH6RXUFH%DQGSODFHWKHUHVXOWLQWKHGHVWLQDWLRQ6RXUFH$DQG

6RXUFH%FDQHLWKHUEHYDOXHVRUDGGUHVVHVWKDWFRQWDLQYDOXHV6HH

7DEOH+IRUVWDWXVIODJVIRUWKH$''LQVWUXFWLRQ

,PSRUWDQW7KH$''LQVWUXFWLRQH[HFXWHVRQFHHDFKVFDQDVORQJDV

WKHUXQJLVWUXHLI\RXRQO\ZDQWYDOXHVDGGHGRQFH

LQFOXGHWKH216FRPPDQGVHHFKDSWHU

Table 4.HUpdating Arithmetic Status Flags for an ADD Instruction

Example:

ADD

ADDSource A

Source B

Destination


Carry (C) sets if carry generated; otherwise resets



Sign (S) sets i f result is negative; otherwise resets

]

ADD

ADD

Source A

Source B

I:012

10 N7:3

N7:4

Destination N7:20

]

If input word 12, bit 10 is set, add the value in N7:3 to the value in N7:4 and store the result in N7:20.


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Arc Sine (ASN)


Description: 8VHWKH$61LQVWUXFWLRQWRWDNHWKHDUFVLQHWKHVRXUFHLQUDGLDQVDQGVWRUHWKHUHVXOWLQUDGLDQVLQWKH'HVWLQDWLRQ6HH7DEOH,IRU

VWDWXVIODJVIRU$61LQVWUXFWLRQ

7KH6RXUFHPXVWEHJUHDWHUWKDQRUHTXDOWRDQGOHVVWKDQRU

HTXDOWR,ILWLVQRWLQWKLVUDQJHWKHSURFHVVRUUHWXUQVD!NAN!

UHVXOWLQWKH'HVWLQDWLRQ7KHUHVXOWLQJYDOXHLQWKH'HVWLQDWLRQLV

DOZD\VJUHDWHUWKDQRUHTXDOWRDQGOHVVWKDQRUHTXDOWR/2ZKHUH

Table 4.IUpdating Arithmetic Status Flags for an ASN Instruction

Example:

ASNARCSINE

Source

Destination






]

ASN

ARCSINE

Source

I:012

10 F8:17

Dest F8:18

]

0.7853982

0.9033391

If input word 12, bit 10 is set, take the arc sine of the value in F8:17 and store the result in F8:18.


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Arc Tangent (ATN)


Description: 8VHWKH$71LQVWUXFWLRQWRWDNHWKHDUFWDQJHQWRIWKHVRXUFHLQUDGLDQVDQGVWRUHWKHUHVXOWLQUDGLDQVLQWKH'HVWLQDWLRQ7KH

UHVXOWLQJYDOXHLQWKH'HVWLQDWLRQLVDOZD\VJUHDWHUWKDQRU

HTXDOWRDQGOHVVWKDQRUHTXDOWR/2ZKHUH6HH7DEOH-IRUVWDWXVIODJVIRU$71LQVWUXFWLRQ

Table 4.JUpdating Arithmetic Status Flags for an ATN Instruction

Example:

ATN

ARCTANGENT

Source

Destination






]

ATN

ARCTANGENT

Source

I:012

10 F8:21

Destination F8:22

]

0.7853982

0.6657737

If input word 12, bit 10 is set, take the arc tangent of the value in F8:21 and store the result in F8:22.


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Average File (AVE)


Description: 7KH$9(LQVWUXFWLRQFDOFXODWHVWKHDYHUDJHRIDVHWRIYDOXHV:KHQWKHUXQJJRHVIURPIDOVHWRWUXHWKHYDOXHDWWKHFXUUHQWSRVLWLRQLV

DGGHGWRWKHQH[WYDOXHZKLFKLVDGGHGWRWKHQH[WYDOXHDQGVRRQ

6HH7DEOH.IRUVWDWXVIODJVIRU$9(LQVWUXFWLRQ

(DFKWLPHDQRWKHUYDOXHLVDGGHGWKHSRVLWLRQILHOGDQGWKHVWDWXV

ZRUG6LVLQFUHPHQWHG7KHILQDOVXPLVGLYLGHGE\WKHQXPEHU

RIYDOXHVDGGHGDQGWKHUHVXOWLVVWRUHGLQWKHGHVWLQDWLRQ

Table 4.KUpdating Arithmetic Status Flags for an AVE Instruction

$QRYHUIORZFDQRFFXULI

WKHLQWHUPHGLDWHVXPH[FHHGVWKHPD[LPXPIORDWLQJSRLQWYDOXH

WKHGHVWLQDWLRQLVDQLQWHJHUDGGUHVVDQGWKHILQDOYDOXHLVJUHDWHUWKDQRUOHVVWKDQ

,IDQRYHUIORZRFFXUVWKHSURFHVVRUVWRSVWKHFDOFXODWLRQVHWVWKH(5

ELWDQGWKH'HVWLQDWLRQUHPDLQVXQFKDQJHG7KHSRVLWLRQLGHQWLILHV

WKHHOHPHQWWKDWFDXVHGWKHRYHUIORZ:KHQ\RXFOHDUWKH(5ELWWKH

SRVLWLRQUHVHWVWRDQGWKHDYHUDJHLVUHFDOFXODWHG

,PSRUWDQW8VHWKH5(6LQVWUXFWLRQWRFOHDUWKHVWDWXVIODJV

Entering Parameters

7RSURJUDPWKH$9(LQVWUXFWLRQ\RXPXVWSURYLGHWKHSURFHVVRU

ZLWKWKHIROORZLQJ

)LOHLVWKHDGGUHVVWKDWFRQWDLQVWKHILUVWYDOXHWREHDGGHG7KLVDGGUHVVFDQEHIORDWLQJSRLQWRULQWHJHU

'HVWLQDWLRQLVWKHDGGUHVVZKHUHWKHUHVXOWRIWKHLQVWUXFWLRQLVVWRUHG7KLVDGGUHVVFDQEHIORDWLQJSRLQWRULQWHJHU

&RQWUROLVWKHDGGUHVVRIWKHFRQWUROVWUXFWXUHLQWKHFRQWURODUHD5RISURFHVVRUPHPRU\7KHSURFHVVRUVWRUHVLQIRUPDWLRQVXFKDVWKHOHQJWKSRVLWLRQDQGVWDWXVDQGXVHVWKLVLQIRUPDWLRQWRH[HFXWHWKHLQVWUXFWLRQ

/HQJWKLVWKHQXPEHURIZRUGVLQWKHILOH

3RVLWLRQSRLQWVWRWKHZRUGWKDWWKHLQVWUXFWLRQLVFXUUHQWO\XVLQJ

AVEAVERAGE FILE

ControlLength

Destination

Position

FileEN

DN







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Using Status Bits

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FRQWUROVWUXFWXUH$GGUHVVWKHVHELWVE\PQHPRQLF

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Example:

This Bit: Is Set:

Enable .EN (bit 15) on a false-to-true rung transition to indicate that the instructionis enabled. The instruction follows the rung condition.

Done .DN (bit 13) after the instruction finishes operating. After the rung goesfalse, the processor resets the .DN bit on the next false-to-truerung transition.

Error .ER (bit 11) when the operation generates an overflow. The instructionstops until the ladder program resets the .ER bit.

$77(17,21 7KH$9(LQVWUXFWLRQLQFUHPHQWVWKH

RIIVHWYDOXHVWRUHGDW60DNHVXUH\RXPRQLWRURU

ORDGWKHRIIVHWYDOXH\RXZDQWSULRUWRXVLQJDQLQGH[HG

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FRXOGRFFXUZLWKSRVVLEOHGDPDJHWRHTXLSPHQWDQGRU

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]

AVE

AVERAGE FILE

File

Dest

I:012

10 #N7:1

N7:0

Control R6:0

]

Length

Position

4

0

]

R6:0

EN

]O:010

5

]

R6:0

DN

]O:010

7

EN

DN

RES

R6:0

If input word 12, bit 10 is set, the AVE instruction is enabled. The values in N7:1, N7:2, N7:3, and N7:4 areadded together and divided by 4. The result is stored in N7:0. When the calculation is complete, outputword 10, bit 7 is set. Then the RES instruction resets the status bits of the control file R6:0.


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Clear (CLR)

Description: 8VHWKH&/5LQVWUXFWLRQWRVHWDOOWKHELWVRIDZRUGWR]HUR7KHGHVWLQDWLRQPXVWEHDZRUGDGGUHVV6HH7DEOH/IRUVWDWXVIODJVIRU

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Table 4.LUpdating Arithmetic Status Flags for a CLR Instruction

Example:

CLR

CLEAR

Destination



Overflow (V) always resets

Zero (Z) always sets


]

CLR

CLEAR

Destination

I:012

10 N7:3

]

If input word 12, bit 10 is set, clear all of the bits in N7:3 to zero.


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Cosine (COS)


Description: 8VHWKH&26LQVWUXFWLRQWRWDNHWKHFRVLQHRIDQXPEHU6RXUFHLQUDGLDQVDQGVWRUHWKHUHVXOWLQWKH'HVWLQDWLRQ6HH7DEOH0IRU

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7KH6RXUFHPXVWEHJUHDWHUWKDQRUHTXDOWRDQGOHVVWKDQ

RUHTXDOWR,ILWLVQRWLQWKLVUDQJHWK

Instruction Set Reference [by Bradley]

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