INSTRUCTION PIPELINGin TMS320C55x

VARUN Kvarunkpa@gmail.com

Pipe line operation

• In computers, a pipeline is the continuous and somewhat overlapped movement of instruction to the processor

• Without a pipeline, a computer processor gets the first instruction from memory, performs the operation it calls for, and then goes to get the next instruction from memory, and so forth.

• Improvement in 4 stage pipeline. One instruction=0.25 clocks

Pipe line operation

• Fetch: Fetches the instruction from memory and updates program counter.

• Decode:Decoding+address generation+ARAU updates

• Read: Operand reading,ARUP:read the memory location before the update of previous decode

• Execute: Specific operation, write back

Pipe line operation

• ADD*+• SAMM TREG0• MPY*+• SQRA *+,AR2

Pipe line operationCYCLE PC FETCH DECODE READ EXECUTE

1 [SAMM] ADD

2 [MPY] SAMM ADD

3 [SQRA] MPY SAMM ADD

4 SQRA MPY SAMM ADD

5 SQRA MPY SAMM

6 SQRA MPY

7 SQRA

PIPELINE WITH BRANCH INSTRUCTIONS• Branch instruction takes 2 cycles(no branch occurs).1-

to enter execute phase 2-fetching branch address• 4 cycles (when branching). 1-to enter execute phase 2-

fetching branch address3,4-flushing the unnecessary instructions.

• ZAP• B pgm 1250H• ADD*• SACL *+• MAC 4500H,25H• Pgm 1250h: LACC*+

Pipe line operationCYCLE PC FETCH DECODE READ EXECUTE

1 [B] ZAP2 [1250H] B ZAP3 [ADD*] 1250H B ZAP4 [SACL*+] ADD* Dummy B ZAP5 [LACC*+] SACL*+ Dummy Dummy B6 LACC*+ Dummy Dummy Dummy7 LACC*+ Dummy Dummy8 LACC*+ Dummy9

Pipeline with ARAU memory mapped registers

• Auxiliary register arithmetic unit updates of ARs occurs during the decode phase of the pipeline

• So AR update also happens in the decode phase• (164h)=90h,(165h)=80h,(166h)=60h,(167h)=40h,

(168h)=30h• LAR AR1,#167h• LACC #164h• SAMM AR1• LACC *+• ADD *+

Pipeline with ARAU memory mapped registers

CYCLE PC FETCH DECODE READ EXECUTE

1 [LACC] LAR

2 [164h] LACC LAR

3 [SAMM] 164h LACC LAR

4 [LACC] SAMM Dummy LACC LAR

5 [ADD] LACC SAMM Dummy LACC

6 ADD LACC SAMM Dummy

7 ADD LACC SAMM

8 ADD LACC

9 ADD

Pipeline with ARAU memory mapped registers

• We want to add [164h],[165h] and store the result in ACC

• But [167h]+[168h] happens; LACC ==167h• LACC=167h• ADD=168h

• The problem is solved by introducing two NOP instructions so that AR1 gets updated by executing SAMM prior to LACC decode

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