Institute of Electronics, National Chiao Tung University VLSI Signal Processing Lab A 242mW, 10mm2...

3
I n s t i t u t e o f E l e c t r o n i c s , N a t i o n a l C h i a o T u n g U n i v e r s i t y V L S I S i g n a l P r o c e s s i n g L a b A 242mW, 10mm2 H.264/AVC High Profile Encoder H.264 High Profile Encoder High Resolution Video (1920x1080) High Definiti on Camera Digital Video Broadcas t in Europe, Japan, ….. Blu-ray HD-DVD …… Motivat ion •Support H.264 high profile •Real time encoding 1920x1080 •Huge computing power and hardware •A low hardware cost H.264 high profile encoder Target

Transcript of Institute of Electronics, National Chiao Tung University VLSI Signal Processing Lab A 242mW, 10mm2...

Page 1: Institute of Electronics, National Chiao Tung University VLSI Signal Processing Lab A 242mW, 10mm2 H.264/AVC High Profile Encoder H.264 High Profile Encoder.

Institu

te of E

lectron

ics, Natio

nal C

hia

o T

ung

Un

iversity

VL

SI S

ign

al P

roc

es

sin

g L

ab

A 242mW, 10mm2 H.264/AVC High Profile Encoder

H.264 High Profile Encoder

High Resolution Video (1920x1080)

High Definition Camera

Digital Video Broadcast in Europe, Japan, …..

Blu-rayHD-DVD……

Motivation•Support H.264 high profile

•Real time encoding 1920x1080

•Huge computing power and hardware

•A low hardware cost H.264 high profile encoder

Target

Page 2: Institute of Electronics, National Chiao Tung University VLSI Signal Processing Lab A 242mW, 10mm2 H.264/AVC High Profile Encoder H.264 High Profile Encoder.

Institu

te of E

lectron

ics, Natio

nal C

hia

o T

ung

Un

iversity

VL

SI S

ign

al P

roc

es

sin

g L

ab

Features of Proposed Design

Processor

Bus Arbiter

Frame Memory

System Controller

Fractional ME

Rec.

Bitstream Buffer

MB Pipeline Stage 1

MB Pipeline Stage 2

MB Pipeline Stage 3

4x4/8x8 DCT & Q

Residue SRAM

Current Buffer

Integer ME

Intra-Predictor

Entropy

Rec. SRAM

Control SignalData Path

Modules for high profile

Deblocking

Ref. SRAM

•Parallelism enhancement

•Cross-stage hardware sharing

•Low complexity modules

•46% of area reduction

•32.6% of operating frequency reduction for 1280x720 video

•53.7 of power reduction for 1280x720 video

Key Techniques

Achievements

3 Stage Architecture

Page 3: Institute of Electronics, National Chiao Tung University VLSI Signal Processing Lab A 242mW, 10mm2 H.264/AVC High Profile Encoder H.264 High Profile Encoder.

Institu

te of E

lectron

ics, Natio

nal C

hia

o T

ung

Un

iversity

VL

SI S

ign

al P

roc

es

sin

g L

ab

Implementation Results

Process UMC 0.13μm 1P8M CMOS1.2V core, 3.3V I/O

Package CQFP 208-pin

Gate Count 593K

Internal memory 22KB

Chip Size 3.76x3.76mm2

Core Size 3.17x3.17mm2

Operating Frequency

145MHz@1080p/30fps62.5MHz@ 720p/30fps

Core Power Consumption

Baseline Profile:176.1mW@1080p/30fps/1.2V84.6mW @720p/30fps/1.2VHigh Profile:242. mW@1080p/30fps/1.2V116.61 mW@ 720p/30fps/1.2V

The output bit-stream is decodable